New Applications for CMP: Solving the Technical and ...€¦ · the Technical and Business...

New Applications for CMP: Solvingthe Technical and Business Challenges

Robert L. Rhoades, Ph.D.NSTI Conference (Houston, TX)May 5, 2009

Our Expertise, Our Services,Your Success

2

Outline

• Background and Business Climate for CMP

• Technical Approach

• STORM Development

• CMP Applications and Examples

• Conclusions


3

What is CMP?

CMP = Chemical Mechanical Polishing (Planarization)• Developed by IBM in late 1980’s. Licensed to and quickly

adopted by both Intel and Micron in the early 1990’s• Key manufacturing process required to improve device

performance and achieve yield advancements

Pictures courtesy of Medtronic, Inc.

No CMP – Traditional Device

4 Basic CMP Steps – Newer Device

(a) Side View (b) Top View

Carrier (head)

Polishing Pad

Platen

Wafer

Pad ConditionerSlurry Feed

Carrier (head)

Slurry Feed PMD

W Via

ILD

W Plug


4

CMOS Life Before CMP

• Topography at ILD levels (some severe)

• Sloped wall vias generally limited designers to only 2 or 3 levels of metal

• Even for fabs that adopted tungsten plugs and SOG, stacked plugs were generally not allowed


5

CMOS Life After CMP

• Topography under control

• CMP enabled multiple levels of metal

• Stacked plugs no longer an issue

• Shallow trench isolation widely adopted

• Drove several generations of shrinks and more complicated stacks

• However … this technology also started to run out of steam for the most advanced CMOS devices

AMD K6 microprocessor (circa 1996)


6

CMOS Life with Cu CMP

IBM PC603 microprocessor(circa 1998)

• Dual damascene process integration for patterning Cu lines and vias

• Primary process issues: Robust clear, defect density, dishing, erosion

• Fastest growing CMP application for past few years, but still smaller than oxide and tungsten overall


7

Interconnects at Intel

Interconnect Technology

500 nmILD planarization, W plugs w etch back

130 nm3-6 Cu Layers, PMD, W, STI

350 nmFour Al metal layers, W polish, PSG

180 nm STI, 6 Al Metal layers

250 nmSTI, Five Al metal layers, SiOF

65 nm4-11 Cu LayersPMD, W, STI, OSG

90 nm3-9 Cu Layers, PMD, W, STIOrganoSilicate Glass (OSG)

1000 nmTwo Al Metal layers, BPSG

CMP Evolution

Oxide PolishPre-Metal DielectricInterlevel Dielectric

STI PolishPoly PolishTungsten PolishCopper PolishBarrier PolishHigh k Gate

CMP Applications

Process, Applicatio

n, Equipment, &

Slurry Evolve, but n

ot as much on Pads

Source: Courtesy of Ken CadienFormer Intel fellow


8

Driving Forces Today

• Since 2005, consumer products have become primary industry driver.

• Short product life cycles.

• Consumers demand More for Less.

• Consumers demand More in Less Space.

• Contributing factors for Moore’s Law – device shrinks, multi-level stacks & larger wafers.

• Result = Fierce Competition

+ Control Unit Costs+ Develop Technology Fast+ Ramp Volume Quickly

Source: 2007 Industry Strategy Symposium – Hans Stork, CTO, Texas Instruments

Source: 2007 Industry Strategy Symposium – Steve Newberry, CEO, Lam Research Corporation


9

Competitive Advantage

Revenue Loss from Being Late to Market Acceleration with CMP Outsourcing:Scenario 1: First time CMP implementation

Customer Internal Technology Integration Project:Ramp

CMP Implementation with Entrepix:Ramp

Scenario 2: CMP capacity expansionCustomer Internal Capacity Expansion Project:

Qualify Ramp

CMP Capacity Expansion with Entrepix:Qualify Ramp

Scenario 3: CMP burst or flex capacity absorptionCustomer Internal Capacity Expansion Project:

Qualify Ramp

CMP Capacity Expansion by IDM already qualified at Entrepix:Ramp

Scenario 4: CMP technology improvement or cost reductionCustomer Internal Capacity Expansion Project:

Ramp

CMP Capacity Expansion with Entrepix:Qualify Ramp

Proj

ect P

hase

s Customer Generating Revenue

TIME

Develop, Optimize & Qualify

Customer Generating Revenue


Equipment Purchase & Delivery Customer Gen. Rev.


Equipment Purchase & Delivery Design, Integrate, Optimize & Quality

Customer Gen. Rev.


Equipment Purchase & Delivery

Optimize & Qualify

Strategic Factors in the IC Industry, FSA Forum, June 05Dr. Handel Jones, Chairman & CEO – IBS, Inc.


10

Business Realities

• Time IS Money– Labor cost + cycles of learning + opportunity cost

• Competition in most markets is fierce

• Quality & reliability can not be compromised

• Each process module must be efficient


11

Business Response

Extend Equipment LifeKeep Depreciated FabsR&D ConsortiaInstall Less OvercapacityDelay Capital Expenditures

Preserve CapitalMinimizeManufacturing Costs

Accelerate DevelopmentWhile Reducing Costs

BenchmarkingYield EnhancementOptimize Unit ProcessesFocus on Efficiencies

Reduce Cycles of LearningExtend Proven TechnologiesLower % of Engineering Wafer StartsLeverage Outside Expertise


12

Comprehensive CMP Solution

#1 Accelerate Time to Revenue#2 Reduce Cost and Risk


13

Applications for CMP Continue to Expand

Numerous complex puzzles1995 - Qty ≤ 2CMOS

Glass (oxide)Tungsten

2001 - Qty ≤ 5CMOS

Glass (oxide)TungstenCopper

Shallow TrenchPolysilicon

CMOS New Apps Substrate/EpiGlass (oxide) Doped Oxides GaAs

Tungsten Nitrides GaNCopper NiFe & NiFeCo InP

Shallow Trench Noble Metals CdTe & HgCdTePolysilicon Al & Stainless Ge and SiGe

Low k Polymers SiCCap Ultra Low k Ultra Thin Wafers Diamond & DLC

Metal Gates Direct Wafer Bond Si & ReclaimGate Insulators Through Si Vias SOI

High k Dielectrics 3-D Packaging QuartzIr & Pt Electrodes MEMS Titanium

Magnetics NanodevicesIntegrated Optics

2009 - Qty ≥ 36

Each application of CMP requires an optimized process that meets

both performance and cost targets


14

CMP Metrics

Five key metrics for a CMP process

Removal Rate and Uniformity

Defectivity

Planarization(step height, dishing/erosion, surface roughness, etc.)

Process Stability(consistent performance from wafer-to-wafer)

Cost per Wafer


15

CMP Development

• Zoom in on CMP process development

• Assumes fundamentals of pad/slurry research are already done by suppliers

• Test wafer availability and quality often impact timeline, validity of results, etc.

• Initial process DOE’s generally focus on removal rate and gross surface quality

• Optimization stages can be interchanged or executed in parallel

• Planarity can mean step height, dishing, erosion, roughness, etc. depending on the material and intended application

• Failure at any stage usually means backing up at least one stage to try again

Consumables Screening

Process DOE's

Optimize Uniformity

Optimize Planarity

Optimize Defectivity

Stability (marathon)

Release for Device Qualification

CMP Development Sequence

Generate Test Wafers

Repeatability (multiple runs)

Screening Tests

Optimization

Repeatability

Marathon


16

STORM

• Screening Tests

• Optimization

• Repeatability

• Marathon

STORMSTORM

A proven approachto successfullydeveloping newCMP processes


17

Intro to CMOS Example

• Project launched to develop a planarized integration for an existing facility running mostly 0.5um and larger devices which did not require CMP.

• Integration included 2 levels of oxide CMP (PMD and ILD) and 2 levels of tungsten CMP (contact and via1).

• Initial estimate was roughly 24 months to purchase, install, and qualify CMP equipment plus develop the integration and be ready for production ramp.

• By leveraging an outsource CMP provider, integration work was started almost immediately and executed in parallel with the equipment lead time.


18

Timeline Comparison

• Key aspects of predicted time savings:– Development could begin as soon as test wafers were ready.– Equipment purchase, lead time, and installation in parallel.– Faster cycles of learning, fewer wafers, lower cost compared to internal.

Initial Project Timeline for Tool Purchase and Internal Development

Install

Adjusted Project Timeline with CMP Outsource through Entrepix:

Install

3 mos 6 mos 9 mos 12 mos 15 mos 18 mos 21 mos 24 mos 27 mos 30 mos

Production Ramp

Development

Production RampQualification

Time

Proj

ect P

hase

s Equip. Purchase

Equip. Purchase

Timeframe Acceleration = 12+ months

Development

Volume Production Revenue Enabled

Qualification


19

Timeline Detail

Detailed Timeline for CMP Process Module Development

Patt.

Waf

ers

Blan

ket W

frs

CM

P L

ab D

ays

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Task or Milestone DetailsPhase 1: PMD Planarization Duration ~6-8 wks X

Generate test wafers BPSG XCMP process - Initial characterization 12 25 2 XPolar evaluation of results XPMD 2nd round optimization 13 25 1 X

Phase 2: Tungsten Contacts Duration ~8 wks XMask layout and photo optimization XGenerate test wafers 3rd party tungsten CVD XCMP process - Initial characterization Incl. SEM X-sections 12 25 3 XPolar evaluation of results XContact 2nd round optimization 13 25 2 X

Phase 3: ILD1 Planarization Duration ~6 wks XGenerate test wafers XCMP process - Initial characterization 12 15 2 XPolar evaluation of results XILD 2nd round optimization 13 10 1 X

Phase 4: Tungsten Vias Duration ~6 wks XMask layout and photo optimization XGenerate test wafers 3rd party tungsten CVD XCMP process - Initial characterization 12 25 2 XPolar evaluation of results XVia 2nd round optimization 13 25 1 X

Prototype Run (Begin Qual Lots) Duration 4-6 wks XMask layout and photo optimization XVerification of entire process flow 25 25 4 XEvaluation of prototype devices In-line and EOL (ongoing)

Polish processes developed: 4 (PMD, W Contact, ILD, W Via1)Total patterned wafers: < 125Total blanket test wafers: < 200Total CMP lab shifts: < 12


20

Issues Resolved

As might be expected, a few issues were encountered during the project. Examples are given below and further detail is provided in a few cases.

Issue How Resolved

Composition and thickness of ILD dielectric layer

Technical inputs from Entrepix with confirmation on 1st engineering lot

Alignment marks (inconsistent contrast on wafers with CMP)

Technical dialogue between Entrepix and customer engineering team

Pattern density effects Verbal description of effects confirmed with data from test structures – adjustments made in design rules

Ti/TiN liner and CVD W deposition thicknesses

Starting point suggestions followed by optimization on 1st and 2nd engineering lots

Poor contact fill (seen on first contact lot)

Suggestions from Entrepix and Novellus helped solve issue in one cycle of learning (Traced to insufficient strip after contact etch)

High NMOS leakage and poor p-field inversion

Changed PMD dielectric composition from TEOS to PSG or BPSG


21

Issue #1 – High Rc

4485A001 80 W-PLUG 3.JPG

4485A001-09 NOTCH A1.JPG

Hollow contact Improved contact

Hollow contacts with high resistance on first lot.

Initial brainstorming between customer and outsource provider led to short list of likely causes.

Resolved with one round of optimization.

Resolution involved optimizing post etch strip and was confirmed

on next product lot.


22

Issue #2 - Leakage

0.01

0.10.03

10.3

103

10030

1000300

100003000

Res

ult

BPSG PSG TEOS

PMD glass composition

BPSGPSG

TEOS.01 .05.10 .25 .50 .75 .90.95 .99

-3 -2 -1 0 1 2 3

Normal Quantile

0

10

20

30

40

50

60

Res

ult

BPSG PSG TEOS

PMD glass composition

BPSGPSG

TEOS

.01 .05.10 .25 .50 .75 .90.95 .99

-3 -2 -1 0 1 2 3

Normal Quantile

NMOS leakage by PMD oxide

P-field inversion by PMD oxide

The first integration lot showed unexpectedly high NMOS leakage and p-field inversion issues.

Technical brainstorming identified trapped charge in TEOS layer as a possible cause of the observed issue.

Split lot data confirms that changing to either BPSG or PSG for pre-metal dielectric resolves both issues.


23

CMOS Summary

• By leveraging the capabilities of an outsource CMP provider, the project timeline for developing a 0.35 um integration in a fab was accelerated by roughly one year.

• Acceleration was driven by two primary factors.

– First, the team did not have to wait on internal CMP equipment to be purchased and installed, thus avoiding 6-9 months of delay.

– Second, several key cycles of learning were assisted by insightsand guidance from the external technical staff.

• Substantial benefits and time savings realized through effective utilization of CMP outsourcing.


24

MEMS over CMOS

Key Process Metrics & Constraints

Metric Incoming Value

Post-CMP Target Actual

Oxide film thickness 6.5 um

2.8 um

n/a

Step Height

3.02 um3.0 um

< 0.4 um

0.5

0.2 um

Removal Rate (um/min) 0.488

Critical Concerns:Thick oxide layer over CMOS

Final topography must be < 0.4um

Smooth – No sharp corners anywhere

Batch to batch consistency0

1000

2000

3000

4000

5000

6000

1 2 3 4 5 6 7 8 9 10 11 12

Run #

Rem

oval

Rat

e (A

ng/m

in)

Photos downloaded from web sites, including Sandia National Lab


25

Direct Wafer Bonding

Example #2: Inlaid Cu in TEOSIncoming topography >2.5 kA

Goal of <200 A total topography

POST-CMP TOPOGRAPHY ACHIEVED

70-90 Angstroms

Example #1: TEOS on XOxide surfaces tend to bond well

when polished to sufficiently low Ra

Incoming roughness driven by surface prep of underlying material

Sufficient oxide thickness must be deposited to remove at least 2x initial peak-to-valley roughness

Material Stack Incoming Ra (A)

Post-CMPRa (A)

TEOS on Silicon 7 3

TEOS on AlN 187 11

72

87

332

TEOS on SiC 7

TEOS on Polysilicon 7

TEOS on Metal 8

Flat across

Feature


26

Conclusions

• Efficient development of new products is required for any device manufacturer to remain competitive

• CMP process development involves a sequence of stages (STORM) to efficiently hit technical goals– Screening Tests– Optimization– Repeatability– Marathon

• Proper utilization of CMP outsourcing enables– Accelerate timelines– Preserve capital– Reduce cost and risk


27

Contact info

Anyone desiring copies of this presentation or any other information please contact:

Rob RhoadesChief Technology Officer

Tel: 602 426-8668Fax: 602 426-8678

[email protected]


28

Appendix

• Slides providing additional details on STORM


29

Screening Tests

Early stage development efforts often involve:• Immature deposition or growth processes• Poorly characterized materials or integrations• Technologists who may not be familiar with CMP and

how it interacts with other process modules• Wide variation in pattern density/feature sizes• Wafer sizes smaller than 200 mm• Limited availability of test wafer

These factors can create huge challenges for CMP


30

Rate Screening

Removal Rate

010002000300040005000600070008000

Slurry #1

Slurry #2

Slurry #3

Slurry #4

Slurry #5

Slurry #6

Slurry #7

Slurry #8

Slurry #9

Slurry #10

Rem

oval

Rat

e (A

ng/m

in)

• Metal CMP application

• Pad selection frozen

• Goal of 4 kA/min• Multiple slurry

candidates• Slurry #8 was

chosen for further optimization


31

Process DOE’s

ResourcesConsumables (Pad and slurry)

Blanket film test wafers (all mtrls)

Defect monitor wafers (if available)

Experimental Plan InputsGoal is to get preliminary process responses to major variables

Preston’s Equation (RR=k*P*V) is only an approximation

Keep % changes below 25% to keep DOE’s as “linear” as possible

Responses to slurry flow and back pressure are not usually linear

Successive 2x2 or 3x3 DOE’s are generally preferable to massive designs

Include defectivity as an output metric if wafers are available

Desired OutputsRate and uniformity responses to

changes in major process variables

Identify a process to start further optimization


32

Optimization

ResourcesConsumables (Pad and slurry)

Blanket film wafers (selected mtrls)

Defect monitor wafers

Patterned wafers for planarization

Experimental Plan InputsBe careful using DOE’s … single-variable curves often more helpful at this stage

Focus on variables with strongest link to parameter being optimized

Uniformity: Carrier-to-table speed ratio, back pressure or carrier zones

Planarization: Downforce, table speed (keep in mind rate tradeoffs)

Defectivity: Downforce, slurry flow, final recipe steps (remember tradeoffs)

Number of wafers can quickly get large

Desired OutputsSingle process recipe that meets all

required process metrics

Data supporting chosen recipe and responses in nearby process space


33

Repeatability

ResourcesConsumables (multiple batches)

Blanket film wafers


Patterned wafers (optional)

Experimental Plan InputsKeep process recipe consistent throughout trials

Measure all relevant metrics, not just removal rate

Planarization monitor can be low sampling frequency

Defect monitor can likewise be low frequency if confident in process

Desired OutputsConsistent process performance

data using same process settings across multiple consumable sets


34

Marathon Run

ResourcesConsumables

Blanket film wafers (selected mtrls)


Patterned wafers

Experimental Plan InputsGenerally want to prove stability for duration of pad life, or at least 250 wafers

Different than repeatability … focus is on process stability of a single pad set

Can be a continuation of the last pad set of the repeatability trial

Liberal use of filler wafers can save cost

Sample at some low frequency for defects and planarization

Desired OutputsData showing process consistency

through pad life (or at least a reasonably large number of wafers)


35

Blanket wafer marathon

1000

2000

3000

4000

5000

Start 25 50 75 100 125 150 175 200 225 250Wafer Number

Rem

oval

Rat

e (A

ng/m

in)

0.0

5.0

10.0

15.0

20.0

Uni

form

ity (%

1-s

igm

a)

Removal Rate% NU

Oxide CMP Qualification RunPolisher: AMAT Mirra MesaPad: IC1010Slurry: Klebosol 1501-50Conditioning: In-situMetrology: 49-point diameter scan, 3mm EE

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