New approach for the ordering of gate permutation in one-dimensional logic arrays

J. Lee J.-H. ChOu S.-L. FU

Indexing tenns: Gate permutation, Logic arrays

Abstract: The one-dimensional gate permutation problem is transferred into a new one of achieving an optimum gate permutation under the con- straint of a predetermined adjustable maximum number of tracks. A fast and efficient constructive algorithm is proposed to solve it. The algorithm has the advantage of uniformly distributing the local congestion so that optimum permutation with the required track number can be obtained. The experimental results show that it is a fast algorithm and gives better solutions than other constructive algorithms. Moreover, it can be used as an improvement algorithm by using a modified ratio-cut technique. The improvement algorithm iteratively improves the previous solutions, and thus results comparable to the simulated anneal- ing approach can be obtained in less CPU time.

1 Introduction

In the late 1960s, Weinberger [l] introduced a novel layout method for MOS complex logic by combining placement and routing into a single process. In his method, a complex logic circuit is constructed from NAND (NOR) gates and is laid out as a one-dimensional array. The one-dimensional gate layout is usually rep- resented by an abstract model of the type shown in Fig. la. In the Figure, the horizontal lines, vertical lines, and

41 42 93 94 95 96 47 98 91 44 92 43 95 96 47 98 p--J1#q3 fi" in6m3

nL "L

"6 "7

n7 a b

Fig. 1 Four-track layout

Examples ofone-dimensional arrays: (a) Three-track layout (b)

Netkt of(4: '3%) = {g,, g.1, G(n2n,) = IsI. g6h G(nJ = Is,, gs). G(nS = IgL. &. g4.sd .G(nd= Iss.g7).G(nJ= Ig1.sz.s3).G(n,)= IgI.g6.ssJ

the black points represent nets, gates, and terminals of gates, respectively. Obviously, different gate permutations will result in different layouts with different numbers of

0 IEE, 1995 Paper 16356 (ElO), first received 22nd Lkember 1993 and in revised form 22nd August 1994 J. Lee and S.-L. Fu are with the Department of Electrical Engineering, and J.-H. Chou is with the Department of Engineering Science, National Cheng Kung University, Tainan, Taiwan, Republic of China

90

tracks. For example, Fig. l b shows a layout with a track number larger than that in Fig. la. As the height of the array varies with the number of tracks, one must mini- mise the tracks required so as to minimise the layout area.

The problem is usually formulated in two different ways. The first is a net-oriented approach, which deter- mines the optimum positions of nets lying in a single track. In this case, the problem is converted into a graph theoretical problem to find an interval graph with the minimum clique number. As it is NP-hard [2, 31, various heuristic algorithms have been proposed in the literature

The second is a gate-oriented approach. In this case, the problem is formulated so as to obtain an optimum gate ordering with a minimised layout area. It is also NP-hard [SI, and thus heuristic algorithms are again needed [7-91. Fujii et al. [A transformed the original problem into a restricted one in which each connection was restricted to be between two columns. Both unidirec- tional and bidirectional approaches [7,8] have been pro- posed to solve it. These methods place the gates, one at a time, based on the objective of minimum tracks for each placed gate. Obviously, only local optimum solutions can be obtained as these algorithms are based on a greedy strategy.

Here, we propose a new approach in which the problem is regarded as one of achieving an optimum gate permutation under the constraint of a predetermined maximum track number. This leads to an efficient heuris- tic algorithm.

~2,4,51.

2 Problem formulation

In this study, a hypergraph is used to model the gate-net incident relation. In the hypergraph model, vertices rep- resent gates, and hyperedges represent nets. For a hyper- graph H(G, N), the vertex set G contains rn vertices indexed by {gl, g2, ..., g,,,}, and the hyperedge set N by {nl, n2, ..., n,,}, where g1 and g,,, are the leftmost and rightmost boundary vertices, respectively, representing the 1/0 terminals of the layout region. The set of vertices incident with hyperedge ni is represented by G(ni), and I G(n,) I denotes the size of ni . The set of hyperedges incid- ent to vertex g, is denoted by N(g,), and 1 N(gj) I is the degree of g, . R denotes the maximum numbers of vertices on any hyperedge, and D denotes the maximum number of hyperedges on any vertex, i.e.

R = Max I G(nJ1 and D = Max IN(gj)l l < i < n l < j S m

IEE Proc.-Circuits Devices Syst., Vol. 142, No. 1, February 1995

Furthermore, G(N(gj)) represents the set of vertices neigh- bouring gi. As an example, Fig. 2 shows a hypergraph corresponding to the netlist given in Fig. la.

Fig. 2 Hypergraph representation of the netlist in Fig. l a

I A vertex permutation P is constructed by a linear set PC1 : ml = <si, gk, ..., si, ..., g,> where P[ll = gl, P[2] = g r , . . . , etc. If P[u] = gj, define P-'(gj) = U which represents the position of gj in P.

The number of tracks on gj in a placement with the vertex permutation P, represented by T,gj), is equal to I Nkj) I + I Q&j) 1, where

The number of tracks required in the placement, T'G), is

The vertex permutation problem can be stated as

Given a hypergraph, H(G, N), with two boundary ver- tices, find the vertex permutation P such that TAG) is minimum. It is a minimisation problem. If one uses the sequential

optimisation technique to solve it, it always needs .to minimise the tracks required for each optimisation process and can easily fall into the traps of local optima. To overcome this drawback, we reconsider it as a con- straint problem described as follows:

Given a hypergraph, H(G, N), with two boundary ver- tices and the maximum number of tracks, Tm,, achieve a vertex permutation, P, such that T,(G) Q TM,. If no solution exists, the constraint is gradually relaxed until a solution is obtained.

In this study, the initial value of T,, is set to D, the lower bound of the tracks required.

With our approach, there is no need to minimise the track number for each optimisation process. In contrast, the local congestion of tracks is redistributed to obtain a solution satisfying the track constraint and avoiding, or at least not falling fast, into a local minimum.

In this paper, we propose two heuristic algorithms for the constraint problem. The first is a constructive algo- rithm (algorithm C) which gives an initial vertex permu- tation. The second is an iterative improvement algorithm (algorithm I) which is used to improve the previous solu- tions.

equal to Maxlci,,

follows:

3 Description of algorithm C

Algorithm C is a repeated-assignment algorithm. At first, the elements in P[2 : m - 11 are empty. Let gt and g, be the leftmost and the rightmost boundary vertices of the empty set, respectively. Initially, gL , is g1 and g p . is gm . The indices iL and i, are used to indicate the positions of gL and g,, respectively. The unassigned vertices are called free vertices. In each assignment process, a free

IEE Proc.-Circuits Devices Syst.. Vol. 142, No. I . Febrwry 199s

vertex is selected and assigned into P according to the selection rules to be described later, If the selected vertex, gs , is assigned to P[iL + 11, then iL is replaced by iL + 1 and gL is updated by gs. On the other hand, if gs is assigned to P[iR - 11, then iR is replaced by iR - 1 and gR is updated by gs. This process is repeated until all vertices are assigned.

Before explaining the details of algorithm C, let US consider an assignment process. Let d be the set of free vertices. A selected vertex, gs E d, is considered to be placed next to g B in P, where g,, is either gL or g,. The set of hyperedges incident to gB and/or gs is represented by N ( g B , gs). That is, N(gs, Ss) = N(gB) U N(gs). N ( g B 9

gs) can be divided into four disjoint subsets: N&B, g$ N,i(g~, gs), N & B , Ss)t and N,i(gs, Bs) as shown in Fig. 3a. We call them the sets of internal hyperedges, of

b X . 1

Ng1 b

Fig. 3 a Four types of bypmdges b Contracted bypergraph after combining gL and us

Four types of hyperedges and hypergraph contraction

partial internal hyperedges, of external hyperedges, and of global hyperedges, respectively. They are defined as follows:

If gs is placed at the neighbours of g B , the number of tracks on gs , written as T h s , gs), is

TdgB 9 9s) = I N ( 8 B 9 9s) I The assignment process can be modelled by combining gB and gs in the hypergraph such as is shown in Fig. 3b, where the previous hypergraph is contracted to a new one with fewer terminals after the combination. The internal hyperedges are deleted from the hypergraph; the partial internal hyperedges are contracted to form one- size-less hyperedges; the external hyperedges have no changes in their sues; and the global hyperedges may change their sizes. For each assignment process the aim is to reduce as many terminals as possible under the maximum track constraint, as the difficulty in finishing a vertex permutation under the track constraint directly

91

- ~

depends on the number of terminals. A function which estimates the contribution of the terminal deletion by combining g, and g, is defined by

where the contribution by the global hyperedges is excluded as each global hyperedge must occupy one track, irrespective of the permutation of other free ver- tices.

TD(g, 2 e3 = 2 I N&B 3 gd I + I Ndgs 9 gs) I

The rules for selecting gB and gs are as follows: (i) Select the pair of maximum TD(g,, gs), if tie (ii) Select the one with maximum I Ndg,, gs) 1, if tie

(iii) Select the one with maximum T&, , gs). again

Rule (ii) is based on the conjecture that if the vertices can be arranged such that those hyperedges with fewer ter- minals are shorter, the tracks required will be greatly reduced [SI. Rule (iii) is very different from previously known algorithms for which minimisation of tracks is required for each process [7-91. There are at least two reasons for this. First, combining the pair of g, and gs with a larger value of T A B , g,) leads to a new boundary vertex which is adjacent to more free vertices; thus, in the subsequent assignment, we can select the next vertex more globally. Secondly, a boundary vertex with more hyperedges has the possibility of contributing to a larger reduction of terminals in the subsequent assignment process.

Algorithm C is initiated by

call ALGORITHM-C(G, N, 1, m) The outline of algorithm C is given in the following.

92

III

If g, is gR, then iR + iR - 1; P[iJ + gs; Gc - {gR}.

STEP 7: If I GI > 2, go to STEP 2. Otherwise, output P.

Example 1: Figs. 4a to f show a step-by-step assignment process of algorithm C for the example shown in Fig. la.

. .

. . .

9"

, . . . #y "7

b

STEP 4: (1) Cl + C1 - {g4, 84; Cz + Cz - (661, because

g4)=Tp(BL7 8 5 ) = T d B R , 66)=4 '

(2) TD(g,, 92) = TD@R, 9 7 ) = 2; TD(gL 9 93) = TD(gR, 84) = 1. N i k 7 ~ , Qz) = 0 and Nin(gR

Tmx.

8 7 ) = 1. STEP 5: Both pairs of {g,, g2} and {g,, g7} have the

largest size of terminal deletion, but the latter has more internal hyperedges, and is thus selec- ted.

STEP 6: (l) - i.31 as "3. E Nin(gR 9 87). (2) There is no partial internal hyperedge in N(g,,

87).

change of n, . (3) q n 7 ) qn7) - bR} + (97). (4) n, E NeJgR, g7) and g7 E G(n5); thus there is no

(5) There is no global hyperedge in N(gR , 9,). (6) iR + 7; P[id + 87, G + G - { B E } .

STEP7: AsIGl>2,gotoSTEP2.

The assignment process proceeds step-by-step. Finally, a layout of three tracks is obtained as shown in Fig. la. In contrast, let us consider the case without the maximum track constraint in the following. In the first assignment process, the pair of g, (i.e. gl ) and g4 which has the largest value of terminal deletion is selected. g4 is then assigned to the place next to g,. The process of vertex assignment proceeds. Finally, a layout of four tracks, as shown in Fig. lb, is made. The example shows how the maximum track constraint can help the assignment process to avoid the traps of local optima.

4

Basically, the procedure of algorithm C is a sequence of hypergraph reductions. Therefore, the initial hypergraph needs the maximum memory space. The space complex- ity is then O( I G I + 1 NI).

To estimate time complexity, let us consider the worst case that assigns the vertex only in one direction. Without loss of generality, we assume each vertex is assigned to the left side one-by-one. The critical step for algorithm C is STEP 4. In this step, for each vertex g, in G(N(gJ), N(g,, gj) is partitioned into four subsets. The operator can be executed by comparing hyperedges in N ( g 3 to those in N(gj); thus, it takes O(IN(gL)I + IN(g,)l) time. After that, both TAg,, gj) and TD(g,, g,) can be determined in U(1) time. Thus the time com- plexity for the assignment process is

Complexity analysis of algorithm C

O( I GO%")) I x I N g d I x I Nhj) I ) As I N(8J I Q D, I N(g3 I Q Tp(G), and I c(N(gd) I 4 R x TAG), time complexity can be represented by

O(T,G)z). Thus, executing algorithm C, one pass takes O(m x TAG)')). For the entire process, algorithm C must be executed TAG) - D + 1 passes; therefore, the entire time complexity of the algorithm is q t x m x where t = TAG) - D + 1. For a sparse hypergraph, the complexity can be further reduced to O(m x TAG)z) because TAG) is close to D. For a dense hypergraph, the complexity is O(m x because TAG) is much larger than D.

6 Algorithm I

Although algorithm C is a constructive algorithm, it can be used as an iterative algorithm by using a modified

I E E Proc-Cirnrits Denices Syst., Vol. 142, No. 1, February 1995

ratio-cut technique. Namely, for each improvement pass, the current hypergraph is partitioned into two sub- hypergraphs of smaller sizes by the modified ratio-cut technique. Algorithm C then reconstructs a new vertex permutation for each subhypergraph. If the new vertex permutation is an improvement on the current one, the current one is replaced by the new one. This procedure continues until a stopping criterion is met. In the follow- ing, we first introduce the modified ratio-cut technique and then describe the improvement algorithm, called

5.1 Modified ratio-cut technique The ratio-cut concept is good for identifying natural clus- ters in a circuit [11-131. Here, a modified ratio-cut tech- nique to divide the current hypergraph into two parts is presented.

Given H(G, N) with vertex permutation P[1 : m], a cut vertex located at k, denoted by g&, divides H(G, N) into two subsets of H'(G', N') and H2(G2, N2) with vertex permutation P[1 : k] and P[k : m], respectively. The weight of gcut is equal to Tde,,). The ratio of g denoted by R(g,), is defined by Tp(g,)/( I G' 1 x I Gip,: The ratio-cut vertex is then a cut vertex that generates the minimum ratio with the minimum track bound. The value of the minimum bound is equal to [(D + T.G))/2], where [I denotes the Gaussian function. The reasons for choosing such a bound are based on the following con- siderations. As gmI is the rightmost and the leftmost boundary vertex in P[1 : k] and P[k : m], respectively, neither T',g,) too large nor too small is a good choice. If T h m , ) is too large, it limits further improvements. On the contrary, if T'gcut) is too small, it is difficult to obtain a layout of uniform track distribution for reasons described in Section 3. Thus, we choose the average value of D and Tp(G) as the minimum bound.

It should be mentioned that our cut is a set of tracks on a vertex. This is different from the usual cut, as given in References 11 to 13, which is a set of hyperedges. It is because the usual cut cannot exactly reflex the tracks

algorithm I.

required. H'(G', N') and H2(G2, N z ) are constructed as follows.

(1) G' = {g i lP- ' (g i ) f k} and G2 = {gjJP-'(g,) 2 k}. (2) N is partitioned into three disjoint subsets: N,, N,,

and N,, where N L = ini I '/si E Wi), P-'(8,) f k}; NR = {ni I Vgj E G(ni), P- '(9,) 2 k}; N ~ = { n , 1 3 9 , , g k E q n 3 3 P - ' ( g j ) < k < P - ' ( g , ) } .

For each ni E NM, it is divided into two parts of ni, , and ni. ,, where

%,d= {B.JgU~ G(ni)AP-'(gJ < k) U {gnu); G(n, RI = {So I Bv E G(ni)A P-'bu) > k} U {gat}.

(3) N' = N , v NM,,; N' = N , U NM,,, where N,, , and N,, R are the sets of n,, , and nl, , , respectively.

Example 2: Consider the logic circuit with the vertex per- mutation P as shown in Fig. 16. Here, g, divides the layout into two parts as shown in Fig. 5, where G' = {gl,

91 94 92 93 95 f l n l l gmn3

n7* L n7. R

Fig. 5 Ratio-mt gate g, dividing Fig. Ib into two pmts

93

I11

Table 1 : Commrison of alaorithm C w i t h some other a l a o r i t h m

Data Gates Nets D

1 [2] 8 8 3 2 121 9 9 3 3 i7j 9 8 4 4 [8] 9 7 4 5[9] 10 1 1 4 6[13] 10 1 1 4 7 [14] 9 21 10

Algorithm C. Other algorithms Optimum solutions

Tracks Wire CPU Tracks Wire Tracks Wire required length time (s) required length required length

3 12 0.01 3 12 3 12 4 17 0.012 4 18 4 17 4 24 0.018 4 27 4 24 5 25 0.018 5 26 5 25 4 25 0.017 4 25 4 25 4 25 0.018 4 26 4 25

1 1 50 0.038 1 1 51 1 1 50

52 Algorithm I A vertex permutation P is an improved permutation on P, if and only if, either

(1) TAG) > WG), or

Using these criteria, algorithm I is initiated by

call ALGORITHM-I(G, N, 1, m)

(2) TAG) = ' M G ) and Eg,eo Ugj) > E g j . G Gbj)

The procedure of algorithm I is as follows:

ALGORITHM-I(G, N', it, i d // Enter H ( G , N') with its permutation P[iL : in]. Update

the old permutation. // STEP 1 : R(gcyl) c a large initial value. STEP 2: For each gj E G

if TAgj) > [ (D + TAG))/21 and Rbj) < R(8,t)T then g, gj

STEP 3: Divide H ( G , N' into H'(G', N') with P[iL : i,] end loop

and H2(GZ, N 1. ) with P[i, : id, where in =

p- '(gcur).

a,).

then P[iL : i,] + P'[iL : i,].

id.

STEP 4 : (1) P[iL : i,] + call ALGORITHM-C(G', N', iL,

(2) If P[iL : i,] is an improvement to P[iL : i,],

(3) P[iK : iR] + call ALGORITHM-C(G2, NZ, i,,

(4) If P[i, : in] is an improvement to P[iK : in], then P[i, : in] c P[iK : in].

STEP 5 : (1) If I G' I > threshold value, then call

(2) If IG21 > threshold value, then call ALGORITHM-I(G', N', iL, iK).

ALGORITHM-I(G2, N2, i,, id.

In the best case, if each time that the ratio-cut technique partitions the one-dimensional permutation into two evenly sized parts, the time complexity is O(t x m x log m x In the worst case, if each time that the ratio- cut technique partitions the one-dimensional permu- tation into two very unevenly sized parts, the time complexity is O(t x m2 x

6 Results and discussion

The algorithms described were implemented in C lan- guage, and run on a SUN SPARC I work-station. Several examples from the literature [2, 7-9, 13-15] were used to test the algorithms and the results were compared with those of others in terms of the tracks required, the total wire lengths, and the CPU running time whenever possible.

Table 1 includes seven examples proposed by other authors [2,7-9, 13, 141. We compare the results of algo- rithm C with others and with the optimum solutions obtained by the exhaustive search using the branch and bound technique. For all of the examples examined, algo- rithm C gives the optimum solutions for both the numbers of tracks required and the total Wire lengths.

In Table 2, we compare the results of algorithm C with those obtained by Hong et al. and the simulated anneal- ing approach [SI. In Table 3, we compare the results of

Table 2: Comparisons of algorithm C w i t h t h e algorithms in Reference 8

Data Gates Nets D Algorithm C Hong etal. Simulated annealing

Tracks Wire CPU Tracks Wire Tracks Wire required length time (s) required length required length

4 9 7 4 5 25 0.015 5 26 8 15 18 6 7 71 0.038 7 71 7 71 9 29 37 7 13 265 0.153 13 254 13 245 10 48 48 7 12 371 0.2 13 383 1 1 357

Table 3: Comparisons of algorithm C with t h e algorithms in Rafarenws 7.9, and 15

Data Gates Nets D Algorithm C Yamsta er e/ 191 Algorithm G [7] Chsng [151 Tracks Win CPU' Tracks Wire CPU' Tracks Wire CPU' Tracks Wire CPU' required length time (6) required length time (s) required length time (6) required length time (6)

3[7] 9 8 4 4 24 0018 4 27 NA 11 [15] 15 79 16 20 116 0125 21 112 NA 12[15] 16 17 4 8 70 0033 8 71 0 2 8 79 1 5 8 73 2 7 13[14] 31 33 4 6 92 0055 6 94 0 7 6 106 3 0 6 91 7 3 14[9] 85 96 16 22 1379 1028 23 1470 4 7 32 1968 9 3

' Run on a SUN SPARC I work-station ' Run on a SONY NEWS 830 work-station ' Run on a VAX 11/180 machine

94 IEE Proc -Circuits Devices Sysf., Vol. 142. No. I , February 1995

algorithm C with those of three previously published algorithms [7, 9, 151. The results show that algorithm C gives better results than other constructive algorithms

0.5

0.4 C 9

m '0 0.3

c 0,

.- E

0, ol

& 0.2

P 6 0.1

c

0 0 5 10, 15 20 25 30

Variation of the average terminal congestion of the unassigned assignment passes

Fig. 8 gatesJor each assignment pass

-0- T,=13 -x- T U =16

-0- T-=11

but is not as good as the simulated annealing approach in most cases.

From the above comparisons, we can conclude that for small-sized problems, algorithm C obtains optimum solutions. For medium-sized problems, although algo- rithm C may not give the optimum solutions, it is better than other constructive algorithms, especially as the number of gates increases. Furthermore, algorithm C is very fast. This is important because the gate assignment problem is NP-hard and one needs to search through the solution space effectively.

Basically, algorithm C assigns each vertex (gate) into a linear set based on a greedy strategy. However, it is very different from the greedy method, because of the maximum track constraint which helps us to avoid the traps of local optima which commonly occur in the greedy method. Before explaining this effect, we introduce the concept of average terminal congestion of the set of free vertices during the execution of algorithm C as

Cong(G-9 = S(G') / (Lz x I @ I ) where S(Gf) is the size of terminals in GI. A larger value of Gong(@) implies a more crowded and difficult circuit to layout. As a typical example, in Fig. 6, the variation of CodGI) against the vertex assignment pass of data 9 is depicted for three different maximum track constraints, namely T,, = 11, 13 and 16. In the first twelve assign- ment passes, all the results indicate the same trend. But after that, the trends are different. For TmX = 11,

Cow(@) increases as the assignment pass proceeds further, as T- is too small for algorithm C to effectively delete terminals. Thus, in the twentieth assignment pass,

13 q 32 31 L 23 - 24 - 25 - 21 - 22 -

78 81 77 I9 - 34 - 35 33

- - - -

28 26 50 49 52 36

9 - 37- 51

U ) $1 43

42 41 e- 53 - 55 5L- 56- 57 - 60 - 59 58 61 - 70 - 64 - 62 - 63- n- 71 - 69 - 65- 68 - 66 - 75 74 - 76 - 67 - 7- 10 85

- -

- -

n- -

-

t

Fig. 7 Lnyart of Data 14

4

if:

r r l

Table 4: Comparison of our algorithms w i t h simulated annealing 181 Data Algorithm C Algorithm I Simulated annealing

Tracks Wire CPU Tracks Wire CPU Tracks Wire required length time (s) required length time (s) required length

9 13 265 0.153 13 257 0.853 13 245 10 12 371 0.2 11 360 1.47 11 357

92 0.055 6 90 0.173 13 6 14 22 1379 1.028 20 1314 10.857

IEE proC.-Circuits Devices Syst., Vol. 142, No. I , F e b w y 1595 95

the maximum track constraint cannot be preserved and the vertex assignment fails. On the other hand, for T, = 16, Cong(C‘) decreases as the assignment pass proceeds further. It shows that T,, is too large, and the assignment procedure falls into local optima and finally obtains a layout of 16 tracks. For T, = 13, Cong(G/) only varies in a small range throughout the assignment process and the result is the best. This example indicates that algorithm C can uniformly distribute the local congestion of terminals (i.e. the tracks) to obtain good results.

In Table 4, we compare the results of algorithm C, algorithm I, and the simulated annealing approach for several large-sized problems. Here, the threshold value was set to be 15, because algorithm C can obtain optimum solutions for small-sized problems. The experi- mental results show that algorithm I gives obviously better results than algorithm C, especially when the size increases. In comparison algorithm I to the simulated annealing approach, algorithm I gives the same number of tracks. The layout of Data 14 obtained by algorithm I is depicted in Fig. 7 as a typical example.

7 Conclusions

We have proposed a new approach to the problem of the ordering of gate permutation in an array such that the corresponding layout area is the smallest. In the approach, we transfer the problem into one of achieving an optimum gate permutation under the constraint of a predetermined, adjustable maximum number of tracks. The new problem can be solved more logically by the sequential optimisation process. We have also developed fast and efficient heuristic algorithms to solve it. The objectives of our algorithms are considered in the global level, thus overcoming the drawback of the greedy method. Moreover, even though algorithm C is a con- structive algorithm, it can be used to iteratively improve the previous solutions by using a modified ratio-cut tech- nique (algorithm I).

The results show that our algorithms can uniformly distribute the local congestion to obtain optimum permu- tation. Compared with other constructive algorithms published in the literature, algorithm C is the best in both performance and the execution time. Algorithm I can improve the results obtained from algorithm C, especially for large-sized problems, and gives comparable results to the simulated annealing approach, but with a shorter execution time. In addition, as a hypergraph is used to model the gate-net relation, this method can easily be

applied to other layout design problems such as the gate matrix layout problem [16, 171 or the linear placement problem [l5, 181.

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17 WING, 0.. HUANG, S., and WANG, R.: ‘Gate matrix layout’, IEEE Trans. Cornput.-Aided Des. 1985, CAD4 pp. 220-231

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