Published in IET Circuits, Devices & Systems Received on 5th June 2008 Revised on 12th November 2008 doi: 10.1049/iet-cds:20080156 ISSN 1751-858X New building block: multiplication-mode current conveyor Y.-S. Hwang W.-H. Liu S.-H. Tu J.-J. Chen Department of Electronic Engineering, National Taipei University of Technology, Taipei 106, Taiwan, Republic of China E-mail: [email protected]Abstract: A new building block called the multiplication-mode current conveyor (MMCC) is proposed here. The structure consists of a differential voltage current conveyor (DVCC) and a folded Gilbert cell without any other auxiliary circuits. Based on the MMCC, a four-quadrant analogue multiplier is designed in TSMC 0.35 mm CMOS 2P4M processes with power supply +1.65 V. HSPICE post-layout simulation results show that the maximum DC operating range is +200 mV, the loading range is from 1 to 10 kV, the bandwidth is about 90 MHz, the total harmonic distortion (THD) is 0.85%, the power consumption is 1.08 mW and the chip area without pads is 0.48 0.36 mm 2 . The new square summer and analogue divider applications employing MMCCs are also presented. 1 Introduction The current-mode circuits are proven to offer several advantages over their voltage-mode counterparts [1, 2]. The second- generation current conveyor (CCII) has been receiving significant attention in current-mode filters [3, 4]. Moreover, many current-mode analogue signal processing applications are presented by using CCIIs [5–7]. Some different types of current conveyors are also proposed [8–10]. But they have the same features which the addition and/or subtraction of the input voltages use. On the other hand, the multiplier is a very useful building block in the modulator, adaptive filter, artificial neural network etc [11, 12]. It is often categorised as the single-quadrant (inputs are both unipolar), two-quadrant (one of the inputs is bipolar) and four-quadrant (inputs are both bipolar) circuits. The basic idea of the multiplier is that there are two input signals applied to a nonlinear device characterised by a high-order polynomial function. The polynomial function involves many nonlinear terms and these terms must be cancelled to reduce the total harmonic distortion (THD). In the recent years, a lot of different architectures of analogue multipliers based on CCIIs are proposed [13–15]. In the article, we propose a new architecture called the multiplication-mode current conveyor (MMCC) that combines the advantages of the differential voltage current conveyor (DVCC) and the folded Gilbert cell [16] four-quadrant multiplier to provide both voltage and current signals from the outputs without any other auxiliary circuits. The circuit description of the proposed MMCC is introduced in Section 2, and the simulation results of the MMCC are shown in Section 3. Section 4 proposes the square summer and the analogue divider applications. Finally, the conclusion is made in Section 5. 2 Circuit descriptions The circuit symbol of the DVCC is shown in Fig. 1. Basically, the terminal relationship of an ideal DVCC can be given by the following matrix I Y1 I Y2 V X I Z 2 6 6 4 3 7 7 5 ¼ 0 0 0 0 0 0 0 0 1 1 0 0 0 0 + 1 0 2 6 6 4 3 7 7 5 V Y1 V Y2 I X I Z 2 6 6 4 3 7 7 5 (1) where the plus sign represents the positive DVCC and the minus one represents the negative DVCC, respectively. The CMOS circuit of the positive DVCC [8] is shown in Fig. 2. The circuit structure consists of additional differential pair and the CCII. The input stage (M 1 and M 2 ,M 7 and M 8 ) adopts two differential pair and provides two inputs, Y 1 and Y 2 . The high-gain stage is composed of an active current mirror (M 3 –M 6 ) which converts the differential IET Circuits Devices Syst., 2009, Vol. 3, Iss. 1, pp. 41–48 41 doi: 10.1049/iet-cds:20080156 & The Institution of Engineering and Technology 2009 www.ietdl.org
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Published in IET Circuits, Devices & SystemsReceived on 5th June 2008Revised on 12th November 2008doi: 10.1049/iet-cds:20080156
ISSN 1751-858X
New building block: multiplication-modecurrent conveyorY.-S. Hwang W.-H. Liu S.-H. Tu J.-J. ChenDepartment of Electronic Engineering, National Taipei University of Technology, Taipei 106, Taiwan, Republic of ChinaE-mail: [email protected]
Abstract: A new building block called the multiplication-mode current conveyor (MMCC) is proposed here. Thestructure consists of a differential voltage current conveyor (DVCC) and a folded Gilbert cell without any otherauxiliary circuits. Based on the MMCC, a four-quadrant analogue multiplier is designed in TSMC 0.35 mmCMOS 2P4M processes with power supply +1.65 V. HSPICE post-layout simulation results show that themaximum DC operating range is +200 mV, the loading range is from 1 to 10 kV, the bandwidth is about90 MHz, the total harmonic distortion (THD) is 0.85%, the power consumption is 1.08 mW and the chip areawithout pads is 0.48 � 0.36 mm2. The new square summer and analogue divider applications employingMMCCs are also presented.
1 IntroductionThe current-mode circuits are proven to offer several advantagesover their voltage-mode counterparts [1, 2]. The second-generation current conveyor (CCII) has been receivingsignificant attention in current-mode filters [3, 4]. Moreover,many current-mode analogue signal processing applicationsare presented by using CCIIs [5–7]. Some different types ofcurrent conveyors are also proposed [8–10]. But they have thesame features which the addition and/or subtraction of theinput voltages use. On the other hand, the multiplier is a veryuseful building block in the modulator, adaptive filter,artificial neural network etc [11, 12]. It is often categorised asthe single-quadrant (inputs are both unipolar), two-quadrant(one of the inputs is bipolar) and four-quadrant (inputs areboth bipolar) circuits. The basic idea of the multiplier is thatthere are two input signals applied to a nonlinear devicecharacterised by a high-order polynomial function.The polynomial function involves many nonlinear terms andthese terms must be cancelled to reduce the total harmonicdistortion (THD). In the recent years, a lot of differentarchitectures of analogue multipliers based on CCIIs areproposed [13–15]. In the article, we propose a newarchitecture called the multiplication-mode current conveyor(MMCC) that combines the advantages of the differentialvoltage current conveyor (DVCC) and the folded Gilbert cell[16] four-quadrant multiplier to provide both voltage and
Circuits Devices Syst., 2009, Vol. 3, Iss. 1, pp. 41–4810.1049/iet-cds:20080156
current signals from the outputs without any other auxiliarycircuits. The circuit description of the proposed MMCC isintroduced in Section 2, and the simulation results of theMMCC are shown in Section 3. Section 4 proposes thesquare summer and the analogue divider applications. Finally,the conclusion is made in Section 5.
2 Circuit descriptionsThe circuit symbol of the DVCC is shown in Fig. 1.Basically, the terminal relationship of an ideal DVCC canbe given by the following matrix
IY1
IY2
VX
IZ
2664
3775 ¼
0 0 0 00 0 0 01 �1 0 00 0 +1 0
2664
3775
VY1
VY2
IX
IZ
2664
3775 (1)
where the plus sign represents the positive DVCC and theminus one represents the negative DVCC, respectively.
The CMOS circuit of the positive DVCC [8] is shown inFig. 2. The circuit structure consists of additional differentialpair and the CCII. The input stage (M1 and M2, M7 andM8) adopts two differential pair and provides two inputs,Y1 and Y2. The high-gain stage is composed of an activecurrent mirror (M3–M6) which converts the differential
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currents to a single-ended output current (M9 and M10), andothers (M13–M18) provide the bias currents. In addition, thetransistors (M11 and M12, M19 and M20) make a copy ofcurrent signal from the input stage, so the output currentsof X and Z terminals are equal.
Considering the open loop gain (Ao) of the first stage, thevoltage relationship between X, Y1 and Y2 can berepresented as
VX ¼ Ao(VY1 � VY2) (2)
When the unity-gain negative feedback applied from theoutput node (X terminal) to the input terminal (gate of M7),and the open loop gain is much larger than one, therelationship between the output and input voltages can berepresented as follows
VX ¼Ao
1þ Ao
(VY1 � VY2) ’ VY1 � VY2 (3)
Figure 1 Circuit symbol of DVCC
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The CMOS folded Gilbert cell [16] is shown in Fig. 3, and itis modified from the Gilbert cell and owns the larger inputcommon-mode range than the traditional one. The outputvoltage of the folded Gilbert cell can be derived from astraightforward circuit analysis and yields
where Kn and Kp are the transconductance parameters ofNMOS and PMOS, and Rout is the output load resistanceof the folded Gilbert cell, respectively.
The advantages of the DVCC and the folded Gilbert cellare now combined and extended to a new building blockcalled the MMCC shown in Fig. 4. The M1 to M6 arethe folded Gilbert cell, and the M7 to M8 are the diode-connection active loads to achieve higher linearity. Inaddition, the fully differential circuit with diode-connectionloads does not need any common-mode feedback network;it can simplify the structure of the MMCC. The M9 to
Figure 2 CMOS circuit of positive DVCC
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Figure 3 CMOS folded Gilbert cell
:
M13 are the bias current sources to get the suitable operationpoint. Because the proposed MMCC is designed to be thesingle-ended input rather than the differential one inthe folded Gilbert cell, the Vb1 and Vb2 are connected tothe DC bias voltages. The M14 to M17 are the level-shiftcircuit, and it makes the input signals to shift theappropriate DC levels. Therefore the input common-modelevel can be obtained as (VDDþ VSS)/2.
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The DVCC is designed and followed by the folded Gilbertcell. To achieve higher linearity, the M24–M25 and M28–M29 are the diode-connection loads with symmetricaltopologies which are different from the current mirror loadsof Fig. 2. According to the characteristic of the DVCC, itgets the differential input signals from the outputs of thefolded Gilbert cell, and passes the multiplication result tothe X terminal of the DVCC. On the other hand, we use
Figure 4 CMOS circuit of proposed MMCC
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the current mirrors (M26–M27 and M32–M37) to copy thecurrent from the X terminal to the Z terminal. The functionof the proposed MMCC is as follows
IY1 ¼ IY2 ¼ 0 (5)
VX ¼ KVY1VY2 (6)
IZ ¼ IX (7)
where K is the constant. The circuit symbol of proposedMMCC is shown in Fig. 5.
3 Simulation resultsThe proposed MMCC is designed using TSMC 0.35 mCMOS 2P4M processes. The major parameters of theTSMC 0.35 mm CMOS 2P4M processes areCoxjn ¼ 3.63 � 1023 F/m2, Coxjp ¼ 2.84 � 1023 F/m2,Vthjn ¼ 0.55 V, Vthjp ¼ 20.77 V, ln ¼ 0.06 V21,lp ¼ 0.1 V21, Kn ¼ 1.03 � 1024 A/V2, Kp ¼ 2.58 �1025 A/V2. The circuit performance is verified by theHSPICE post-layout simulation. The power supplies usedare VDD ¼ –VSS ¼ 1.65 V because of employing theTSMC 0.35 mm CMOS 2P4M process with a 3.3 Vstandard voltage. The value of K is 0.2267 (unit: V21). Thebias voltages Vb1 ¼ Vb2 ¼ 0 V, Vb3 ¼ 20.8 V andVb4 ¼ 20.7 V.
The DC transfer curve of the proposed MMCC is shownin Fig. 6, where VY1 is varied from 2200 to 200 mV, and VY2
is a DC signal between +200 mV in 0.05 V steps. The DCoperating range is between +200 mV and the outputcommon-mode level is at DC 0 V. The simulation result
Figure 5 Circuit symbol of MMCC
Figure 6 DC transfer curve of MMCC
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demonstrates the four-quadrant operation of analoguemultiplier. The AC gain response of the proposed MMCCis shown in Fig. 7, and the bandwidth is about 90 MHz.For the transient responses, the terminal Y1 inputs a400 mVP-P sinusoidal wave of 1 MHz shown in Fig. 8a;and the terminal Y2 inputs the same amplitude of 20 MHzshown in Fig. 8b. The output voltage signal of X terminalis shown in Fig. 8c and the multiplication result ofamplitude modulation can be found. Next, we put the1 kV load at the X terminal and the same load at the Zterminal. The simulated current wave of X terminal isshown in Fig. 9a and the output current wave of Zterminal is shown in Fig. 9b. The currents of the X and Zterminals are always followed to verify the function ofcurrent conveyance. The loading effect for resistor less than1 kV added to node X will cause the larger currentmismatch. The output transient response of frequencydoubler is shown in Fig. 10c with both 400 mVP-P inputsine and cosine signals of 1 MHz shown in Figs. 10a and10b, respectively. From Fig. 10c, a 2 MHz output sine wave
Figure 7 Gain response of MMCC
Figure 8 Voltage transient responses of MMCC
a Input Y1
b Input Y2
c Output X
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is obtained to show the double frequency of input signals.Fig. 11 shows the THD against the input amplitude from10 to 110 mV, and the THD of presented MMCC is0.85% which is lower than 1.3% of [8] under a 2 MHzinput signal. The THD is well controlled below 1% and itshows the good linearity of proposed MMCC. Finally, thephysical layout of proposed MMCC is shown in Fig. 12 andthe total chip area without pads is about 0.48 � 0.36 mm2
and the power dissipation is 1.08 mW.
4 ApplicationsTwo application circuits of the proposed MMCC arereported in this section. First, the square summer is shownin Fig. 13. The square rooter following the square summeris a special case of vector summation circuit. The vector
Figure 10 Transient response of frequency doubler
a Input Y1
b Input Y2
c Output X
Figure 9 Current transient responses of MMCC
a X terminalb Z terminal
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summation circuit has found applications in instrumentation,communication and neural network. For example, it is usefulin Fourier spectral analysis and neural computation [17].Only two MMCCs and two grounded resistors are used inthe proposed square summer. The output current can bederived as
Io ¼KV 2
Y1
Rþ
KV 2Y2
R¼
K
R(V 2
Y1 þ V 2Y2) (8)
Figure 11 THD comparison between MMCC and [8]
Figure 12 Chip layout of proposed MMCC
Figure 13 Proposed square summer
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Figure 14 DC transfer curve of square summer
To verify the function of proposed square summer, the DCtransfer curve is shown in Fig. 14, where VY1 is variedbetween +200 mV, and VY2 is a DC signal between+200 mV in 0.01 V steps. The value of load resistor R isequal to 1 kV. For the transient responses, we input both400 mVP-P sinusoidal waves of 1 MHz in VY1 and VY2
shown in Figs. 15a and 15b, respectively. The output signalis shown in Fig. 15c for the square summer.
The second application of MMCC is the analogue divider.Fig. 16 shows the proposed divider circuit that employs only aMMCC, a CCII and two grounded resistors. Here, the CCIIis used as a voltage to current converter. The Z terminal output
Figure 15 Transient responses of square summer
a Input Y1
b Input Y2
c Output signal
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impedances Ro of both CCII and MMCC, and the loadimpedance RL are taken into account. Based on the routineanalysis, we can obtain the following equation
Vo ¼VY1
R=(RL==Ro=2)� KVY2
(9)
If (RL//Ro/2)� R, the analogue division function can beobtained as
Vo ¼�VY1
KVY2
(10)
The DC transfer curve of proposed divider is shown in Fig. 17,where the value of VY1 is equal to 20.01 V, and VY2 is a DCsignal between +100 mV. For the transient responses, theAC input VY1 is a triangle wave between 210 mV and10 mV, and VY2 is switched between two symmetricalconstant values (+100 mV) at a frequency of 1 MHz shownin Figs. 18a and 18b, respectively. Fig. 18c shows the outputramp waveform and the division result can be found.
Figure 16 Proposed analogue divider
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Figure 17 DC transfer curve of proposed analogue divider
In addition, a comparison of analogue divider between previouspublications and this work is shown in Table 1.
5 ConclusionA new CMOS MMCC and its two applications usingTSMC 0.35 mm 2P4M processes are proposed in thisarticle. The MMCC provides not only multiplication-mode voltage output but also current output. The proposedsquare summer and analogue divider exhibit the simplerstructures and good performances. The simulation resultsconfirm the theoretical analysis. The proposed circuits areuseful for current-mode analogue signal processing.
6 AcknowledgmentsThe authors would like to thank the reviewers for valuablesuggestions. The authors would also like to thank the ChipImplementation Center of Taiwan for the processsupporting. This work was supported in part by theNational Science Council of Taiwan under Grant NSC 97-2221-E-027-106.
7 References
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