Abstract—This paper describes a new design for a fault tolerantH-bridge dc–dc converter. Fault tolerance is achieved using a mul-tilevel converter topology in combination with a pulsewidth mod-ulation control strategy allowing a large set of converter switchingstates to produce bidirectional power flows at any required outputvoltage. For a given converter open-circuit or short-circuit fault, allpotential switch combinations are compared in terms of converterlosses and output voltage harmonics to identify the most suitableswitching combinations to achieve the prefault output voltage level.The fault tolerant ability of the proposed converter to recover therequired output voltage is verified by both computer simulationsand experimentally using a 1 kW laboratory set.
Index Terms—DC–DC power conversion, fault tolerance, har-monic analysis, losses, multilevel system.
I. INTRODUCTION
DC–DC converters are commonly used in a wide variety ofapplications, including a number of critical applications
in which very high levels of reliability are required because theloss of converter operation can have serious consequences. Forexample, control of a car is lost when the supply voltage fora brake-by-wire system has collapsed due to a converter fail-ure. Another critical application is the use of a dc–dc converterin low-power refrigeration applications developed for use inan ambulance to maintain saline temperature within a specificrange for immediate injection into a patient [1]. In such an ap-plication, the loss of control of the converter voltage can lead toa temperature difference of several degrees and serious medicalcomplications.
In order to achieve highly reliable dc–dc conversion sys-tems, N+M redundancy concepts have been proposed in thepast [2], [3]. This is a costly option in which one or more ad-ditional dc–dc converters are connected in parallel to achievethe required levels of redundancy in case of failure of themain converter. More recently, it has been shown that multi-level dc–ac converter topologies can be operated as fault tol-erant circuits [4]–[6]. Multilevel dc–dc converters with multi-ple dc sources and no magnetic storage components have beenproposed recently to achieve variable dc output voltage opera-tion [7]. Initial investigations of the multilevel concept as ap-plied to dc–dc converters for fault tolerant applications have alsobeen presented [8]–[10]. Khan et al., for example, described a
Manuscript received August 6, 2009; revised October 7, 2009. Current versionpublished June 3, 2010. Recommended for publication by Associate EditorU. K. Madawala.
The authors are with the School of Electrical, Electronic and Com-puter Engineering, Newcastle University, Newcastle Upon Tyne NE1 7RU,U.K. (e-mail: [email protected]; [email protected]; [email protected]).
Digital Object Identifier 10.1109/TPEL.2009.2038217
Fig. 1. Power circuit of the HBALSC multilevel dc–dc converter.
pseudo fault tolerant modular multilevel dc–dc converter [9],which could continue to operate in the event of a short cir-cuit fault in any of the series connected modules; the circuit,however, could not operate successfully if one of its power de-vices had experienced an open circuit fault, as recognized by theauthors.
In this paper, a “true” fault tolerant multilevel dc–dc con-verter based on the multilevel H-bridge inverter topology pro-posed by Ceglia et al. [11] is developed and its fault tolerantbehavior is investigated. The original circuit, as proposed byCeglia et al., suffers from a number of potential problems anddrawbacks when operated as a dc–dc converter including highoperational losses and long term reliability problems, as someof the switches are required to conduct permanently. In this pa-per, a new pulsewidth modulation (PWM) control strategy isdeveloped and applied to a modified circuit topology, in whichthe original converter is extended by the addition of an extraswitching leg and bidirectional selector switches, to overcomethese problems.
Fig. 1 shows the proposed H-bridge with auxiliary leg andselector cells (HBALSC) fault tolerant multilevel dc–dc con-verter. The main H-bridge power circuit (power devices S1–S4 and diodes D1–D4) is extended by two auxiliary switches(SA1/DA1 and SA2/DA2), three selector cells (power devicesS5-S7, diodes D5-D16 and bidirectional switches SE1–SE3)and six additional bidirectional switches (SE4–SE9) to formthe multilevel topology. Fault tolerant operation is achievedby using different switching states and controlling the PWMduty cycles of the individual switches to produce the required
1510 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 6, JUNE 2010
TABLE ISWITCHING STATES FOR EACH VOLTAGE LEVEL
average output voltage with the minimum number of switchesand power diodes.
The paper examines different fault scenarios to demonstratethe full fault tolerant capacity of the proposed converter. Differ-ent combinations of switching states and duty cycles are eval-uated and compared in terms of power losses and generatedoutput voltage harmonics to identify the most suitable conduc-tion states to achieve the required output. The variety of switch-ing combinations and PWM duty cycles provide fault tolerantoperation.
II. OPERATING PRINCIPLES OF THE PROPOSED CONVERTER
The operation of the H-bridge, dc–dc HBALSC converter(connected to a resistive load) under normal operating condi-tions is described in this section.
The HBALSC converter allows bidirectional power flow and,depending on the switching states used, can produce nine differ-ent output voltage levels (−120, −90, −60, −30, 0, 30, 60, 90,and 120 V) when operating without PWM control, as shown inTable I. The application of PWM control allows operation at anyrequired average voltage between −120 and +120 V. It shouldbe noted here, that the circuit cannot achieve the redundancyneeded for fault tolerant operation by varying the switchingstates alone; each voltage level can be generated by only oneswitch combination as shown in Table I. The current path forthe conduction state corresponding to an output voltage of 30 Vis shown in Fig. 2 as an example.
In the following analysis, only forward power flow switchcombinations will be considered (i.e., no negative voltageswitching states will be described).
Fig. 3 shows four output voltage levels VLn with PWM con-trol at a fixed duty cycle D and a constant switching frequency.Assuming each voltage level is applied for an equal time T/4(see Fig. 3), the average output voltage V0 can be calculatedfrom
Vo =D
m
m∑
n=1
VLn (1)
where D is the duty cycle, m is the number of voltage levels andVLn is the output voltage associated with level n.
Equation (1) shows that the different switching states can pro-duce a large number of possible output voltages when combinedwith all the possible values of converter duty cycle D. For exam-ple, Table II shows five possible switching states combinations
Fig. 2. Current path for conduction state corresponding to 30-V output voltage.
Fig. 3. Output voltage levels.
TABLE IIPOSSIBLE SWITCH COMBINATIONS TO GENERATE 60 V AVERAGE OUTPUT
with different values of D to generate a 60 V average outputvoltage.
The operation of the converter was investigated using PSpicesimulation and verified experimentally. Models provided bysemiconductor manufacturers were used for the power de-vices and diodes. A 1 kW prototype IGBT test circuit wasalso constructed to test the operation of the proposed circuit
AMBUSAIDI et al.: NEW CIRCUIT TOPOLOGY FOR FAULT TOLERANT H-BRIDGE DC–DC CONVERTER 1511
Fig. 4. Measured output voltage waveform for Vo = 60 V; PWM duty cycleD = 0.75 with voltage levels of 30, 90, and 120 V, respectively.
Fig. 5. Measured output voltage waveform for Vo = 60 V; PWM duty cycleD = 0.57 with voltage levels of 90 and 120 V, respectively.
topology. The converter was fed from four 30 V power suppliesand operated with a 5 kHz switching frequency.
Figs. 4–6 show measured output voltages for three diffe-rent device switching combinations (states 1, 3, and 5 inTable II). It is apparent from the figures that PWM control allowsalternative switching options for the required output voltagelevel. Converter operation with the same switch combinationswas also simulated using PSpice showing good agreement withmeasurement.
III. EVALUATION OF CONVERTER LOSSES AND HARMONIC
CHARACTERISTICS
In this section, different switching combinations will be eval-uated in terms of the resulting converter power losses and outputvoltage harmonics in order to investigate the operating charac-teristics of the converter and identify the switch combinationsneeded to achieve the best overall performance for a given outputvoltage.
Fig. 6. Measured output voltage waveform for Vo = 60 V; PWM duty cycleD = 0.5 with voltage level of 120 V.
A. Converter Power Losses
Converter conductions and switching power losses and theresulting converter efficiencies when operating at two outputvoltages of 45 and 75 V, respectively, with different switch com-binations were calculated and the results are shown in Tables IIIand IV. Output voltage levels VLn are lower than the valuesof the input power supply voltages because of the conductionvoltage drops across the converter devices.
The lowest power losses are achieved when operating theconverter with one output voltage level of 120 V where thecurrent path contains only two power devices (S1 and S4). Incontrast, the highest losses are obtained when the converter isoperated with the maximum number of output voltage levelswhen the current flows through more than two power devicesand two diodes increasing the total power loss. It is also evidentthat losses are a function of the duty cycle. A larger duty cyclemeans longer conduction times and higher power losses.
B. Harmonic Analysis of Converter Output Voltage Waveforms
Power switching devices produce harmonics because of theirnonlinear characteristics. In this section, the harmonic contentof converter output voltage waveforms when operating at outputvoltages of 45 and 75 V with different switch combinations werecalculated and the results are shown in Figs. 7 and 8.
As expected, the frequency spectra of the output voltagewaveforms have the same dc value at zero frequency. The am-plitudes of the harmonic orders are different, however, mainlydue to the different values of duty cycles used and the differ-ent shapes of the resulting time domain waveforms. Figs. 7 and8 show that higher values of PWM duty cycle result in loweroutput voltage harmonics, regardless of the number of levelsof the output voltage. For example, Fig. 7 shows that the threelevels switching combination (30, 60, and 90 V, and D = 0.75)produces lower output voltage harmonics than the four levelsswitching combination (30, 60, 90, and 120 V, and D = 0.6)with a significant reduction in the value of the first (5 kHz)harmonic. Similar results can be observed in Fig. 8, where the
1512 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 6, JUNE 2010
TABLE IIICALCULATED POWER LOSSES AND EFFICIENCIES; Vo = 45 V
Fig. 7. Harmonic spectrum of output voltage Vo = 45 resulting from switchcombinations described in Table III.
Fig. 8. Harmonic spectrum of output voltage Vo = 75 resulting from switchcombinations described in Table IV.
switching combination with D = 1 (voltage levels 30, 60, 90,and 120 V) produces the lowest output voltage harmonics. Tosum up, higher values of PWM duty cycles result in lower out-put voltage harmonics but at the cost of higher converter lossesand lower operating efficiencies. The control of the converter isthus a compromise between these two conflicting requirements.
Fig. 9. Voltage sensor circuit.
IV. FAULT TOLERANT INVESTIGATIONS
Assuming the occurrence of only one fault at a given time,constant input voltage, no loss of sensor signals and no con-nection faults, the fault tolerant behavior of the converter isevaluated using the 60 V operating states discussed in SectionII as an example. The converter must demonstrate the abilityto detect a short circuit or an open circuit component fault andmust change the switching states appropriately to recover therequired average output voltage.
A. Description of the Test Circuit
Three IXYS power modules of the type (FIO 50–12BD)each consisting of a single IGBT and four diodes were usedto implement selector cells S5–S7 and D5–D16 . One IXYSpower module (FII 40–06D), comprised of two IGBTs withtwo antiparrallel diodes, was used for each leg of the mainH-bridge circuit (S1–S4 , D1–D4) as well as the auxiliary leg(SA1–SA2 , DA1–DA2). The current sensors used in the cir-cuit were Hall-effect LEM current transducers (LTS 15-NP).Optocouplers (PC123XNNSZ0 F) were used to sense a shortcircuit fault across the IGBTs and diodes as shown in Fig. 9.A Dspic30F5015 controller was used to generate the requiredPWM control signals and to affect the appropriate change incircuit topology on detecting a fault.
AMBUSAIDI et al.: NEW CIRCUIT TOPOLOGY FOR FAULT TOLERANT H-BRIDGE DC–DC CONVERTER 1513
The total number of sensors is low when compared with al-ternative circuit topologies [8]. However, the number of currentsensors can be reduced even further by monitoring the outputvoltage using a neural network technique [12] or by using a smartIGBT gate drive with self-diagnosis and fault protection [13].The complete fault tolerant HBALSC multilevel H-bridge dc–dcconverter is shown in Fig. 10.
B. Open Circuit Faults
If an open circuit fault occurs in any of the main switchesS1–S4 or D1–D4 , the extended additional leg must be activated.The switching sequence following an open circuit fault in S1 isdiscussed here in detail as an example. A summary of controlleractions following an open circuit in any device is presented inTables V and VI in the Appendix.
Under normal operating conditions, S1 is switched ON andthe controller receives a current measurement from CS4 . If thecontroller does not receive this signal while S1 is still switchedON, the controller will flag this as an open circuit fault in S1 .The controller now identifies a new switching state that needsto be activated, in this case switches SA1 and SE8 , in order toprovide the required voltage. Fig. 11 shows the timing diagramcorresponding to this event. At t = 0.75 ms, the device becomesfaulty. The current transducer delay plus the signal delay timefrom the controller to the drive circuit for S1 is td = 50 µs andthe time that the controller needs to select a new switching stateand to send the required gate signal is 70 µs giving a total faultresponse time of 120 µs (see Fig. 11). Fig. 12 shows how SA1and SE8 are switched on to maintain normal operation at thesame output voltage when an open circuit fault occurs in S1 .After the fault, the current passing through S1 falls to zero, butload current continues to flow through SA1 and SE8 .
If an open circuit fault occurs in any of the selector switchingcells (devices S5–S7, diodes D5–D16 and bidirectional switchesSE1–SE3), the converter will no longer be able to produce the
Fig. 11. Timing diagram for open circuit fault in S1 : (a) output voltage, (b)current sensor signal, (c) gate signal of the faulty power device, and (d) gatesignal of the on coming power device.
Fig. 12. Measured output voltage waveform before and after an open circuitfault in main switch S1 .
required average output voltage using the existing switch statecombination. For example, under normal operating conditions,the converter produces output voltage levels of 30, 60, 90, and120 V with a duty cycle D = 0.8 to generate the required averageoutput voltage of 60 V. If an open circuit fault were to occurin switch S5 say, the converter is no longer able to produce avoltage level of 90 V leading to the loss of the required 60-Voutput voltage. On detecting the fault, the sequence of switchingstates needs to change to operate the converter at 120 V and aduty cycle D = 0.5 (to minimize losses). Fig. 13 shows measuredoutput voltage waveform when open circuit fault occurs in S5 ,showing converter operation with the above conduction statesbefore and after the fault at the same average output voltage.The current passing through S5 (see Fig. 13) becomes zero afterthe fault.
If an open circuit fault occurs in any of the H-bridge devices(power devices S1–S4, diodes D1–D4 and bidirectional switchesSE4–SE7), the switches in the auxiliary converter leg (SA1 andbidirectional switch SE8) will be activated to supply the loadwith same voltage.
Similar results are obtained when simulating the operation ofthe circuit under the same fault conditions.
1514 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 6, JUNE 2010
TABLE IVCALCULATED POWER LOSSES AND EFFICIENCIES; Vo = 75 V
Fig. 13. Measured output voltage waveform before and after an open circuitfault in selector switch S5 .
Fig. 14. Timing diagram for short circuit fault in S5 : (a) output voltage, (b)voltage sensor signal, (c) gate signal for the faulty power device, and (d) gatesignal of the on coming power device.
C. Short Circuit Faults
Diode short circuit faults are detected using the voltage sen-sor circuits shown in Fig. 9; short circuit faults in the powerdevices are detected via the gate drive circuits. On detection,short circuit faults are isolated by deactivating the correspond-ing selector switch. The control of the system under short-circuitfault conditions is more complex when compared with open cir-cuit faults responses due to the large number of voltage sensors
Fig. 15. Measured output voltage waveform before and after a short circuitfault in selector switch S5 .
and switches needed to detect and isolate each fault. The switch-ing sequence following a short circuit fault in S5 is discussedhere as an example.
Fig. 14 shows the timing diagram corresponding to a shortcircuit fault in S5 . On detecting the fault, SE1 and SE4 areswitched OFF and SE8 and SA1 switched on to initiate the newconduction state. Fig. 14 shows the timing of the events cor-responding to this short circuit fault including voltage sensordelay tS (130 µs) and controller delay tC (70 µs). The delaywhen changing from one switch combination to another due tothe slow response of the Omron G8P-1A4P electromechanicalsingle-pole relays used to implement the bidirectional selectorswitches (SE1–SE9) in this experimental setup (td1 + td2 = 5ms) is also shown.
Similar responses are required for short circuit faults in anyof the main H-bridge switches. A summary of controller actionsfollowing a short circuit in any device is presented in Tables Vand VI in the Appendix.
In the experimental investigation, a short-circuit fault con-dition was generated by switching an additional power deviceconnected in parallel with the device to be tested. Fig. 15 showsthe measured output voltage waveform before and after a shortcircuit fault selector switch S5 .
AMBUSAIDI et al.: NEW CIRCUIT TOPOLOGY FOR FAULT TOLERANT H-BRIDGE DC–DC CONVERTER 1515
V. CONCLUSION
A novel, fault tolerant multilevel H-bridge dc–dc convertertopology has been presented in this paper. Different switchingstates are combined with PWM control to produce and main-tain a constant average output voltage despite the occurrenceof converter open circuit and short circuit faults. The perfor-mance of the new fault tolerant circuit topology is analyzedin terms of power losses, efficiencies and output voltage har-monics. Experimental results obtained with a prototype 1 kWcircuit have been presented to verify the proposed design anddemonstrate the ability of the converter to achieve fault tolerantoperation.
APPENDIX
TABLE VFAULT TOLERANT INVESTIGATIONS IN THE DIODES
TABLE VIFAULT TOLERANT INVESTIGATIONS IN THE POWER DEVICES
ACKNOWLEDGMENT
This paper has not been presented at a conference or submittedelsewhere previously.
REFERENCES
[1] M. R. Holman and S. J. Rowland, “Design and development of anew cryosurgical instrument utilizing the Peltier thermoelectric ef-fect,” J. Med. Eng. Technol., vol. 21, no. 3–4, pp. 106–110,1997.
[2] P. A. Kullstam, “Availability, MTBF and MTTR For repairable M out ofN system,” IEEE Trans. Rel., vol. R-30, no. 4, pp. 393–394, Oct. 1981.
[3] R. V. White and F. M. Miles, “Principles of fault tolerance,” in Proc. IEEEAppl. Power Electron. Conf. Expo.—APEC, San Jose, Cost Rica, 1996,pp. 18–25.
[4] A. Chen, L. Hu, L. Chen, Y. Deng, and X. He, “A multilevel convertertopology with fault-tolerant ability,” IEEE Trans. Power Electron., vol. 20,no. 2, pp. 405–415, Mar. 2005.
[5] X. Kou, K. A. Corzine, and Y. L. Familiant, “A unique fault-tolerant designfor flying capacitor multilevel inverter,” IEEE Trans. Power Electron.,vol. 19, no. 4, pp. 979–987, Jul. 2004.
[6] B. Francois and J. P. Hautier, “Design of a fault tolerant control systemfor a N.P. C. multilevel inverter,” in Proc. IEEE Int. Symp. Ind. Electron.,L’Aquila, Italy, 2002, vol. 4, pp. 1075–1080.
[7] S. Miaosen, P. F. Zheng, and L. M. Tolbert, “Multilevel DC-DC power con-version system with multiple DC sources,” IEEE Trans. Power Electron.,vol. 23, no. 1, pp. 420–426, Jan. 2008.
[8] K. Ambusaidi, V. Pickert, and B. Zahawi, “Computer aided analysis offault tolerant multilevel DC-DC converters,” in Proc. IEEE Conf. PowerElectron., Drives Energy Syst. Ind. Growth, New Delhi, India, 2006, pp.1–6.
[9] F. H. Khan and L. M. Tolbert, “Multiple load-source integration in a mul-tilevel modular capacitor clamped dc/dc converter featuring fault tolerantcapability,” IEEE Trans. Power Electron., vol. 24, no. 1, pp. 14–24, Jan.2009.
1516 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 6, JUNE 2010
[10] V. Choudhary, E. Ledezma, R. Ayyanar, and R. M. Button, “Fault tolerantcircuit topology and control method for input-series and output-parallelmodular DC-DC converters,” IEEE Trans. Power Electron., vol. 23, no. 1,pp. 402–411, Jan. 2008.
[11] G. Ceglia, V. Guzman, C. Sanchez, F. Ibanez, J. Walter, and M. I. Gimenez,“A new simplified multilevel inverter topology for DC-AC conversion,”IEEE Trans. Power Electron., vol. 21, no. 5, pp. 1311–1319, Sep. 2006.
[12] S. Khomfoi and L. M. Tolbert, “Fault diagnostic system for a multilevelinverter using a neural network,” IEEE Trans. Power Electron., vol. 22,no. 3, pp. 1062–1069, May 2007.
[13] C. Lihua, F. Z. Peng, and C. Dong, “A smart gate drive with self-diagnosisfor power MOSFETs and IGBTs,” in Proc. 23rd Annu. IEEE Appl. PowerElectron. Conf. Expo. (APEC 2008), pp. 1602–1607.
Khalid Ambusaidi received the B.Sc. degree in elec-trical and electronics engineering from Sultan Qa-boos University, Muscat, Oman, in 2000 and theM.Sc. degree in electrical engineering from Newcas-tle University, Newcastle Upon Tyne, U.K., in 2005.He is currently working toward the Ph.D. degree inpower electronics system at the School of Electri-cal, Electronic and Computer Engineering, Newcas-tle University.
His current research interests include fault tolerantdc/dc converters.
Volker Pickert (M’04) received the Dipl.-Ing. de-gree in electrical and electronic engineering fromRheinisch-Westfalische Technische Hochschule,Aachen, Germany and the University of Cambridge,Cambridge, U.K., in 1994, and the Ph.D. degree fromNewcastle University, Newcastle Upon Tyne, U.K.,in 1997.
In 1998, he joined Semikron International,Nurnburg, Germany, as an Application Engineer andtwo years later he worked for Volkswagen, Medford,MA, where he became the Group Leader for the de-
velopment of electric drives for electric vehicles. Since 2003, he has been a Se-nior Lecturer at the School of Electrical, Electronic and Computer Engineering,Newcastle University. His current research interests include power electronicsfor automotive applications, thermal management, fault tolerant converters andadvanced nonlinear control.
Bashar Zahawi (M’96–SM’04) received the B.Sc.and Ph.D. degrees in electrical and electronic engi-neering from Newcastle University, Newcastle UponTyne, U.K., in 1983 and 1988, respectively.
From 1988 to 1993, he was a Design Engineer atCortina Electric Company Ltd., a U.K.-based man-ufacturer of large ac variable speed drives and otherpower conversion equipment. In 1994, he joined asa Lecturer in electrical engineering at the Universityof Manchester, Manchester, U.K. Since 2003, he hasbeen a Senior Lecturer at the School of Electrical,
Electronic and Computer Engineering, Newcastle University. His current re-search interests include small-scale distributed generation, power conversion,and the application of nonlinear dynamical methods to electrical circuits andsystems. He is also a Chartered Electrical Engineer.
Dr. Zahawi is a recipient of the Crompton Premium Award of the IEE.
