New class of t-error correcting and all unidirectional error detecting (t-EC/AUED) codes S. Nandi P.P. Chaudhuri Indexing terms: Error correction, Error detection, Hamming distance, Unidirectional errors, Random errors, Parity check codes, Symmetric errors Abstract: A new class of t-error correcting and all unidirectional error detecting (t-ECIAUED) codes with reduced number of check bits is presented. The encoding/decoding algorithms for this class of codes can be implemented with faster as well as simpler hardware. The ROM implementation of the proposed scheme results in significant saving of word length. List of symbols N(X, Y) = number of 1 + 0 crossovers from X to Y D(X, Y) = Hamming distance between X and Y D(C) = minimum distance of a code C W(X) = weight or number of 1s in X A(X, Y) = max {N(X, Y), N(Y, X)} : asymmetric dis- LZj rZ1 N(C) = minimum number of 1 + 0 crossover of a k n = k number of information bits and parity check bits for t-error correcting (t-EC) code n* = n bits t-EC code and additional check bits for t-ECIAUED code tance between X and Y = the largest integer less than or equal to 2 = the smallest integer greater or equal to Z code C = number of information bits 1 Introduction For digital information transfer and storage, error correcting/detecting codes are extensively used. Various error control codes have been proposed to enhance the reliability of a computer system [9, lo]. The errors in digital information systems can be classi- fied into three classes: (a) Symmetric: Both 1 + 0 and O+ 1 errors are equally likely in a codeword. (b) Asymmetric: Only one of the errors 1 + 0 or 0 + 1, can occur in a codeword. The error is known a priori. (c) Unidirectional: Either 1 + 0 or 0 + 1 errors can occur but they do not occur in the same codeword. The causes of errors are transient, intermittent and per- manent faults. Transient faults create a limited number of 0 IEE, 1995 Paper 1512E (C2), first received 6th January and in revised form 27th July 1994 The authors are with the Department of Computer Science and Engin- eering, Indian Institute of Technology, Kharagpur - 721 302, India 32 symmetric errors or multiple unidirectional errors. Inter- mittent faults also lead to a limited number of errors, but permanent faults cause either symmetric or unidirectional errors. Recent research shows that many faults in VLSI circuits (such as the faults that affect address decoders, word lines, power supply and stuck-fault in a serial bus etc. in ROM and RAM memories) cause unidirectional errors [SI. An extensive theory of symmetric error control coding has been developed [9, lo]. It is therefore important to construct classes of codes that simul- taneously correct t-symmetric errors and detect all unidirectional errors. This has motivated researchers to look for optimal codes for systematic t-error correction and all unidirec- tional error detection. Several theories and classes of codes have been developed [l-8, 111, but these are not optimised for systematic t-ECIAUED codes. In this paper, we propose a new method to construct t-EC/ AUED systematic codes. Compared with existing schemes [l, 3, 5, 71, the proposed code employs a simpler encoding/decoding algorithm with lower complexity. The proposed code also achieves better results with respect to number of extra check bits. Furthermore, the ROM word size becomes significantly reduced in the event of ROM based implementation of the hardware. The notation used in this paper, where X and Y are codeword in C, is given in the List of symbols. 2 Let C denote a binary linear systematic t-error correcting (n, k) code with D(C) 2 2t + 1 and C* be a systematic (n*, k) t-EC/AUED code. For a codeword X E C, the codewords in the proposed t-ECIAUED systematic code C* have the following form Fundamental properties of t-EC and t-EC/AUED codes x x,x, x, ..’ x, where the Xis are check bits derived by using Berger’s technique [12]. The appended check bits are used to increase the crossover between two codewords. Prior to deriving the new code, we establish some of the properties of t-EC code through the following theorem and corollary that provide the foundation for the proposed code. Let Ci be the set of all codewords of C with exactly i number of 1s. It should be noted that some of the sets Ci (e.g. C,, C,, ..., Czf) are empty because they cannot satisfy the minimum distance constraint. Example 1 noted below illustrates the sets Ci for (7, 4) Hamming code. IEE Proc.-Comput. Digit. Tech., Vol. 142, No. I, January 1995
Transcript
New class of t-error correcting and all unidirectional error detecting (t-EC/AUED) codes
Abstract: A new class of t-error correcting and all unidirectional error detecting (t-ECIAUED) codes with reduced number of check bits is presented. The encoding/decoding algorithms for this class of codes can be implemented with faster as well as simpler hardware. The ROM implementation of the proposed scheme results in significant saving of word length.
List of symbols
N ( X , Y) = number of 1 + 0 crossovers from X to Y D(X, Y) = Hamming distance between X and Y D(C) = minimum distance of a code C W ( X ) = weight or number of 1s in X A(X, Y) = max { N ( X , Y), N ( Y , X)} : asymmetric dis-
LZj rZ1 N(C) = minimum number of 1 + 0 crossover of a
k n = k number of information bits and parity
check bits for t-error correcting (t-EC) code n* = n bits t-EC code and additional check bits for
t-ECIAUED code
tance between X and Y = the largest integer less than or equal to 2 = the smallest integer greater or equal to Z
code C = number of information bits
1 Introduction
For digital information transfer and storage, error correcting/detecting codes are extensively used. Various error control codes have been proposed to enhance the reliability of a computer system [9, lo].
The errors in digital information systems can be classi- fied into three classes:
(a) Symmetric: Both 1 + 0 and O+ 1 errors are equally likely in a codeword.
(b) Asymmetric: Only one of the errors 1 + 0 or 0 + 1, can occur in a codeword. The error is known a priori.
(c) Unidirectional: Either 1 + 0 or 0 + 1 errors can occur but they do not occur in the same codeword.
The causes of errors are transient, intermittent and per- manent faults. Transient faults create a limited number of
0 IEE, 1995 Paper 1512E (C2), first received 6th January and in revised form 27th July 1994 The authors are with the Department of Computer Science and Engin- eering, Indian Institute of Technology, Kharagpur - 721 302, India
32
symmetric errors or multiple unidirectional errors. Inter- mittent faults also lead to a limited number of errors, but permanent faults cause either symmetric or unidirectional errors. Recent research shows that many faults in VLSI circuits (such as the faults that affect address decoders, word lines, power supply and stuck-fault in a serial bus etc. in ROM and RAM memories) cause unidirectional errors [SI. An extensive theory of symmetric error control coding has been developed [9, lo]. It is therefore important to construct classes of codes that simul- taneously correct t-symmetric errors and detect all unidirectional errors.
This has motivated researchers to look for optimal codes for systematic t-error correction and all unidirec- tional error detection. Several theories and classes of codes have been developed [l-8, 111, but these are not optimised for systematic t-ECIAUED codes. In this paper, we propose a new method to construct t-EC/ AUED systematic codes. Compared with existing schemes [ l , 3, 5, 71, the proposed code employs a simpler encoding/decoding algorithm with lower complexity. The proposed code also achieves better results with respect to number of extra check bits. Furthermore, the ROM word size becomes significantly reduced in the event of ROM based implementation of the hardware.
The notation used in this paper, where X and Y are codeword in C, is given in the List of symbols.
2
Let C denote a binary linear systematic t-error correcting (n, k ) code with D(C) 2 2t + 1 and C* be a systematic (n*, k) t-EC/AUED code. For a codeword X E C, the codewords in the proposed t-ECIAUED systematic code C* have the following form
Fundamental properties of t - E C and t - E C / A U E D codes
x x, x, x, . . ’ x, where the Xis are check bits derived by using Berger’s technique [12]. The appended check bits are used to increase the crossover between two codewords.
Prior to deriving the new code, we establish some of the properties of t-EC code through the following theorem and corollary that provide the foundation for the proposed code.
Let Ci be the set of all codewords of C with exactly i number of 1s. It should be noted that some of the sets Ci (e.g. C,, C,, ..., C z f ) are empty because they cannot satisfy the minimum distance constraint. Example 1 noted below illustrates the sets Ci for (7, 4) Hamming code.
IEE Proc.-Comput. Digit. Tech., Vol. 142, No. I , January 1995
Example 1: Consider the (7, 4) Hamming codet with D(C) = 3. It will be partitioned into subsets CO, C,, C , and C, as shown in Table 1.
Theorem I : VY E Ci and X E C,+k, the following equal- ity holds:
N ( X , Y ) - N ( Y , X ) = k
Proof: There are at least k bits where X has a 1 but Y has 0. Let Y and X be the bit strings obtaind by removing those particular k bits from the respective strings. Hence, W ( X ) and W( Y ) have the same value. So change in bit positions of X and Y occur pairwise, i.e.
N ( X , Y) = N(Y’ , X )
Hence
N ( X , Y ) = N ( X ’ , Y ) + k and
N ( Y , X ) = N ( Y , X )
3 N ( X , Y ) - N ( Y , X ) = k
Corollary I : D ( X , Y ) + k is always even.
Proof.
D ( X , Y ) + k = N ( X , Y) + N ( Y , X ) + k = N ( X , Y ‘ ) + N( Y , X ’ ) + k + k
= 2 N ( X , Y ’ ) + 2k
= 2 [ N ( X ’ , Y’) + k]
t Using parity check generator matnx:
I E E Proc.-Cornput. Digit. Tech., Vol. 142, No . 1, January 1995
From the Theorem 1 and Corollary 1, we get the follow- ing fundamental relations:
( a ) If k = 0 then as per Corollary 1: D ( X , Y ) is even, i.e. D ( X , Y ) > 2t + 2. Hence from Theorem 1, we get:
N ( X , Y ) = N ( Y , X ) 2 t + 1 (1)
(b) For 1 < k < 2 t : (i) if k is odd then as per Corollary 1: D ( X , Y ) is
also odd, i.e. D ( X , Y ) 2 2t + 1. Hence from Theorem 1, we get:
k + l k - 1 N ( X , Y ) > t + - 2 and N ( Y , X ) 2 t - - 2 (2)
(ii) If k is even then as per Corollary 1: D ( X , Y ) is even, i.e. D ( X , Y ) 2 2t + 2. Hence from Theorem 1, we get:
k k N ( X , Y ) 2 t + 1 + - 2 and N ( Y , X ) > t + 1 - - 2 (3)
(c) For k 2 2t + 1, D ( X , Y ) > k. Hence from Theorem 1, we get:
N ( X , Y ) > 2t + 1 and N ( Y , X ) 2 0 (4)
In the above discussions we have derived Some funda- mental properties of t-EC codes which shall be utilised in the next Section to construct the t-ECIAUED code. Below are stated the necessary and sufficient conditions for a code to be t-ECIAUED.
Theorem 2 [SI: A code C* is capable of correcting t- symmetric errors iff D(C*) 2 2t + 1.
Theorem 3 [SI: A code C* can correct t or fewer uni- directional errors, if and only if for all X * , Y* E C* :
for X * , Y* an ordered pair A(X*, Y*) 2 2t + 1 A ( X * , Y*) 2 t + 1 for X * , Y* unordered
Theorem 4 [SI: A code C* is t-ECIAUED if and only if N ( X * , Y*) 2 t + 1 for all X * , Y* E C*.
3
The objective is to construct a t-ECIAUED code (i.e. C*) from a given t-EC code (i.e. C) by appending r* number of extra check bits. These r* check bits (i.e. X , X, X , . . . X,) can be divided into three subsets. The first subset covers the last bit, the second subset is the group of q-bits (where t < 4 < 2t) referred to as ‘last group’ and the third one is the subset consisting of groups each with (t + 1)- bits (Fig. 1). The ‘last group’ with q bits can have values
OOO}. The subset of q-bits are initialised with all 1s. The ‘last group’ of check bits can be derived by left shifting these q-bits. The bit patterns in each of the remaining groups have only two values either 11 . 11 1 or 00 . OOO; that is either all 1s or all Os.
The ‘Procedure find-no-of-bits’ noted below operates on a number of information and parity check bits (i.e. n) and gives a number of appending bits (i.e. r*). It also gen- erates information regarding the number of groups and the number of bits in the ‘last group’, that is the value
procedure find-no-of-bit& last, max, no-of-bits) /* It takes input n (the number of bits in a codeword in C) /* and t (the number of errors to be corrected). /* It gives output no-of-bits that are appended to the codeword in C to form in C*. /* Output ‘last’ gives number of bits in the last group. /* Output ‘rnax’ gives the number of groups in the third subset.
begin temp-t t 2t + 1 ; /* Maximum number of different values that ‘last group’ can have. temp t rn/21; max t 0; while (temp > temp-t)
begin m a x t m a x + 1; temp t [temp/2] ;
end ; last t temp - 1; no-of-bits t max * (t + 1) + last + 1 ;
end:
The procedure noted below generates the extra check bits, i.e. X, X, ... X,. It accepts the number of 1s of a code- word in C as input and other information like ‘last’ and ‘max’ from the previous procedure.
Procedurefind_code(no-of-one, last, max) /* It takes input no-of-one, is the number of Is, W ( X ) in the codeword X E C. /* Inputs ‘last’ and ‘max’ are outputs of the Procedure find-no-of-bits. /* Array ‘group’ gives output of the procedure, i.e. value of the appended r* bits. /* ‘shift-register’ is a group of bits that can be shifted left.
begin set(shift-register) t 1; /* set ‘shift-register’ to all 1 state. for i = 0 to (max + 1)
int[il t 0; /* The ‘int’ array used to store intermediate values of group of bits.
int[O] t no-of-one mod 2; no-of-one t Lno-of-one/2J ; count t 1 ; intcl] + no-of-one mod (last + 1); /* ‘int[l]’ contains number of shift cycles for ‘shift-register’. no-of-one + Lno-of-one/(last + 1 ) ~ ; while (no-of-one > 0)
begin count + count + 1; int[count] t no-of-one mod 2; no-of-one + [no_of_one/2] ;
end ; count t max + 1; while (count > 1)
begin if(int[count] = 1)
else
count t count - 1;
group[count] t 00 . . . OOO;
groupCcount] + 11 . . . 11 1 ;
end;
shiftleft(shift-register); /* Shiftleft shift ‘shift-register’ left by 1 bit. while (int[count] > 0)
group[ 11 t output(shift-register); /* Store output of ‘shift-register’ to ‘group[l]’.
group[O] t 0;
groupCO] + 1 ;
if(int[O] = 1)
else
end ;
Table 2 illustrates the Procedure find-code for r* = 4 and 5 and t = 1. Table 3 shows (11, 4) t-ECIAUED codes generated by the proposed scheme.
34 IEE Proc.-Cornput. Digit. Tech., Vol. 142, No. I , January I995
Table 2: Output of the procedure find-code for r* = 4 and 5 and t = 1 ~-
r * = 4 r* = 5
Number of X , X , X,. Number of X , X , X , 1s in C
We now prove that the above procedure results in a t-EC/AUED codes C*. Let ( X , X , , X , , ..., X,) and ( Y , Y,, Y , , . . . , Ye) be two codewords in C* constructed using the above procedure. The r* check bits, as discussed earlier, are divided into three subsets. Let for a codeword X * in C* the subsets be denoted as S,,, S,, and S 3 , . The subsets S,,, S,, and SSy are defined similarly for code- word Y * E C*. The number of groups in the third subset
is I (say). Crossovers between these three subsets of Y * with that of X * are denoted as:
n1 = N S , , , SIX) = change in last bit from 1 to 0, that is n , may have
value 0 or 1
n2 = N S , , , S2J = m
where
W(S2,) - WS2A if WS, , ) ’ W,,) m = { 0 , otherwise
that is, n2 may have value 0, 1, 2, . . . , q.
n3 = N(S3,> S3A
= change in zero or more groups in the third subsets from (t + 1) 1s to ( t + 1) Os
that is, n3 may have value 0, ( t + I), 2(t + l), . . ., I(t + 1).
Proof: Let N,, = N [ ( Y , , Y, , ..., Ye), ( X I , X , , .
Here W ( X ) = i + k and W( Y ) = i.
I
first group
third subset (with gr6ups each having(t+l) bits)
counter
Fig. 1
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Simple circuit block diagram for generation o / X , s
35
Case (a) If k = 0 then X and Y are the same set which gives n1 = n2 = n3 = 0. so
N,, = n , + n2 + n3 = 0
Case (b) If 1 < k < 2t then X and Y are in different sets. So as per the Procedure find-code:
(i) for k odd,
and
n3 2 (t + 1) where
where n, = n, = 0 and i is odd where n, = 1, n3 = 0 and i is even
for k = 1 {:or 1, for
n2 = 0, i is odd or even and n, =
so
(ii) for k even,
n2 > k/2 where
n3 = 0, n, is 0 or 1 and i is odd or even
and
n3 2 ( t + 1)
n2 = 0, n, is 0 or 1 and i is odd or even
where
so
k N , , = n , + "2 + n3 >- 2
Case (c) If k 3 2 t + 1 then X and Y are also different according to the Procedure find-code:
k > l
sets. So
t + 1, where n, = n3 = 0, k is odd and i is odd t , t + 1, where n2 = 0, nt is 0 or 1, k is even
where n1 = 1, n3 = 0, k is odd and i is even
and i is odd or even
and
n3 2 (t + 1)
where
n2 = 0, n, is 0 or 1, i is odd or even and k is odd or even
so N,, = n1 + n2 + n3 3 t + 1
Theorem 5 : The code C* constructed using the pro- cedure find-code is a t-ECIAUED code.
Proof: As per Theorem 4, we only need to show that v x * , Y* E c* I x * # Y * :
N(X*, Y * ) 2 t + 1 36
Consider X E C , + , and Y E Ci. Three different cases need to be considered:
Case (a)
From eqns. 1 and 5, we obtain k = 0.
N(X*, Y * ) z N ( X , Y ) 2 t + 1
N(Y*, X * ) z N(Y, X ) 2 t + 1
and
Case (b) 1 < k < 2t.
from eqns. 2 and 6, we get (i) For k odd
N(X*, Y * ) z N ( X , Y ) 2 t + 1
and
N(Y*, X * ) = N ( Y , X )
+ NC(Y1, y2 1 ' ' . , Y,), ( X l , X2 9
at--+- k - 1 k + l 2 2
i.e.
N(Y*, X * ) 2 t + 1
(ii) For k even, from eqns. 3 and 7, we get
N(X*, Y * ) 3 N ( X , Y ) > t + 1
and
N(Y*, X * ) = N ( Y , X )
...
k k > t + l - - + -
2 2 i.e.
N(Y*, X * ) 3 t + 1
Case (c) k z 2 t + 1 . From eqns. 4 and 8 we get
N(X*, Y * ) > t + 1
and
N(Y*, X * ) = N ( Y , X )
+ N ( Y i , Y 2 , . . . , Y + ) , ( X 1 , X 2 , . . . , X , ) l > O + t + l
i.e.
N(Y*, X * ) > t + 1
The procedure 'find-code' ensures that encoding informa- tion bits in one of the t-ECIAUED codes is straightfor- ward and simple. The encoder consists of a t-error correcting parity check encoder and a circuit calculating the values of X , X , . . . X , .
The values of r*-bits depend only on the number of 1s in X , W ( X ) . The Berger code generator can be used to compute W ( X ) . The circuit for generation of r* check bits can be designed from a circuit that accepts W ( X ) as the input. It can be implemented in two ways.
(a) Using combinational circuit: The Procedure find-code can be realised with the circuit shown in Fig. 1
IEE Proc.-Comput. Digit. Tech., Vol. 142, No. 1. January 1995
to calculate values X, X, . . . X,. The input to the circuit is W(X). The size of the circuit depends on output of the procedure find-no-of-bits (i.e. r*) and number of symmetric errors that the code can correct. So the circuit consists of a number of modulo-2 counters, one modulo- (q + 1) counter, one q-bit shift register, and a few NOT gates. Output ‘count’ of modulo-2 counter is inverted to generate the bits of each group and the last bit. Output ‘count’ of modulo-(q + 1) counter shifts the shift register leftwards to generate the value of the last group. The ‘carry’ output of every counter is input to the next counter stage. The ‘carry’ of the last stage counter gener- ates the complemented value of the first group. The number of stages (i.e. number of counters) in the circuit shown in Fig. 1 is r(r* - (2t + l))/(t + 111 + 1. The delay of the encoding circuit depends on the number of stages.
An alternative faster implementation using a high speed array divider circuit is shown in Fig. 2. The LSB of W ( X )
4 Error detection/correction algorithm for the t-ECIAUED codes
Let Q = X X, X, X , ’ . . X, be an error free codeword in the proposed t-EC/AUED code; Q‘ = X’ Xi X; Xi
I x:
first subset (the last bit)
, r . . . , v first group second subset - (the ‘last group’)
third subset (with groups each having (t+l) bits)
Fig. 2 Faster circuii block diagramfor generation o / X , s
is inverted to generate the last bit. The remaining bits of W ( X ) are fed to the high speed divider circuit as divi- dend. While the value of (p + 1) is input as divisor. The ‘remainder’ output of the divider gives the number of shifts necessary to derive the second subset, i.e. ‘last group’. Every bit of the divider output ‘quotient’ is inverted to generate the bits of each group of the third subset. The size and delay of the circuit mainly depends on the size of the divider dictated by the value of t and k.
(b) Using ROM: Calculation of the values of X, X, . . . X, can also be implemented using a ROM (or a RAM) which accepts a value of W ( X ) as the address and the contents of this address are the values of r*-bits. Since W ( X ) < n, thus a ROM of n + 1 words is sufficient. So for a parity check code C with n = 127, a ROM of 128 words is enough. From Table 4 we can find that the number of extra check bits necessary is 20. Thus, we need a 128 x 20 bit ROM. Now, according to our code con- struction method, except the last group and last bit, all other groups have the property that in each group all bits have same value, i.e. 0 or 1. Therefore, instead of storing (t + 1) bits, we can store 1 bit for each of these groups in ROM. Hence, the word length of the ROM can be reduced significantly. Thus, instead of a 128 x 20 bit ROM, we need a 128 x 8 bit ROM. Table 11 shows the reduction achieved for ROM word size.
I E E Proc.-Comput. Digit. Tech., Vol. 142, No. I , January I995
’ . . X, be the received word with some errors in Q; and Q” = X” X ; X$ . . Xs be the derived codeword from Q’.
4.1 Error detectionlcorrection algorithm Step I Apply the decoding algorithm of parity check code C to X . If the algorithm fails to find a codeword X” in C at distance < t from X’, then more than t errors have occurred in X , i.e. in Q . Declare that unidirectional errors have occurred and stop. If the algorithm finds a codeword X” in C with D(X‘, X”) < t, then proceed with step 2.
Step 2 Compute the values of r*-bits which correspond to X”. so Q” = xrr x; x; . . . X;. If D(Q‘, Q”) < t, then the word Q“ is the correct codeword in C* and stop, else detectable error (i.e. unidirectional) with a multiplicity greater than t + 1 has occurred.
The decoding algorithm of the t-EC/AUED code has same order of complexity as that of the t-EC (n. k) code C. Example 2 illustrates the error detection and correc- tion steps.
Example 2: We consider the 1-EC/AUED code of Example 1, the parity check matrix H corresponding to
37
the generator matrix G is given by:
1 [ 0 1 1 1 0 0 1
1 1 0 1 1 0 0 H = 1 0 1 1 0 1 0
Consider the following codeword belonging to the above mentioned 1-EC/AUED code:
Q = 1OOO110 1100 +- x xi
(a) Suppose that one symmetric error has occurred in the above codeword in position marked with *, as shown below :
Q = li00llO 1100 +- x’ xi
Error correction/detection algorithm : By step 1 : we compute the syndrome S of X in the parity check code:
S = H X T = [lollT
The syndrome S is equal to the second column of the parity check matrix H. We conclude that a single error has occurred in the second position of X . The error is corrected and the resulting word is X” = 1OOO 110.
By step 2: we consider the value of X ; which corre- sponds to X”. Since W(X”) = 3, as per the Procedure find-code, X ; = 1100.
Then,
Q = 1o00110 1100 +-.- x” x;
Since D(Q’, Q”) = 1, the word Q” is the correct word Q. (b) Next, we consider the occurrence of a symmetric
error with multiplicity greater than one in the same word Q. Let the received word be
Q = lOiO6600 1100 -4J
x’ xi
By step 1 : we compute the syndrome S of X in the parity check code
S = H X T = [lollT
Since the syndrome is not equal to a column of H, an uncorrectable error is detected in X and hence in Q’.
Therefore, the error is detected in the received code- word.
(c) Finally, we consider the occurrence of an unidirec- tional error with multiplicity greater than one in the same word Q. Let the received word be
Q = l r n l h 77
By step 1 : we compute the syndrome S of X in the parity check code
S = H . X T = [11OIT
Since the syndrome S is equal to the first column of the parity check matrix H. We conclude that a single error has occurred in first position of X . The error is corrected and the resulting word is: x”=0000000
38
By step 2: We compute the value of X ; which corre- sponds to X . Since W ( X ) = 0, as per the Procedure find-code X y = 11 11.
Then
Q” = 0000000 1111 +- x x;
Since D(Q’, W ) = 4 > t = 1 we conclude that only a detectable error has occurred.
5 Experimental results and comparison with existing codes
The experimental results and comparative study with some of the existing codes are presented in Tables 4-1 1.
IEE Proc.-Comput. Digit. Tech., Vol. 142, No. I , January 1995
The symbols noted in the tables are as indicated in Section 1. Number of extra check bits necessary to t = 1, 2, 3 , 4 for a different range of k are shown in Tables 4-7.
Table 8: Commrison f o r t = 1 of Reference 7 with Table 4
The comparative results of the proposed scheme with the schemes noted in References 5 and 7 are tabulated in Tables 8-10 for different values of k and t. Results show that the information rate (kin*) of the proposed code is higher than for other codes and this vanes with t, the number of errors it can correct. In case of a ROM imple- mentation, reduction in word length varies with k and t as shown in Table 11. Also, compared with other schemes, our encoding/decoding algorithms can be implemented with a simpler, modular and cascadable structure that is ideally suited for VLSI technology.
Table 10: Comparison for t > 3 of References 7 and 5 with Tables 6, 7 etc.
k n t r* of r* of r* of ~~i~ in bits [7] [5] Table 5
I E E Proc.-Comput. Digit. Tech., Vol. 142, No . I , January 1995 39
6 Conclusion
A new scheme to construct t-ECIAUED systematic codes with faster speeds and less hardware has been proposed. This scheme needs a lower number of extra check bits than existing schemes [l, 5, 71. Compared with the scheme proposed in Reference 3, the number of check bits for this scheme is the same in lower information bits and a few bits higher in higher information bits. However, the encoding/decoding algorithms of Reference 3 are more complex than the proposed scheme. The com- parative results, reduction of number of check bits and ROM word length achieved by the proposed scheme are tabulated in Tables 4-11. The scheme can be imple- mented with simple hardware. Thus, the proposed code can be found to be much more efficient than others pro- posed so far in the literature.
7 References
1 KUNDU, S., and REDDY, S.M.: ‘On systematic error correcting and all unidirectional error detecting codes’, IEEE Trans. Cornpu< 1990.39, (6), pp. 752-761
40
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IEE Proc.-Cornput. Digit. Tech., Vol. 142, No. I , January I995
