IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38, NO. 7, JULY 1991 1641

New Physical Insights and Models for High-Voltage LDMOST IC CAD

Yeong-Seuk Kim, Student Member, IEEE, Jerry G . Fossum, Fellow, IEEE, and Richard K. Williams, Member, IEEE

Abstract-The lateral DMOST (LDMOST), including an LDD and the inherent BJT, is studied extensively using the two-di- mensional device simulator PISCES. The PISCES simulations provide new physical insights on the normal- and reverse-mode operations of the LDMOST, which are used for developing a comprehensive LDD LDMOST model for circuit simulation. In the modeling methodology, the LDD LDMOST is regionally partitioned into three main components (the channel, the drift region, and the BJT), and carrier-transport problems in each component are solved. The composite physical model is imple- mented in SPICE for HVIC CAD and is supported by mea- surements. The modeling methodology is also applicable to the RESURF LDMOST.

I. INTRODUCTION IGH-VOLTAGE integrated circuits (HVIC’s) in- H cluding lateral DMOST’s are now viable alternatives

to hybrid circuits comprising discrete high-voltage de- vices. Optimal design of these HVIC’s requires physical LDMOST models implemented in a circuit simulator like SPICE. Equivalent-(sub)circuit SPICE models for the high-voltage LDMOST [I ] have some utility, but are fun- damentally deficient; they cannot simulate unique power device characteristics such as quasi-saturation and re- verse-recovery transients [2].

Several physically based investigations of the on-resis- tance of LDMOST’s [3]-[5] have been done, but a com- plete physical model has not been reported. LDMOST’s in HVIC’s are subjected to unusual operating conditions, and hence robust models are needed. For example, an in- ductive load in power circuits will force the LDMOST into high-currentholtage regimes where reverse current flow through the device may occur. Claessen and van der Zee [6] presented a model for the LDMOST covering the high-current/voltage region. But their model is limited to dc conditions, and it does not account for quasi-saturation nor the inherent BJT, which is commonly activated in HVIC’s.

In this paper we develop a new physical charge-based LDMOST model which accounts for the BJT. We study

Manuscript received October 24, 1990; revised February 18, 1991. This work was supported in part by the National Science Foundation under Grant

Y. S . Kim was with the Department of Electrical Engineering, Univer- sity of Florida, Gainesville, FL 3261 1-2044. He is now with Motorola, Inc., Austin, TX 78762.

J . G . Fossum is with the Department of Electrical Engineering, Univer- sity of Florida, Gainesville. FL 3261 1-2044.

R. K . Williams is with Siliconix, Inc., Santa Clara, CA 95054. IEEE Log Number 9 10006 1 .

ECS-84 19427.

D Q s P G P

n + n- P

\

P- I Fig. 1. Unit-cell structure of the LDD LDMOST

the lightly doped-drain (LDD) n-channel LDMOST struc- ture (see Fig. l), using the two-dimensional device sim- ulator PISCES [7] for guidance. The PISCES simulations provide new insights on normal- and reverse-mode dc op- eration of the LDD LDMOST and on the significance of the inherent n-p-n BJT in transient reverse-recovery char- acteristics. For the model development, we regionally partition the device structure into three components: the channel, the LDD drift region, and the n-p-n BJT. The composite model, which requires some iterative numeri- cal solution of the carrier-transport equations, is imple- mented in SPICE for HVIC CAD. The modeling meth- odology is also applicable to the RESURF LDMOST structure [8], and with our physical VDMOST modeling in [2] defines LDMOST models for either technology.

11. NEW INSIGHTS BY NUMERICAL SIMULATIONS PISCES [7] simulations have been done to gain new

physical insights regarding the LDD LDMOST structure. These insights facilitate the device modeling for circuit simulation described in the next section. PISCES is a two- dimensional numerical semiconductor device simulator which can be used for dc steady-state and transient bias conditions. It solves the basic semiconductor device transport equations, using plausible physical models. For the LDD LDMOST, we used doping-density profiles and structural dimensions obtained from Siliconix, Inc. [ 13. The LDMOST’s were biased into both normal mode ( VDs > 0) and reverse mode (VDs < 0) in dc simulations; the

0018-938319 1/0700-1641$01 .OO 0 199 I IEEE

1642 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38, NO. I . JULY 1991

LDMOST's were switched from the reverse mode into the normal mode in transient reverse-recovery simulations.

The self-isolated n-channel LDD LDMOST is shown in Fig. 1. We assume the common case in which the source is shorted to the body. The channel region, which functions as a fast switch for the electron current flow, consists of two different regions: the double-diffused channel and the substrate channel. The double-diffused channel is nonuniformly doped by the difference of lateral diffusions between the p body and the n+ source. The substrate channel has constant doping density. PISCES simulations show that the electron drift velocity saturates near the source in the double-diffused channel, not near the drain as in conventional MOSFET's. We discussed this unusual behavior in [2].

The LDD (n--drift) region is used to block high volt- ages in the ow-state without breaking down, but it also affects the current-voltage characteristics in the owstate. owstate simulations [8] indicate that the current is con- fined near the surface of the LDD region due to the LDD- substrate junction electric field. As V,, is increased, the junction depletion region widens, and hence reduces the effective cross section of current flow (JFET action). At a critical VDs, for a specific VGs high enough to avoid sat- uration in the channel, the carriers (electrons) in the LDD attain their maximum (saturated) drift velocity near the n+ drain, and begin to accumulate to support incremental current. This electron accumulation, viz., quasi-satura- tion, counteracts the JFET action near the drain, and con- trols 1,s for high VDs (and high V&.

The lateral n-p-n BJT inherent in the LDD LDMOST (see Fig. 1) is activated when a (transient) reverse current flows through the LDMOST, as is forced by some power- switching circuits, e.g., switching power supplies [9]. The BJT causes a reverse-recovery delay and a troublesome abrupt current change, which we discuss later. There are two different modes of operation of the BJT (inverse and forward), depending on the bias conditions as discussed in [2]. To study the two modes, we have done PISCES simulations of the reverse-recovery characteristics. For the transient simulations, the drain-source terminals are driven through a load resistor by a negative-to-positive voltage pulse with a 50-11s rise time; VGs = 0 V (< V T ) .

PISCES-simulated reverse-recovery characteristics are shown in Fig. 2. To indicate the activation of the two BJT modes, we have separated out three current components: lD(r), Zs(r), and ZB(r ) are the currents flowing into the n+ drain, the n+ source, and the p body, respectively. For 0 < t < 45 ns, Zs(r) > 0, implying inverse-mode operation with the drain-substrate junction forward-biased. For 45 ns < r < 65 ns, Z,(r) < 0, implying forward-mode op- eration with the source-body junction forward-biased (near the channel). Initially at t = 0 s , with a negative voltage applied to the drain (source and body contacts are tied to ground), all the junction (p-p-, p--n-, and n-- n + ) potential barriers are lowered such that conductivity modulation (high injection) is prevalent in the p--sub- strate and f - d r i f t regions. A BJT action, with zero col-

0 . 0 0 0 1

80 - 8 5

6e - 0 5

4 e - 85 - 2 9 - 8 5

0 - 2 e - 8 5

- 4 e - 8 5

- 6 9 - 8 5

- 8 9 - 8 5 F ' " ' 0 . 8 8 5 0 . 0 0 1 0 0 . 0 8 1 5 0 . 0 0 2 0 0 . 0 0 2 5 0 . 0 8 308.81

" " " ' ' ' ' ' ' I " " I ' ' "

t i m e ( n s e c )

Fig. 2. PISCES-simulated reverse-recovery current transients of the LDD LDMOST. The drain-source voltage-drive pulse, applied through R, (= 54 kn . pm), changes from -5 to + 5 V with a 50-11s rise time. f D ( r ) , I s ( t ) , and I s ( t ) are the currents flowing into the n+ drain, the n t souce. the p body, respectively.

Fig. 3. PISCES-simulated current flowlines in the reverse-recovery tran- sient of Fig. 2 at (a) t = 0 s, showing the activation of the inverse-mode BJT ( A f = 7.4 X I O - 6 A/pm). and (b) t = 50 ns. showing the activation of the forward-mode BIT (A[ = 8. I x IO-' A/pm).

lector-base voltage, supports the current: I , = -(Is + Z,) = - ( P I + l )Zs. Fig. 3(a) shows PISCES-simulated current flowlines at t = 0 s. It reveals the inverse-mode BJT action. About 75% of the total current (ID) is collec- tor current (Is), i.e., electrons flowing out the n f source. The rest of the total current is base current (Is), i.e., holes flowing in from the body contact to support the high-in- jection recombination in the substrate/drift region. High gain ( P I ) of this inverse-mode transistor decreases the re- verse-recovery delay because there is less charge stored corresponding to a specific reverse current. Optimal de- sign of the device would hence require a high gain for the

KIM er a l . : NEW PHYSICAL INSIGHTS AND MODELS FOR LDMOST IC C A D

~

I643

inverse-mode BJT, but a low gain for, or suppression of the fonvard-mode BJT (using the deep p+-body diffu- sion), which we now discuss.

The direction of IB( t ) changes during the reverse recov- ery (at r = 7 ns in Fig. 2) due to the increased hole current ( d e , / d t , characterized in Section IV) discharging the quasi-neutral substrate (and body). This (dis)charging current flowing through the lateral body resistance R,,B produces a voltage drop, hence fonvard-biasing the source-body junction near the channel and inducing elec- tron injection into the p body and p- substrate. The for- ward-mode BJT is thereby activated. Fig. 3(b) shows PISCES-simulated current flowlines at t = 50 ns in the reverse recovery showing this BJT action. About 35% of the total current ( I D ) is due to the forward-mode BJT ( I s ) at this time. This BJT mode is undesirable for several rea- sons. First, it increases the reverse-recovery delay be- cause of added charge stored in the p--substrate region. Second, it induces an abrupt change in current I D ( t ) evi- dent in Fig. 2 because of the fast switching of Is(t) . This phenomenon, called “snap recovery” [9], can generate a very high voltage drop across stray inductance, which can induce dV/dt tum-on. Finally, the tum-on of the forward- mode BJT can result in significant saturation of the n-p-n BJT and possibly destructive breakdown of the LDMOST 191. Furthermore, the BJT effects can be exacerbated by impact ionization in the LDD region [8].

The RESURF LDMOST [8] is similar in structure to the LDD LDMOST with the exception of the drift-region design. The whole n- epilayer functions as a drift region, and its thickness and doping density are controlled to pro- duce low surface electric field to provide high breakdown voltage [lo]. PISCES simulations [8] reveal that the JFETIquasi-saturation tradeoff is similar to that in the LDD LDMOST. In addition to an inherent lateral n-p-n BJT, the RESURF LDMOST structure also has a vertical pin diode, which injects additional current and charge in the device. The reverse-recovery characteristic of the RE- SURF LDMOST is similar to that of the LDD LDMOST, but it exhibits a longer delay because of the additional charge stored in the vertical pin diode, i.e., in both the n--epi and p--substrate regions.

111. LDMOST MODEL Based on physical insights gained from the simulations

discussed in Section 11, we model the LDMOST by re- gionally partitioning it into three main components for analysis of the carrier transport: the channel, the drift re- gion, and the inherent BJT. We describe a physical com- posite model for the n-channel LDD LDMOST, which is implemented in SPICE and hence has utility for HVIC CAD. The modeling methodology is also applicable to the RESURF LDMOST.

A . LDMOST Channel The LDD LDMOST channel is modeled based on the

VDMOST channel model in [ 2 ] , but expanded to account

for the extended channel over the substrate, as illustrated in Fig. 1. We thus approximate the channel doping den- sity as

N A = NAo exp ( - - ) 7 x / L I ) , 0 5 x I L,

= NAs, L , 5 x I L , + L , (1)

where L, and L 2 are the double-diffused and substrate channel lengths. We use a piecewise-continuous electron velocity model

otherwise (2) - - Vsatr

where E, = ) d V / d t ) is the longitudinal electric field, usat (1 lo7 cm/s) is the electron saturated drift velocity, pneB = pno/[l + e(V,, - V T ) ] where p,Io is the low-field electron mobility, and 0 is the fitting parameter which de- fines the transverse-field dependence.

Following the methodology used in [2], we describe the strong-inversion channel current by integrating Z,, =

- WzuQ, from x = 0 to L , + L 2

(3)

where Vch is the total channel voltage drop, and

(4)

and 1 / 2

c,, = -- dQd (x = L , ) = [E] dV

are the “ody depletion “capacitances” for the doulx-dif- fused and substrate channels, respectively. In (4), VI is the double-diffused channel voltage drop, which is de- fined by equating the following two equations for channel current obtained from integrations along the respective channels:

W: P n e f f Q ~ ( L I ) - Qf,(o> Ich = -

+ (~neff/2usatLI>VII 2(Cox + CdI)

(7)

1644 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38. NO, 7, JULY 1991

and the threshold voltage V , is defined by the doping den- sity at the source as in [ 2 ]

P-

o*

: SectionA t n+

( - - - - - Fig. 4 . Magnified view of the LDD region showing the Gaussian volume

(thick solid l ines). . ( 1 1 )

drop VLDD The channel-current saturation is caused by electron velocity saturation near x = 0, which implies a simple expression for the saturated current as in [ 2 ]

Ich(sat) = - % usat wz YJ qpnd

ILDD = = 0)

= W : ~ s a t C o x ( ~ G S - V T ) . (12)

Equating ( 1 2 ) and ( 3 ) gives Vch(sat) for a given Vcs, above which the channel current is saturated.

B. LDD Region

The LDD drift region, in the general case, is further divided into two sections as illustrated in Fig. 4: section A , near the substrate channel, is the field-dependent-ve- locity region where the JFET action takes place; section B , near the n+ drain, is the (high-field) saturated-velocity

[(VLDD + v,,>”* - V Y ~ I ] (14)

which, for a given ILDD, is solved analytically for VLDD. Note from ( 1 3 ) that

(15) region. At low currents, the LDD region exhibits only ILDD(\at) = wz [ y, - qND uW

JFET action, viz., only section A . At high currents, sec- tion B materializes. Let us consider two regions of oper- ation defined by the LDD current ZLDD relative to ILDD(sat), which we define as the current at which the electron drift velocity saturates at the drain in the LDD region (x = Ld in Fig. 4), viz., the onset current for quasi-saturation.

I ) ILDD I ZLDD(,yar,: In this case, E, is not high enough to cause velocity saturation. Hence the carrier density does not exceed the doping density ND, and the LDD region (only section A exists) is described by conventional JFET theory. The drain current is expressed, using a continuous electron drift velocity-field function, as

where yd(Ld) is given by the depletion approximation and VLDD(sat), which follows from equating ( 1 5 ) to (14).

2) ZLDD > ILDD(sat,: In this current range, quasi-satura- tion obtains as the electron drift velocity saturates near the drain. The LDD region thus comprises the two sec- tions, A and B. In section A , electrons move by the field- dependent velocity, but in section B by the saturation ve- locity. At the boundary x = LA between these two sec- tions, the drain current is, from ( 1 3 ) , I L D D = %:[ y, - yd (LA)] qND usat where yd (LA) depends on the voltage VA at x = LA through the depletion approximation. This current expression yields

where y j is the metallurgical LDD junction depth, yd(x) is the extent of the junction depletion region into the LDD at x, pnd is the low-field electron mobility, and E, =

usat Ipnd. Integrating ( 1 3 ) over the LDD, we get the relationship

between the LDD current and the LDD-region voltage

where NAS is the substrate doping density used in ( 1 ) . With (16), the JFET analysis applied to section A defines the section-A length LA corresponding to ILDD.

In section B , we apply Gauss’s theorem to a volume enclosed by planes of unit width (see thick solid lines of

KIM et al. : NEW PHYSICAL INSIGHTS AND MODELS FOR LDMOST IC CAD

Fig. 4) ?J Yl

E s' E , d x + E i ( - E A ) d y + E io E , d y LA 0

= q 1, (No - n ) d y d x (17)

where the integral component along the top surface of the LDD is neglected due to the small transverse electric field there. To further simplify the analysis, we assume that the LDD-substrate junction electric field, EJ = 1 /2 [E, (x = LA) + E,(x = Ld)], is an average value independent of x. The depletion approximation is used to evaluate this av- erage. Also EA and Ex are assumed to be independent of position y . All of these assumptions concerning the elec- tric field are consistent with PISCES simulations.

Differentiating both sides of (17) with respect to x gives

This equation is integrated twice to give the section43 voltage drop

+ (Ld - LA)Ec* (19)

(20)

Now the complete LDD-region voltage drop is

VLDD = VA + VB where, for a given ILDD, V, and VB are characterized by (16) and (19). Because Ej in (19) depends on VLDD, the equations require numerical solution for this case, which is done via direct iteration within the model routine im- plemented in SPICE (see Section IV).

C. n-p-n BJT

We model the inherent n-p-n BJT of the LDD LDMOST based on physical insights from Section I1 and on our VDMOST BJT model in [2]. The one-dimensional n'-p- p--nf structure shown in Fig. 5 is representative of the basic device operation. As discussed in Section 11, the BJT can possibly operate in the forward mode, where the source-body (n'-p) junction is forward-biased (near the channel), or in the inverse mode, where the drain-sub- strate (n'-p- ) junction is forward-biased. As indicated in Fig. 3, few carriers (electrons) are injected through the LDD-substrate (n--p-) junction due to the voltage drop (debiasing) along the LDD region.

The integral charge-control relation (ICCR) can be ap- plied to the p-body base region to obtain the electron base transport current. Actually there is a composite base re- gion for the n-p-n BJT, comprising the p-body base and the p--substrate base. But we focus on the p-body base

Body

Fig. 5 . The one-dimensional n + - p - p - - n + BJT structure of the LDMOST.

1645

Drain --e

LDD

where .Ip = 0, which validates the ICCR. As indicated in Fig. 3(a) for the inverse mode, but also true for the for- ward mode, the predominant hole recombination current flows vertically through the body-substrate junction un- der the body contact, removed from the intrinsic p-body base. The ICCR in the quasi-neutral p-body base region, in low injection, thus gives

(21) qDn [n ( X E p ) p(xEp) - n (XEp) p ( X B p ) 1

XBP -.In =

NA(x) d x XEP

where for quasi-equilibrium in the junctions

and

n(xBp)p(xBp) = p ' ( X B p - )

= ~k exp (2vJpP- / v T ) . (23)

The junction voltages and boundaries in (21)-(23) are de- fined in Fig. 5 . High injection is assumed in the p- sub- strate ( p = n >> NAS) to derive ( 2 3 ) . Combining these equations yields the net p-base transport current

where superscripts F and I designate different parameters corresponding to the forward and inverse BJT modes. Note that the application of (24) to the forward mode is restricted to cases in which VBEn is induced by (equal to) an ohmic voltage drop along the p body (across RpB). In essence, (24) is a quasi-two-dimensional characteriza- tion, with the parameters being implied by the particular portions of the BJT structure which are actually activated in the respective modes of operation.

The BJT base (recombination) current in the forward mode is typically negligible relative to the hole charging

1646 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38. NO. I . JULY 1991

current ( d Q , / d t ) that triggers the forward-mode BJT in transient operation of the LDMOST. The current is thus not modeled. In the inverse mode, however, the recom- bination in the p- substrate defines a significant compo- nent of base current. To characterize this recombination, we solve the ambipolar transport equation in the sub- strate, where we assume high injection. The solution [ 1 I] is

n(x)

n(xBp-) sinh f-) + n(xcp-) sinh r 5 ) xCp- - xBp-

sinh ( LA ) where the boundary carrier densities are defined by the junction voltages

where we assume negligible recombination in the nf-drain region. Equations (26)-(29), for given VB, and VJpp-, are solved simultaneously (and analytically) to get n(x,,-) and n(xcp- ) [2]. Then the recombination current for inverse- mode operation is given by

where 7H is the (high-injection) carrier lifetime in the p- substrate.

The substrate-region voltage drop is significant for in- verse-mode BJT operation. It is evaluated by integrating the electric field in the substrate, characterized via the am- bipolar-transport analysis [12] in terms of the total cur- rent, and by adding VJp-n+, evaluated via (27)

xcp-

I/sub = iXBp E.r(x) d x + VJp-n+. (31)

Note here that the two bases (body and substrate) are linked by (24) and (28); ZcT is controlled by VJpp- and ZBI is a function of ZcT. Thus for specified junction voltages VBEn and VJpp-, the above formalism analytically describes the pertinent BJT characteristics, i.e., ZcT, le,, and Vsub.

IV. SPICE SIMULATIONS AND DISCUSSION The physical, semi-numerical composite model for the

LDD LDMOST described in Section 111 is intended for use in a SPICE-based circuit simulator. Fig. 6 shows the

Gate ?

BodylSource I

IBI

Fig. 6. Network representation of the L D D LDMOST model.

network representation of the model, based on integration of the regional analyses with l,h = ZLDD. This is not a simple equivalent circuit, but is a physical charge-based representation of the device structure. For demonstration of the model, all the elements in Fig. 6 have been imple- mented in SPICE via user-defined controlled sources (UDCS’s) which access the model routine that semi-nu- merically solves the implicit system of equations devel- oped in Section 111. UDCS’s are FORTRAN subroutines in SLICE [13], an enhanced version of SPICE2. (The model could ultimately be implemented directly in source code of any SPICE-based circuit simulator for HVIC CAD applications .)

The sources in the model network in Fig. 6 are voltage- controlled currentholtage sources defined in terms of node voltage differences VGs, r / ch , and VBEn. The voltage source Vdrift represents VLDD in normal-mode operation of the LDMOST and Vsub in reverse-mode operation. The tran- sient characteristics of the device are simulated by the charging-current UDCS’s

where i = p , J , and j = GS, ch, BEn. This charge dy- namics is based on the quasi-static approximation with the charges derived from the analysis in Section I11

XCP

Qp = qA’ sxBp- n(x) d x (33)

with n ( = p ) given by (25), is the hole charge stored in the p- substrate for inverse-mode operation of the inher- ent BJT

with VDs = V,, + VLDD, is the LDD-substrate junction depletion charge for normal-mode operation of the LDMOST. (The excess electron charge in the LDD due to velocity saturation is negligible as discussed in [2].) Also included in the model is CGS, the gate-source capac- itance, the most significant component of which is that due to the gate electrode overlapping the n+ source. The charging currents are calculated numerically using finite-

KIM ef U / . : NEW PHYSICAL INSIGHTS AND MODELS FOR LDMOST IC CAD I647

difference approximations for the voltage derivatives. These approximations are also used for the transcapaci- tances and transconductances needed for circuit nodal analysis.

In the nodal analysis, SPICE calls the UDCS's itera- tively, which in tum access the semi-numerical LDMOST model routine. The model algorithm 181, given VGs, Vch,

and VBEn, first determines the mode of operation by check- ing the sign of Vch. In the normal mode (Vch ? 0), low- and high-current (relative to ZLDD(s.atJ paths exist, both yielding the LDMOST solution with VD.7 = Vch -t VLDD. No BJT analysis is done in the normal mode. In the re- verse mode (Vc. < o), the BJT analysis is activated with VJpp- = -Vch and VBEII equal to the (transient) voltage drop across RPB, yielding the BJT solution with VDs = VJpp- + Vqub. No channel/LDD analysis is done in the reverse mode.

Test structures of LDD LDMOST's were fabricated using lateral-charge-control technology at Siliconix, Inc. [ I ] . Fig. 7 shows measured and simulated dc Zns-VDs characteristics for the LDD LDMOST. For the simula- tions, the model parameters related to the device structure and doping density were estimated from the technology; the other parameters were extracted to fit measured data without any optimization. The physical nature of the model facilitates experimental isolation of the parame- ters, which would enable effective extraction via local op- timizations. For example, LDD-related parameters were derived from measurements in the quasi-saturation mode (high VGs, VDs), and BJT-related parameters were derived from measurements in the reverse mode (V,, < 0).

As evidenced in Fig. 7, quasi-saturation, in which Ins is independent of VGs and the output conductance is ab- normally high for high VDs, is predicted in simulations for high VGs = 8, 10, 12 V, in agreement with the measure- ments. The abrupt current transition from the triode re- gion to the saturation region for the lower VGs simulations in Fig. 7 is due to the piecewise-continuous electron ve- locity model in (2).

In Fig. 8, we show measured and model-simulated re- verse-recovery current characteristics of the LDD LDMOST. When t < 100 ns, the device, in reverse-mode operation (VDs < 0 V) where the inverse-mode BJT is activated, stores a high concentration of holes and elec- trons predominantly in the p- substrate region. At t = 100 ns, a voltage pulse ( - 5 to +4 V with 100-ns rise time) is applied to the drain-source terminals through a resistor ( I 52 Q) to switch the device from the reverse-oN- state to the normal-om-state. Then the stored hole (and electron) density in the substrate begins to diminish (dQp/d t < 0) by carrier removal through the base (p- body) contact and by recombination. The time delay from initiation of switching until the device recovers to a spec- ified ows ta t e is defined as the reverse-recovery time. This recovery time is controlled by a) the rise time of the switching pulse; b) T~ and P I ; and c) R,,B. Fast switching, short T~ but high P I , and small RpR tend to cause quick

IDS-VDS

I " " " " " ' 1 0.10

0.08

- 4 0.06 Ln -

0.04

0.02

0.00 0.0 20.0 40.0 60.0 80.0 100.0 120.0

VDS [ V I

Fig. 7 . Measured (small rectangles) and SPICE-simulated (curves) cur- rent-voltage Characteristics of the LDD LDMOST (&, = 42 pm).

-50 OefOO 2e-07 4e-07 6e-07 8e-07 le-06

time [sec]

(b) Fig. 8 . Reverse-recovery current characteristics for the LDD LDMOST (15, = 42 p n ) : (a) measured ( I division on the x-axis = 100 ns and 1 division on the y-axis = 13.2 mA); (b) SPICE-simulated. The drain-source voltage-drive pulse, applied through R,. ( = 152 R ) , changes from -5 to f 4 V with a 100-ns rise time starting at / = 100 ns.

reverse recovery. In Fig. 8, the forward-mode BJT is not triggered because the induced ohmic voltage drop across RPB (i.e., VBEn) is not sufficient to adequately forward-bias the source-body junction. Note that the storage-time sim- ulation corresponds well with the measuremcnt. The mea- surement shows a long recovery tail unaccounted for in the simulation, which is not really crucial in CAD appli- cations. This tail could be due to probe-station parasitics,

LL R L P &2-+T t ;--i" LDMOSTZ .:;

Fig. 9. Test circuit for the LDD LDMOST transients. Rc = 50 52, L,. = 5 mH, R, = 250 52, and Vs = 20 V .

30

20

10 - U

- 0 v >

-10

-20

60

40

20

0

-20

- 40

-30 t ~ " " " " " " ' l ~ " " " " ' " ' ' l ~ " " ~ ' ' ' -60 Oe+00 le-07 2 - 0 7 3e-07 4e-07 5e-07 6e-07 7e-07 6 e e ~ .

time [sec]

Fig. 10. SPICE simulation results for the circuit in Fig. 9

or to charge dynamics in the LDMOST structure that we ignored.

Fig. 9 shows our test circuit for transient simulations. This circuit, which is a basic building block for a variety of DMOST applications, e.g., two-quadrant chopper cir- cuit, tests both normal- and reverse-mode operations, in- cluding transient reverse recovery. Fig. 10 shows results of transient simulations. Initially ( t = 0), VGs > V,; so LDMOSTl is OFF and LDMOST2 is ON. As VGs goes to zero ( t = 0.15 ps)), LDMOST2 is turned off and ZDs2 de- creases. Consequently, the current through LL, Z L , de- creases and induces a voltage drop across LL. Then the voltage at node P , V p , is greater than the supply voltage VB, and this voltage difference turns on the n-p-n BJT (the so-called integral diode) of LDMOST1. When VGs in- creases again ( t = 0.25 p s ) , LDMOST2 turns ON, with the n-p-n BJT of LDMOSTl undergoing reverse recov- ery. Hence IDS2 = IDS2(ON) + IRRl, which is larger than the normal-oN current due to ZRRl, the reverse-recovery current of LDMOSTl. During the recovery time, ZL (=IDs2 - rDsl) changes very little. The peak IDS2 occurs when VDS2 is also higher than normal. This condition can cause significant impact ionization in LDMOST2, leading possibly to second breakdown. ZRRl is higher when the rise time of VGs is shorter. In this case, the second breakdown

is more probable. We note that the predicted shape of the LDMOST 1 reverse-recovery characteristic in Fig. 10 de- pends strongly on the BJT model parameters as well as

The transient simulations shown in Figs. 8(b) and 10, which reveal effects of the inherent BJT in LDMOST cir- cuits, demonstrate a capability of mixed-mode device/cir- cuit simulation. This feature of our physical model, which is not afforded by other equivalent-(sub)circuit models, can be quite useful in computer-aided optimal device/cir- cuit design of HVIC's. Based on preliminary benchmark- ing, the added model complexity due to the BJT as well as the LDD accountings increases the device/circuit sim- ulation run-time by less than a factor of two over that for the simple equivalent-(sub)circuit SPICE model [ 13.

VGS( t ) .

V. SUMMARY

New physical insights regarding the LDD LDMOST structure have been obtained by using the two-dimen- sional device simulator PISCES. These insights were used to develop a physical, semi-numerical composite model for the LDD LDMOST, including the inherent BJT. The modeling methodology is also applicable to the RESURF LDMOST. The charge-based model was implemented in SPICE via UDCS's and supported by dc and transient measurements of test devices. Transient simulations for both normal- and reverse-mode operations were done to show the superiority of the physical model over empirical equivalent-(sub)circuit models for HVIC CAD.

The comprehensive model, although semi-numerical, could be implemented directly in source code of any SPICE-based circuit simulator. It is useful for computer- aided optimal design of LDMOST's as well as of HVIC's. Key model parameters are technological (i.e., defined by the device structure), and hence can be systematically ad- justed with proper correlations to achieve optimal device/ circuit performance. For example, to control the reverse- recovery time, deep p+ diffusion into the p body can be employed to reduce RpB, or electron irradiation can be used to reduce T ~ . To assess these technological variations, de- vice/circuit simulations can be done to directly predict their effects on performance without having to do any fab- rication, provided, of course, RpB and T~ can be physi- cally linked to the technology.

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