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New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate...

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New Tools and Methodology for MEMS Development June 2013 Steve Breit, PhD V.P. Engineering
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Page 1: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

New Tools and Methodology for MEMS Development

June 2013

Steve Breit, PhD V.P. Engineering

Page 2: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

© Coventor, Inc. Confidential

Company Overview

History: Founded in 1996 with focus on MEMS design automation

• Software tools and design methodology • Expertise in 3D modeling and simulation • Proven track record in the MEMS industry

with worldwide, top-tier customer base

Today: Expanded offering to the MEMS and semiconductor industries with a unique process modeling solution

• Critical for advanced technology nodes: 22 nm CMOS and beyond, DRAM, Flash,…

• Multiple use cases: process development and integration, design rules, DFM, metrology,...

• Speed and Capacity far surpass alternative solutions

Apple iPad and iPhone Nintendo Wii

MEMS Market

Intel 22nm trigate transistors

Array of 9 8T SRAM cells in SEMulator3D

FinFET variability analysis

Semiconductor Market

Slide 2

Page 3: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

New Tools & Methodology for MEMS Design

Overview • Motivation

• The Traditional Approach

• The New Approach

• Case Study: MEMS Varactor Manufacturability

• Conclusion & Discussion

© Coventor Inc. 2012 Slide 3

Bring MEMS to market still takes too long!

Reduce time-consuming “built-and-test” cycles

Page 4: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

MEMS development still takes too long!

Use simulation to shorten

development time to market

Page 5: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

Coventor Product Platform

© Coventor Inc. 2011 Slide 5

Process Development

Device Design

System-Level Optimization

CoventorWare®

SEMulator3D®

MEMS+® • Rapid concept

exploration • MEMS models for

system & IC design

• Multi-physics simulation

• Stress analysis • Damping effects • Packaging effects

• Virtual fabrication of MEMS & semi-conductor devices

• Silicon-accurate geometry

• Virtual metrology

• Sensitivity • Linearity • Frequency response • Signal-to-noise • Cross-axis sensitivity • Temperature stability • Switching time • Contact force • Efficiency (Q) • Power transmission • Process corners • Opens & shorts • Release etching • CVD, sputtering,… • RIE, wet etch,… • And more…

Simulate

Page 6: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

The Traditional Approach to MEMS Design

© Coventor Inc. 2013 Slide 6

ASIC Design

MEMS Design

Fab / Foundry

MEMS Process Learning Cycle

MEMS Process Learning Cycle

MEMS Process Learning Cycle

Control System Design Control System Design Control System Design

Conventional FEA

Conventional FEA Conventional FEA Conventional

Modeling Modeling Modeling Modeling

IC Design IC Design IC Design

Over-simplified, non-parametric

Too slow to inform fab cycles Full coupling infeasible

Hand-crafted

Design-specific

Consequence: too many “build and test” cycles

Page 7: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

MEMS+ The New Approach

© Coventor Inc. 2012 Slide 7

MEMS+ Simulator

MATLAB

Simulink

Virtuoso

Simulate and Analyze Enter Design in 3D Visualize Results in 3D

MEMS+ Finite Element Library: MEMS-specific, 3D, high-order, parametric

A tool for creating compact finite element models that run in MATLAB, Simulink, and Cadence

Page 8: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

MEMS+ a different kind of FEA

Traditional Finite Element Analysis

3D Geometry

Mesh Generator

Library of generic, low-order

finite elements

Brick, tet, shell, and beam elements

Meshed Model

Large 10k to 10M DoF

MEMS+ Finite Element Analysis

3D Design Entry in Graphical UI

Library of parametric, MEMS-specific, high-order finite elements

Scripting in MATLAB or Python

or

Meshed Model

Small 10 to 1000 DoF

Page 9: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

Overview of the MEMS+ Element Library

Rigid Shapes Flexible Shapes Beams Suspensions Start with Mechanical Components

In-Plane Electrodes

Side Electrodes

Interdigitated Combs

Piezo Layers Add Electro-

Mechanical Coupling

Squeezed-Film Damping

Fluid Chambers

Pressure Loads Add Fluid

Damping and Loading

Page 10: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

MEMS+ Application Examples

Slide 10

DLP mirror, 11 DoF

RF Switch 119 DoF

Gyroscope, 96 DoF Accelerometer, 67 DoF Ring Gyro, 345 DoF

Ring Resonator, 727 DoF

MEMS+ is general. MEMS+ models are small, but accurate and simulate fast for rapid design and manufacturability studies

Page 11: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

Why use MEMS+

MEMS present specific simulation challenges

© Coventor Inc. 2012 Slide 11

MEMS are multi-physics Mechanics + electrostatics + fluidic effects + packaging effects + etc.

MEMS are part of a system • MEMS + control system • MEMS + IC

MEMS+ can simulate fully coupled physics

• Dynamic response • Rapid design studies • Design optimization • Manfacturability

MEMS+ models work in system and IC tools

• Closed-loop operation • Noise analysis • Device arrays

Page 12: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

Case Study: MEMS Varactor Manufacturability

Page 13: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

Recent Successes, Designed with Coventor…

© Coventor Inc. 2012 Slide 13

“Thank you for developing MEMS tools that support our needs for composite piezo materials”

– Harmeet Bhugra, Managing Director, MEMS Product Line

The first piezo MEMS timing solution, announced in 2011

TDCA, the first RF MEMS varactor array to ship in cell phones, Samsung phone tear down, 2011

Page 14: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

MEMS Varactor Modeling Methodology

© Coventor Inc. 2011 Slide 14

Deformation vs. bias voltage

Quasi-static pull-in analysis in MEMS+ and CoventorWare

Simulated in MEMS+

2. Verification of MEMS+ model with conventional FEA Deformation due to process-induced stress gradient

Simulated in MEMS+ and CoventorWare

Disclaimer: Design shown is from an EU project, NOT from WiSpry or another customer

Design entered in MEMS+

1. Parametric design entered in MEMS+ intuitive UI

Page 15: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

Varactor Array Capacitance

© Coventor Inc. 2011 Slide 15

0 10 20 30 40

Tota

l Arr

ay

Capa

cita

nce

Bias Voltage

Array 1Array 2Array 3Array 4Array 5

Designed pull-in V

Supplied measured data (mock up of proprietary info) • Each array has 100s of varactors • Multiple arrays measured from different wafer locations

Huge variation in pull-in voltage is caused by process variations

Page 16: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

Process Variation Assumptions

Slide 16

Parameter Nominal Delta

Mech1 Mean Stress (Mpa) 60 ± 100%

Mech1 Delta Stress (Mpa) 80 ± 90%

Mech2 Stress (Mpa) -170 ± 35%

Mech1 Thickness (um) 0.2 ± 10%

Varactor Gap (um) 1.0 ± 5%

mech1

mech2

mean residual stress and stress gradient

gap thickness

Which process variations cause the large variation in pull-in voltage?

Process cross section

Page 17: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

Multi-variable sensitivity analysis

Coventor Inc. Confidential Slide 17

5-way virtual experiment on a parametric MEMS+ model, scripted in MATLAB

Page 18: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

Pull-In Sensitivity Simulated in MEMS+

Slide 18

Mech1 Mean Residual Stress (Mpa) Mech2 Residual Stress (Mpa) Gap (um)

Pull_

in (V

)

24

22

20

18

16

14

12 -10 20 50 80 110 -245 -215 -185 -155 -125 0.71 0.73 0.75 0.77 0.79

thickness mech1

mech2

mean residual stress

gap

Page 19: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

Total Variation Analysis

Slide 19

Use the variation envelope to predict yield Example: Tolerance of ±4V from nominal pull-in voltage gives 55% yield

Total Variation = Root Sum Squares ( input variations normalized by SD )

Page 20: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

Polysilicon thickness Young’s Modulus variation Y-mode Frequency Z-mode Frequency

MEMS+ models enable manufacturability studies

+ MATLAB script

10 minutes CPU time to compute 400 mode frequencies

MEMS+ model

Example: Modal frequencies vs. cross-wafer non-uniformity

Page 21: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

Import to Cadence for transient analysis & IC design

Slide 21 Exposed parameters of interest

Exposed pins of interest

Page 22: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

Virtual Fabrication with SEMulator3D

23

Detailed Process Description

Metal 1

Metal 2

Metal 3

Metal 4

Metal 5

Si3N4

Substrate

SiGe BiCMOS Process (HBTs, MOSFETs)

High-Voltage Electrodes for electrostatic actuation

RF-Signal Line

Met

alliz

atio

n of

BiC

MO

S

RFMEMS Switch is embedded in to metallization levels of BiCMOS process

Suspended Membrane (Metal3)

2D Design Data (GDS2 Layout)

Proven Value • Process Development • Design Verification

Silicon-Accurate 3D Models

2D Cross Sections

Page 23: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

Conclusion: MEMS+ is a New Approach

© Coventor Inc. 2013 Slide 24

ASIC Design

MEMS Design

Fab / Foundry

MEMS Process Learning Cycle

MEMS Process Learning Cycle

Control System Design

Conventional FEA

Modeling

IC Design

Complementary, for details and verifying MEMS+

Automatically generated, parametric, tunable accuracy vs. speed

Industrial strength, Fast AND Accurate, Full coupling feasible

Result: fewer “build and test” cycles

MEMS+, A Different Kind of FEA Rapid Design Studies Optimization Manufacturability

Page 24: New Tools and Methodology for MEMS Development · Nintendo Wii MEMS Market Intel 22nm trigate transistors Array of 9 8T SRAM cells in SEMulator3D FinFET variability analysis Semiconductor

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