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EC2307 COMMUNICATION SYSTEMS LABORATORY

R.M.SURYA ,AP/ECE JAYAM COLLEGE OF ENGINEERING AND TECHNOLOGY

SYLLABUS

EC2307 COMMUNICATION SYSTEMS LABORATORY L T P C 0 0 3 2

S.NO NAME OF THE EXPERIMENT

1. AMPLITUDE MODULATION AND DEMODULATION

2. FREQUENCY MODULATION AND DEMODULATION

3. PULSE MODULATION PAM / PWM / PPM

4. PULSE CODE MODULATION

5. DELTA MODULATION, ADAPTIVE DELTA MODULATION

6. DIGITAL MODULATION & DEMODULATION ASK, PSK, QPSK, FSK (HARDWARE &MATLAB)

7. DESIGNING, ASSEMBLING AND TESTING OF PRE-EMPHASIS / DE-EMPHASIS CIRCUITS

8. PLL AND FREQUENCY SYNTHESIZER

9. LINE CODING

10. ERROR CONTROL CODING USING MATLAB

11. SAMPLING & TIME DIVISION MULTIPLEXING

12. FREQUENCY DIVISION MULTIPLEXING

TOTAL= 45 PERIOD


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JAYAM COLLEGE OF ENGINEERING & TECHNOLOGY

DEPT OF ELECTRONICS AND COMMUNICATION ENGINEERING

B. E. - ELECTRONICS AND COMMUNICATION ENGINEERING (R 2008)EC2307 - COMMUNICATION SYSTEMS LABORATORY

REQUIREMENT FOR A BATCH OF 30 STUDENTS

HOD/ECE

S.No. Description of Equipment Quantityrequired

Quantityavailable

Deficiency%

1 CRO - 20 MHz 15 12 33%

2 Function Generator (1 MHz ) 15 15 -

3 Power Supply ( 0 - 30 Volts Variable ) ( IC Power

supply)

15 15 -

4 Bread Board 10 10 -

5 AM Transceiver Kit 2 1 -

6 FM Transceiver Kit 2 1 -

7 PAM,PPM,PWM Trainer Kits 2 2 -

8 PCM /DM/ ADM Trainer Kit 2 2 -

9 Line Coding & Decoding Kit 2 1 50%

10 ASK,PSK,FSK,QPSK Trainer Kits 2 2 -

11 Sampling & TDM trainer kit 2 1 50%

12 Mat lab (Communication tool box) 5 userlicense 5 -

Consumables

13 IC 565,566,567,741

Minimumof

50 No.each

50 -

14 BC 107 50 -

15 BFW10 50 -

16 OA79 50 -

17 Resistors ( Various ranges ) 50 -

18 Capacitors ( Various ranges ) 50 -

19 Decade Inductance box 50 -


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EC2307 - COMMUNICATION SYSTEMS LABORATORY

LIST OF EXPERIMENTS:

S.NO NAME OF THE EXPERIMENT1. AMPLITUDE MODULATION AND DEMODULATION

2. FREQUENCY MODULATION AND DEMODULATION

3. PULSE MODULATION PAM / PWM / PPM

4. PULSE CODE MODULATION

5. DELTA MODULATION, ADAPTIVE DELTA MODULATION

6. DIGITAL MODULATION & DEMODULATION ASK, PSK, QPSK, FSK (HARDWARE &

MATLAB)

7. DESIGNING, ASSEMBLING AND TESTING OF PRE-EMPHASIS / DE-EMPHASIS CIRCUITS

8. PLL AND FREQUENCY SYNTHESIZER

9. LINE CODING

10. ERROR CONTROL CODING USING MATLAB

11. SAMPLING & TIME DIVISION MULTIPLEXING

12. FREQUENCY DIVISION MULTIPLEXING

ADDITIONAL EXPERIMENTS1.

2.

DESIGN EXPERIMENTS1.

2.

OPEN ENDED EXPERIMENTS

1.

2.

3.


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EX NO: 1 AMPLITUDE MODULATION AND DEMODULATION

DATE:

AIM:

To generate amplitude modulated wave and to demodulate the modulated wave using

envelope detector.

APPARATUS REQUIRED:

THEORY:

Amplitude modulation:

Modulation is defined as the process by which some characteristics of a carrier signalis varied in accordance with a modulating signal. The base band signal is referred to as themodulating signal and the output of the modulation process is called as the modulation signal.Let us consider modulating signal, V m and carrier signal, Vc then the modulation index can

be calculated as:

a) when V m< V c ,modulation index , ma is said to be Under modulation b) when V m=V c, modulation index , ma is said to be Critical modulationc) when V m>V c, modulation index , ma is said to be Over modulation

Amplitude demodulation:

The process of detection provides a means of recovering the modulating signal fromcarrier signal. Demodulation is the reverse process of modulation.

S.No Name of the apparatus Quantity

1. Amplitude modulation transmitter kit (ACL-01) 1

2. Amplitude modulation receiver kit (ACL-02) 1

3. Cathode Ray Oscilloscope 1

4. Connecting probes 1

5. Patch chords As Required

6. Power Supply Dual mode


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Block Diagram:

Amplitude modulation & demodulation :

Kit diagram :

Procedure:

1. Refer to block diagram and Carry out the following connections.

2. Keep all the switch faults in OFF position.

3. Connect SINE OUT post of function generator section (ACL-01) to the I/p of Balance

Modulator1 (ACL-01) SIGNAL IN Post.

4. To connect o/p of VCO (ACL-01) RF OUT post to the input of Balance modulator 1

CARRIER IN post (ACL-01).

5. Connect the power supply with proper polarity to the kit ACL-01 & ACL-02, while connecting


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ensure that the power supply is OFF.

6. Keep switch SW1 towards 1-10 KHz position.

7. Keep Out post LEVEL about 0.5Vpp; FREQ. About 1 KHz.

8. Keep switch SW2 towards 500 KHz position.9. Keep RF out LEVEL about 1 Vpp; FREQ. about 450 KHz, Switch on 500 KHz.

10. Plot the graph as per output and input wave form.

Tabular Column:

INPUT SIGNAL: M= V MAX -VMIN

CARRIER SIGNAL: V Max+V MIN

S.No Given signal Type of the signal Amplitude in(volt)

Timeperiod in(ms)

1

MODULATEDSIGNAL

UNDER MODULATION

Vm1

FMAX =

FMIN =

FMAX =

FMIN =

FMAX =

FMIN =

2DEMODULATEDSIGNAL

FMAX =

FMIN =


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Waveform :

Result:

Thus the AM modulator and Demodulator circuit is constructed and tested. From the plottedwaveform of modulated signal on graph paper , modulation index values for specific readingsare:

1. when V mV c,modulation index , ma=..


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EX NO: 2 FREQUENCY MODULATION AND DEMODULATION

DATE:

AIM:

To generate Frequency modulated wave using varactor diode and to plot the demodulationcharacteristics of the fm demodulator using Foster-Seeley Demodulator.

APPARATUS REQUIRED:

THEORY:

Frequency modulation Generation:In practice, there are two main methods used to generate the FM:

Direct method:The most common device with variable reactance is the Varactor or Varicap, which is

a particular diode whose capacity varies as a function of the reverse bias voltage. Thefrequency of the carrier is established with AFC circuits (Automatic Frequency Control) orPLL (Phase Locked Loop).Indirect method:

In this case, FM is done by Phase Modulation, after the modulating signal has beenintegrated. In the phase modulator the carrier can be generated by a quartz oscillator and soits frequency stabilization is easier.Frequency demodulation:

Demodulation is the reverse process of modulation. For the detection of the frequencymodulated signals, different circuit solutions have been used :

1. Travis discrimination2. Foster-seeley discriminator3. Ratio discriminator4. Quadrature detector5. PLL detector6. Detuned resonance detector7. Amplitude limiter:


1. Frequency modulation transmitter kit (ACL-03) 1

2. Frequency modulation receiver kit (ACL-04) 1






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Block Diagram:

Frequency modulation & demodulation :

Kit diagram :

FUNCTIONGENERATOR

LIMITER FOSTER SEELEY

DETECTOR

LOCALOSCILLATOR

MIXER


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Procedure:

1. Refer to block diagram and Carry out the following connections.


3. Connect the o/p of function generator OUT post to the modulation IN post offrequency modulator.

4. Connect the oscilloscope to the output of the modulator FM/RF OUT.

5. To observe the FM at lower frequencies apply Sine wave of 1KHz and 1Vpp from

external function generator to MOD IN post of onboard Function Generator and keep

JP4 at 10-100KHz position and adjust the frequency at about 20-25KHz and output

level of Function generator at 2Vpp.

6. Connect the oscilloscope across post FS OUT. If the central frequency of the

discriminator and the carrier frequency of the FM signal and local oscillator frequency

coincide, you obtain demodulated signal of FOSTERSEELEY DETECTOR .

7. Connect the FS OUT to the IN post of LOW PASS FILTER. Note that the

demodulated signal has null continuous component.

Tabular Column:

INPUT SIGNAL:

MODULATING FREQUENCY:

S.no Given signal Frequency deviation(DF)(Fmax Fmin)/2

Modulationindexmf = DF/f

Amplitudein (volt)

Time period in(ms)

1

MODULATEDSIGNAL

FMAX

FMIN 2

DEMODULATEDSIGNAL

FMAX

FMIN


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Waveform :

Result:

Thus the FM modulator and Demodulator circuit is constructed and tested. From the plotted waveform of modulated signal on graph paper, modulation index values andFrequency deviation for specific readings are calculated.


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EX NO: 3a PULSE MODULATION PULSE AMPLITUDE MODULATION

DATE:

AIM:

To generate pulse amplitude modulated wave and demodulated wave.

APPARATUS REQUIRED:

THEORY:

Pulse amplitude modulation:

In Pulse Amplitude Modulation, the signal is sampled at regular intervals and theamplitude of each sample is made proportional to the amplitude of the signal at that instant ofsampling. This amplitude of each sample is hold for the sample duration to make pulses flattop.

The Pulse Amplitude Demodulator consists of Active Low Pass Butterworth filter. Itfilters out the sampling frequency and their harmonics from the modulated signal andrecovers the base band by integrated action. In pulse amplitude modulation (PAM), theamplitude of a carrier consisting of a periodic train of rectangular pulses is varied in

proportion with the sample values of a message signal. In this type of modulation, the pulseduration is held constant. By making the amplitude of each rectangular pulse the same as thatof the message signal at the leading edge of the pulse.

If the top of the samples vary as per the message signal variations, it is due to naturalsampling. Instead, if the top of the samples remain constant, then it is called as flat topsampling. Flat-top sampling introduces amplitude distortion and delay. This distortion iscalled aperture effect. This effect is reduced by employing equalizer. The equalizer has theeffect of decreasing the in-band loss of the reconstruction filter, as the frequency increases insuch a manner as to compensate for the aperture effect.


1. Pulse modulation transreceiver kit (DCL-08) 1




6. Power Supply Single mode


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Block Diagram:

Kit diagram :

Procedure:

1. Refer to Block Diagram & Carry out the following connections and Switch settings.

2. Connect the power supply with the proper polarity to the Kit DCL-08 and switch ON.


4. Select 16 KHz sampling frequency by jumper JP1.

5. Connect PAM OUT post to AMP IN post.

6. Connect AMP OUT post to FIL IN post.

7. Keep the amplifier gain control potentiometer P5 to maximum completely clockwise.

8. Observe the Amplified signal at AMP OUT Post.

9. Observe the Pulse Amplitude Demodulated signal at FIL OUT, which is same as the

input signal.

10. Repeat the experiment for different input signal and sampling frequencies.

FUNCTIONGENERATOR

SAMPLINGFREQUENCY

PAMMODULATOR

4 ORDERFILTER


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Tabular column:

S.NO Given Signal Amplitude(volts) Time period (ms)

1 Message Signal

2 Carrier Signal

3 Modulated Signal

4 Demodulated Signal

Waveform :

Result:

Thus pulse amplitude modulation and demodulation circuits were constructed and itsoutput waveforms were observed.


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EX NO: 3b PULSE MODULATION PULSE WIDTH MODULATION

DATE:

AIM:

To generate pulse width modulated wave and demodulated wave.

APPARATUS REQUIRED:

THEORY:

Pulse Width modulation:

This technique of modulation controls the variation of duty cycle of the square wave

the amplitude variation of the modulation signal is reflected in the ON period variation of

square wave. Hence, it is a technique of V to T conversion.

Pulse width demodulation:

The input signal is Pulse Width Modulated, so the ON time of the signal is changing

according to the modulating signal. In this demodulation technique during the ON time of

PWM signal one counter is enabled. At the end of ON time, counter gives a particular count,

which directly corresponds to the amplitude of input signal. Then this count is fed to a DAC.

The output of DAC corresponds to the amplitude of input signal. Thus train of varying pulse

widths gives varying count values and accordingly DAC give outputs, which is directly

proportional to amplitude of input signal. This is then filtered to get original signal. Thus at

the output we get the original modulating signal extracted from PWM wave.








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Block Diagram:

Kit diagram :

Procedure:


2. Connect the power supply with the proper polarity to the Kit DCL-08 and switch ON.3. Keep all the switch faults in OFF position.

4. Put jumper JP3 to 2nd position

5. Connect the 1 KHz sine wave signal generated onboard 1 KHz post to PAM IN Post.

6. Observe the Pulse Width Demodulated signal at FIL OUT, which is same as the input

signal.


FUNCTIONGENERATOR

CLOCK

PWMMODULATOR

4 ORDERFILTER


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Tabular column:


1 Message Signal

2 Carrier Signal

3 Modulated Signal


Waveform :

Result:

Thus pulse width modulation and demodulation circuits were constructed and its outputwaveforms were observed.


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EX NO: 3c PULSE MODULATION PULSE POSITION MODULATION

DATE:

AIM:

To generate pulse position modulated wave and demodulated wave.

APPARATUS REQUIRED:

THEORY:

Pulse position modulation:

The position of the TTL pulse is changed on time scale according to the variation of

input modulating signal amplitude, Width of the pulses and Amplitude of the pulses remain

same.

Pulse position demodulation:

This pulse position modulated signal is converted into PWM pulse form using

Monostable multivibrator. This signal is then demodulated using the same technique of PWM

demodulation. In this demodulation technique during the ON time of PWM signal one

counter is enabled. At the end of ON time, counter gives a particular count, which directlycorresponds to the amplitude of input signal. Then this count is fed to a DAC.

The output of DAC corresponds to the amplitude of input signal. Thus train of

varying pulse widths gives varying count values and accordingly DAC gives outputs, which

is directly proportional to amplitude of input signal. This is then filtered to get original signal.

Thus at the output we get the original modulating signal extracted from PWM wave.








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Block Diagram:

Kit diagram :

Procedure:


2. Connect the power supply with the proper polarity to the Kit DCL-08 and switch ON.

3.

Keep all the switch faults in OFF position.4. Put jumper JP3 to 2nd position

5. Connect the 1 KHz sine wave signal generated onboard 1 KHz post to PAM IN Post.

6. Observe the Pulse Width Demodulated signal at FIL OUT, which is same as the input

signal.


FUNCTIONGENERATOR

CLOCK

PPM MODULATOR 4 ORDERFILTER


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Tabular column:


1 Message Signal

2 Carrier Signal

3 Modulated Signal


Waveform :

Result:

Thus pulse position modulation and demodulation circuits were constructed and itsoutput waveforms were observed.


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EX NO: 4 PULSE CODE MODULATION

DATE:

AIM:

To generate pulse code modulated wave and demodulated wave.

APPARATUS REQUIRED:

THEORY:

Pulse code modulation and demodulation:

The sine waves (analog signal) of frequency 500Hz and 1 KHz and DC Signal DC1

and DC2 whose amplitude can be varied accordingly are generated onboard on DCL-03.

These signals are fed to the input of the Sampling logic CH0 & CH1 and their samples are

multiplexed by interleaving them properly in their assigned time slots.

The Crystal oscillator generates a clock of 6.4MHz from which all the transmitter data

and timing signals are derived. For fast mode operation the transmitter clock is 240KHz, and

Sampling clock is 16KHz.For slow mode operation depending on jumper position the

transmitter clock is 1.23Hz or 0.6Hz and sampling clock is 0.088Hz or 0.044Hz i.e. the

sampling rate per channel is 11 or 22 seconds and serial data transmission rate is 813

milliseconds or 1.6 seconds.

The multiplexed data is Pulse Code Modulated before transmission. At the receiver

after the Pulse Code Demodulation, the recovered data multiplexed data is sent to

Demultiplexing logic. The two demultiplexed samples are fed to Reconstruction unit which


1. Pulse code modulation transmitter kit (DCL-03) 1

2. Pulse code modulation receiver kit (DCL-04) 1






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consists of 4 th order Low Pass Butterworth Filter, where frequency components are filtered

out to recover the original base band signal at the receiver output CH0 and CH1.

Block Diagram:

Pulse code modulation:

Pulse code demodulation:

Kit diagram :


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Procedure:

1. Refer the Block Diagram & Carry out the following connections.

2. Connect power supply in polarity to the kits DCL-03 and DCL-04 and switch ON.

3. Connect sine wave frequency 500Hz and 1 KHz to the input CH0 and CH1 of thesample and hold logic.

4. Connect OUT 0 to CH0 IN & OUT 1 to CH1 IN.

5. Set the speed selection switch SW1 to FAST mode.

6. Select parity selection switch to NONE mode on both the kit DCL-03 and DCL-04 as

shown in switch setting diagram.

7. Connect TXDATA, TXCLK and TXSYNC of the transmitter section DCL-03 to the

corresponding RXDATA, RXCLK, and RXSYNC of the receiver section DCL-04.8. Connect posts DAC OUT to IN post of demultiplexed section on DCL-04.

9. Repeat the above experiment with DC Signal at the inputs of the Channel CH0 and

CH1.

10. Connect ground points of both the kits with the help of connecting chord provided

during all the experiments.

Tabular column:


1 Message Signal

2 Carrier Signal

3 Modulated Signal



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Waveform :

Result:

Thus pulse code modulation and demodulation circuits were constructed and its output

waveforms were observed.


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EX NO: 5a DELTA MODULATION

DATE:

AIM:

To generate Delta modulated wave and demodulated wave.

APPARATUS REQUIRED:

THEORY:

Delta modulation:

Delta modulation is the differential pulse code modulation scheme in which the

difference signal is encoded into just a single bit. In digital modulation system, the analog

signal is sampled and digitally coded. This code represents the sampled amplitude of the

analog signal. The digital signal is sent to the receiver through any channel in serial form. At

the receiver the digital signal is decoded and filtered to get reconstructed analog signal.

Sufficient number of samples are required to allow the analog signal to be reconstructed

accurately. Delta modulation is a process of converting analog signal into one bit code, means

only one bit is sent per sample. This bit indicates whether the signal is larger or smaller thanthe previous samples.

Delta demodulator:

The Delta Demodulator consists of a D-flip/flop, followed by an integrator and a 2nd

and 4th order low pass Butterworth filter. The Delta Demodulator receives the data stream

from D-flip/flop of Delta Modulator. It latches this data at every rising edge of receiver clock.

This data stream is then fed to integrator; its output tries to follow the analog signal in ramp

fashion and hence is a good approximation of the signal itself.


1. Delta modulation transreceiver kit (DCL-07) 1






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Block Diagram:

Kit diagram :

Procedure:

1. Refer to Block Diagram & Carry out the following connections and Switch settings.2. Connect the power supply with the proper polarity to the Kit DCL-07 and switch ON.

3.

Keep all the switch faults in OFF position.4. Connect output of buffer post OUT to Digital Sampler input post IN1 .5. Then select clock rate of 8 KHz by pressing switch S1 selected clock is indicated by

LED glow.6. Keep Switch S2 in Delta position.7. Connect output of Digital Sampler post OUT to input post IN of Integrator 1.8. Observe the Delta modulated output at output of Digital Sampler post OUT and

compare it with the clock rate selected. It is half the frequency of clock rate selected9. Connect output of Demodulator post OUT to the input of Integrator 3 post IN10. Keep Switch S4 in high position.11. Connect output of Integrator 3 post OUT to the input of output buffer post IN .

FUNCTIONGENERATOR

DIGITALSAMPLER

INTEGRATOR

1AND 3

4 ORDERFILTER

FF


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Tabular column:


1 Message Signal

2 Carrier Signal

3 Modulated Signal


Waveform :

Result:

Thus Delta modulation and demodulation were constructed and its output waveforms

were observed.


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EX NO: 5b ADAPTIVE DELTA MODULATION

DATE:

AIM:

To generate Adaptive delta modulated wave and demodulated wave.

APPARATUS REQUIRED:

THEORY:

Adaptive delta modulation:

Delta Modulation system is unable to chase the rapidly changing information of the

analog signal, which gives rise to distortion and poor quality reception. The problem can be

overcome by increasing the integrator gain. Adaptive Delta Modulation is a variation of Delta

Modulation, which offers relief from disadvantage of DM by adopting the step size to

accommodate changing signal conditions. If the input signal is large, step is cause to increase,

thereby reducing slope overload effects. A Delta Modulator consists of a comparator in the

forward path and an integrator in the feedback path of a simple control loop.The usual implementation involves a continuously variable slope Delta (CVSD).

There are varieties of IC's for CVSD encoding and decoding in today's semiconductor

market. CVSD produces equal quality at 32Kbit/sec. In CVSD Decoder CVSD mod output is

fed to the input of comparator. Adaptive Delta Modulation do not change step size on a

pulse-to pulse basis, but changes are made much more slowly, such slow control is referred to

as syllabic.


1. Delta modulation transreceiver kit (DCL-07) 1






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Block Diagram:

Kit diagram :

1. Procedure:2. Refer to Block Diagram & Carry out the following connections and Switch settings.3. Connect the power supply with the proper polarity to the Kit DCL-07 and switch ON.4. Keep all the switch faults in OFF position.5. Connect output of buffer post OUT to Digital Sampler input post IN1 .6. Then select clock rate of 8 KHz by pressing switch S1 selected clock is indicated by

LED glow.7. Keep Switch S3 in Low position.8. Connect output of Digital Sampler post OUT to input post IN of Integrator 2.9. Connect output of Demodulator post OUT to the input of Integrator 3 post IN.10. Keep Switch S4 in LOW position.11. Connect output of Integrator 3 post OUT to the input of output buffer post IN.12. Connect output of output buffer post OUT to the input of 2nd order filter post IN.

13. Connect output of 2nd order filter post OUT to the input of 4th order filter post IN14. Observe output at digital sampler output post

FUNCTIONGENERATOR

DIGITALSAMPLER

INTEGRATOR

1AND 3

4 ORDERFILTER

FF


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Tabular column:


1 Message Signal

2 Carrier Signal

3 Modulated Signal


Waveform :

Result:

Thus Adaptive delta modulations were constructed and its output waveforms were

observed.


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Block Diagram:

Kit diagram :

Procedure:

1. Refer the block diagram and carryout the following connections and switch settings.2. Connect power supply in proper polarity to the kits DCL-05 and DCL-06 and switch

it ON.3. Connect clock and data generated ON DCL-05 to coding clock in and DATA INPUT

respectively by means of connecting chords provided.4. Connect NRZ-L data input to control input of carrier modulated logic.5. ASK=>connect carrier component SIN2 to INPUT1 and GROUND TO INPUT2 of

the carrier modulator logic.6. Connect ASK modulated signal modulator output on DCL-05 to ASK of the ASK

demodulator on DCL-05.


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Tabular column:


1 Message Signal

2 Carrier Signal

3 Modulated Signal


Waveform :

Result:

Thus the techniques of ASK modulation and demodulation is performed and the graphis plotted.


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EX NO: 6b DIGITAL MODULATION & DEMODULATION FSK

DATE:

AIM:

To generate Carrier Modulation Techniques by Frequency Shift Keying.

APPARATUS REQUIRED:

THEORY:

Frequency shift keying:

Carrier modulation is a technique by which digital data is made to modulate a

continuous wave (sine wave) carrier. For all types of carrier modulation, the carrier frequency

should be at least 2 times that of modulating frequency. In Frequency Shift keying

modulation techniques, the modulated output shifts between two frequencies for all `one'

(mark) to `zero' (space) transitions. The carrier frequency chosen for FSK modulation are 500

KHz and 1MHz. Note that the above frequencies are greater than twice the modulating

frequency.

Note that the FSK may be thought of as an FM system in which the carrier frequency

is midway between the mark and space frequencies, and modulation is by a square wave.

CARRIER GENERATOR block on DCL-05 generates the carrier waves 500 KHz and 1

MHz, which are available at SIN1 and SIN2 post. The FSK modulator is also built around the

2 to 1 Analog Multiplexer, which switches between the 500KHz and 1MHz signals for all

'one' to `zero' transitions .


1. Data conditioning and carrier modulation kit(DCL-05) 1

2. Data conditioning and carrier demodulation kit

(DCL-06)

1






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Block Diagram:

Kit diagram :

Procedure:

1. Refer the block diagram and carryout the following connections and switch settings.2. Connect power supply in proper polarity to the kits DCL-05 and DCL-06 and switch


respectively by means of connecting chords provided.4. Connect NRZ-L data input to control input of carrier modulated logic.5. ASK=>connect carrier component SIN2 to INPUT1 and GROUND TO INPUT2 of

the carrier modulator logic.6. Connect FSK modulated signal modulator output on DCL-05 to FSK of the FSK



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Tabular column:


1 Message Signal

2 Carrier Signal

3 Modulated Signal


Waveform :

Result:

Thus the techniques of FSK modulation and demodulation is performed and the graph

is plotted.


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EX NO: 6c DIGITAL MODULATION & DEMODULATION PSK

DATE:

AIM:

To generate Carrier Modulation Techniques by Phase Shift Keying.

APPARATUS REQUIRED:

THEORY:

Phase shift keying:

Phase-shift keying (PSK) is a digital modulation scheme that conveys data by

changing, or modulating, the phase of a reference signal (the carrier wave).

Any digital modulation scheme uses a finite number of distinct signals to represent

digital data. PSK uses a finite number of phases, each assigned a unique pattern of binary bits. Usually, each phase encodes an equal number of bits. Each pattern of bits forms the

symbol that is represented by the particular phase. The demodulator, which is designed

specifically for the symbol-set used by the modulator, determines the phase of the received

signal and maps it back to the symbol it represents, thus recovering the original data. This

requires the receiver to be able to compare the phase of the received signal to a reference

signal such a system is termed coherent (and referred to as CPSK).


1. Data conditioning and carrier modulation kit(DCL-05) 1


(DCL-06)

1






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Block Diagram:

Kit diagram :

Procedure:1. Refer the block diagram and carryout the following connections and switch settings.2. Connect power supply in proper polarity to the kits DCL-05 and DCL-06 and switch


respectively by means of connecting chords provided.4. Connect NRZ-L data input to control input of carrier modulated logic.5. PSK=>connect carrier component SIN2 to INPUT1 and GROUND TO INPUT2 of

the carrier modulator logic.6. Connect PSK modulated signal modulator output on DCL-05 to PSK of the PSK



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Tabular column:


1 Message Signal

2 Carrier Signal

3 Modulated Signal


Waveform :

Result:

Thus the technique of PSK modulation and demodulation is performed and the graphis plotted.


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EX NO: 6d DIGITAL MODULATION & DEMODULATION QPSK

DATE:

AIM:

To generate Carrier Modulation Techniques by Quadrature phase Shift Keying.

APPARATUS REQUIRED:

THEORY:

Quadrature Phase shift keying:

QPSK is another form of angle-modulated, constant-amplitude digital modulation. Itis an M-ary encoding technique where M=4. with QPSK four output phases are possible for asingle carrier frequency. Two bits (a dibit) are clocked into the bit splitter. After both bitshave been serially inputted, they are simultaneously parallel outputted. One bit is directed tothe I channel and the other to the Q channel. The I bit modulates a carrier that is in phase withthe reference oscillator and the Q bit modulates a carrier that is 900 out of phase with thereference carrier.

QPSK modulator is two BPSK modulators combined in parallel.The input QPSKsignal is given to the I and Q product detectors and the carrier recovery circuit. The carrierrecovery circuit produces the original transmit carrier oscillator signal. The recovered carriermust be frequency and phase coherent with the transmit reference carrier. The QPSK signal isdemodulated in the I and Q product detectors, which generate the original I and Q data bits.The output of the product detectors are fed to the bit combining circuit, where they areconverted from parallel I and Q data channels to a single binary output data stream.


1. Data conditioning and carrier modulation kit(ADCL-02)

1


(ADCL-03)

1






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Block Diagram:

Kit diagram :

Procedure:

1. Refer to the block diagram & carry out the following connections and switch settings

2. Connect power supply in proper polarity to the kit.

3. Select data pattern of simulated data using switch SW1

4. Connect SDATA generated in DATA IN to NRZ-L CODER.

5. Connect the coded data NRZ-L DATA to the DATA IN of the DIBIT ONVERSION

6. Connect SCLOCK to CLK IN of DIBIT CONVERSION


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7. Connect the dibit data I bit to control input C1 of CARRIER MODULATION

8. Connect the dibit data Q bit to control input C2 of CARRIER MODULATION

9. Connect the carrier component to input of CARRIER MODULATOR as follows

a. SIN1 to IN1

b. SIN2 to IN2

c. SIN3 to IN3

d. SIN4 to IN4

10. Connect the QPSK MOD OUT to MOD IN of the QPSK DEMODULATOR

11. Observe the output of the first squarer at the SQUARER1

12. Observe the output of the second squarer at SQUARER2

13. Observe the four sampling clocks at the output of the SAMPLING CLOCK

GENERATOR

14. Observe the output of ADDER1

15. Observe the output of ADDER2

16. Observe the recovered data bit I at the output of the ENVELOPE DETECTOR 1

17. Observe the recovered data bit Q at the output of the ENVELOPE DETECTOR 2

18. Connect I BIT, Q BIT & CLK OUT of QPSK demodulator to I BIT IN & Q BIT IN &

CLK IN posts of data decoder respectively.

19. Observe the recovered NRZ-L data from I and Q bits at the output of the DATA

DECODER

20. Use RESET switch if delay occurs at data out post and use PHASE SYNC switch if

there is mismatch in the patterns of data at output with respect to the transmitter data.

Tabular column:


1 Message Signal

2 Carrier Signal

3 Modulated Signal



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Waveform :

Result:

Thus the techniques of QPSK modulation and demodulation are performed and thegraph is plotted.


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A pre-emphasis network in the transmitter accentuates the audio frequencies above 3

KHz, so providing the higher average deviation across the voice spectrum, thus Improving

the signal to noise ratio.

Circuit diagram:

Using active component :

Using passive components :


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Procedure:

1. Connections are made as per the circuit diagram.

2. Set input signal amplitude using function generator.

3. Vary the input signal frequency from 0Hz to 100kHz in regular steps.

4. Note down the corresponding output voltage.

5. Plot the graph: Gain(dB) vs Frequency(Hz).

Tabular column:

V i =

S.NOGiven Signal Frequency(Hz)

Output

Voltage(v o)

Gain (dB)=20

log (V 0/V i)

1 Message Signal

2 Carrier Signal

Model Graph:

Result:

Thus pre-emphasis circuit using active and passive components is constructed andverified.


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EX NO: 7b DESIGNING, ASSEMBLING AND TESTING OF DE-EMPHASIS CIRCUIT

DATE:

AIM:

To construct and verify De-emphasis network using active & passive components and

plot the waveform.

APPARATUS REQUIRED:

THEORY:

De-emphasis :

The problem in FM broadcasting is that noise and hiss tend to be more noticeable,

especially when receiving the weaker stations. To reduce this effect, the treble response of the

audio signal is artificially boosted prior to transmission. This is known as pre-emphasis. At

the receiver side a corresponding filter or de -emphasis circuit is required to reduce the

treble response to correct level. Since most noise and hiss tend to be at the higher frequencies,

the de-emphasis removes a lot of this. Pre-emphasis and de-emphasis thus allow an improved

signal to noise ratio to be achieved while maintaining the frequency response of the original

audio signal. The de-emphasis stage is used after the detector stage.

S.No Name of the Component Range Quantity

1. IC IC741 1

2. Resistors 100K,2.2K,15K,820 Each 1

3. Capacitor 0.1F,1F,0.001F Each 1

4. Function generator (0-1)MHz 1

5. CRO (0-20)MHz 1

6. DPS (15-0-15)V 1


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EX NO: 8a PHASE LOCKED LOOP

DATE:

AIM:

To study IC 565 PLL and find the following parameters:1. Lock Range2. Capture Range

APPARATUS REQUIRED:

THEORY:

Phase Locked Loop:

A phase-locked loop is a feedback system combining a voltage controlled oscillatorand a phase comparator so connected that the oscillator frequency (or phase) accurately

tracks that of an applied frequency- or phase-modulated signal. Phase-locked loops can beused, for example, to generate stable output frequency signals from a fixed low-frequencysignal. However, they only found broad acceptance in the marketplace when integrated PLLs

became available as relatively low-cost components in the mid-1960s. The phase locked loopcan be analyzed in general as a negative feedback system with a forward gain term and afeedback term. The loop filter is a low-pass type, typically with one pole and one zero. Thetransient response of the loop depends on: 1. The magnitude of the pole/zero,

2. The charge pump magnitude,

3. The VCO sensitivity,

4. The feedback factor, N.

S.No Name of the apparatus Range Quantity

1. IC NE565 Each 1

2.Capacitors

10F, 0.001F

0.01F

Each 1

Each 2

3. Resistor 12K Each 1

4. Function generator (0-1)MHz Each 1

5. CRO (0-20)MHz Each 1

6. DPS (15-0-15)V Each 1


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Block Diagram:

Circuit diagram :

Procedure:

1. Connect the circuit as per the circuit diagram.

2. Measure the free running frequency of IC565 at pin 4 using CRO with the input

signal (say 0V) from the signal generator or shorting pin 2 to ground.

3. Set the input signal say 1V, 1 kHz to pin 2 using signal generator and observe the

waveform on the CRO.


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1

2

3

4

5

6

Waveform :

Result:

Thus the PLL is studied and the Lock range, capture range and free running frequencyhave been calculated.


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Date post:	04-Jun-2018
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