Manas Bajaj1, Russell Peak1, Dirk Zwemer2, Thomas Thurman3, Michael Dickerson4, Kevin Brady5, John Messina5

1. Georgia Institute of Technology2. AkroMetrix, LLC3. Rockwell Collins, Inc.4. InterCAX, LLC5. National Institute of Standards and Technology

Next Generation Simulation-based Design Technologies for Electronics Product Realization

AkroMetrix

PDE 2005The 7th NASA-ESA Workshop on Product Data Exchange (PDE)

April 19-22, 2005 Manufacturing Research Center, Georgia Tech, Atlanta

2© Copyright 2005

AbstractNext Generation Simulation-based Design Technologies for Electronics Product Realization

The realm of electronics product realization is marked by an extremely fast-paced market, stringent demands for product reliability and high importance to innovative design. Further, the time-to-market and the cost-to-realize play a critical role for product success. However, these attributes pose conflicting constraints on the realization process. While engineers need to converge quickly on a set of design alternatives, the high demand for reliability increases the breadth of behavioral simulations across the design space. Further, the multi-disciplinary nature poses integration challenges due to a disparate set of engineering tools, model representations, and simulation techniques.

In this presentation, we shall focus on the following three technical areas to alleviate these hurdles in knowledge management during electronics product realization:

(1) Design-Analysis Integration: In order to quickly converge on a set of feasible design alternatives while covering a wide range of behavioral simulations across the design space, it is essential for engineers to synthesize analysis and solution-specific product models for a given design alternative. This process is guided by ascertaining the context of analysis, identifying possible idealizations and mapping information from design specifications to the analysis specifications. Further, the modularity of this process is essential to explore all possible alternatives.

We leverage from over a decade’s worth of experience spanning methodologies and tools (www.eislab.gatech.edu/research/dai/) and some recent advances in this area to demonstrate current and envisioned technologies for seamless design-analysis integration.

(2) Standards-based Knowledge Representation: In order to create high-fidelity design, analysis and manufacturable product models, it is essential to use a detailed and standard ontology for electronics product data specification. In this light, we employ STEP AP 210 (www.ap210.org) for electronic assembly packaging and design as the underlying representational structure for creating and archiving product models. Further, we use a harmonized set of STEP-based schemas for product model specifications across the design-analysis integration bridge. In this presentation, we shall focus on the ability of a standards-based knowledge representation scheme to support product and process related knowledge for electronics PLM.

(3) Experimental Validation of Simulation Techniques: In general, a simulation-based methodology needs to be validated against experimental results to justify reuse and instill confidence in decisions based on simulation results. In this presentation, we shall also demonstrate on algorithmic techniques for validating simulation results with experimental data and discuss some critical issues concerning the same.

Further, in this presentation, we will exemplify recent developments in the three technical areas using thermo-mechanical warpage analysis problem for printed circuit boards and assemblies, as part of the current collaborative effort between co-author organizations.

http://eislab.gatech.edu/pubs/seminars-etc/2005-cpda-dsfw-peak/

This document may identify commercial product names and materials to describe certain procedures or to provide concrete examples (i.e., to help clarify abstract concepts via specific instances). In no case does product or material identification imply recommendation or endorsement by the authors or their organizations, nor does it imply that such items are necessarily the best available for the purpose. Company, product, or service names may be included that are trademarks or service marks of others.

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Contents Role of Simulation-based Design in

Electronics Product RealizationTheme -- Warpage Worthiness

Enabling Technologies– Design-Analysis Integration– Standards-based Product and Process Models– Computer-based engineering framework for

analysis, validation and design enrichment

Future Research

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Electronics Product Realization

Environmental

Placement

Fabricate Test/Inspect

Part Symbol& Footprint

Assemble

Doc/Proc/RegGuidelines

Corrections

Release

Learn todayUtilize tomorrow

Functional

Layout

Req

uir

emen

ts

Routing Review

Des

ign

Build

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Simulation-based DesignElectronic Packaging Examples: PWA-B

Analysis Modules (CBAMs) of Diverse Mode & Fidelity

Design Tools

Laminates DB

FEA Ansys

General MathMathematica

Analyzable Product Model

XaiToolsPWA-B

XaiToolsPWA-B

Solder JointDeformation*

PTHDeformation & Fatigue**

1D,2D

1D,2D,3D

Modular, Reusable Template Libraries

ECAD Tools Mentor Graphics,

Accel*

temperature change,T

material model

temperature, T

reference temperature, To

cte,

youngs modulus, E

force, F

area, A stress,

undeformed length, Lo

strain,

total elongation,L

length, L

start, x1

end, x2

mv6

mv5

smv1

mv1mv4

E

One D LinearElastic Model(no shear)

T

e

t

thermal strain, t

elastic strain, e

mv3

mv2

x

FF

E, A,

LLo

T, ,

yL

r1

12 xxL

r2

oLLL

r4

A

F

sr1

oTTT

r3L

L

m a t e r i a l

e f f e c t i v e l e n g t h , L e f f

d e f o r m a t i o n m o d e l

l i n e a r e l a s t i c m o d e l

L o

T o r s i o n a l R o d

G

J

r

2

1

s h e a r m o d u l u s , G

c r o s s s e c t i o n :e f f e c t i v e r i n g p o l a r m o m e n t o f i n e r t i a , J

a l 1

a l 3

a l 2 a

l i n k a g e

m o d e : s h a f t t o r s i o n

c o n d i t i o n r e a c t i o n

t s 1

A

S l e e v e 1

A t s 2

d s 2

d s 1

S l e e v e 2

L

S h a f t

L e f f

s

T

o u t e r r a d i u s , r o a l 2 b

s t r e s s m o s m o d e l

a l l o w a b l e s t r e s s

t w i s t m o s m o d e l

M a r g i n o f S a f e t y( > c a s e )

a l l o w a b l e

a c t u a l

M S

M a r g i n o f S a f e t y( > c a s e )

a l l o w a b l e

a c t u a l

M S

a l l o w a b l et w i s t Analysis Tools

PWBWarpage

1D,2D

Materials DB

PWB Layup ToolXaiTools PWA-B

STEP AP210, GenCAM**,

PDIF*

* = Item not yet available in toolkit (all others have working examples) ** = Item available via U-Engineer.com

DFX

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ThemeAssessing Thermo-Mechanical Warpage of PWBs

Definition: WARPAGE is out of plane deformation of the artifact, caused by differential (non-homogenous) shrinkage or expansion of elements composing the artifact.

Out of plane deformation of a linear element

= (b L2 T) / t where

L: Undeformed Length; t: Undeformed Thickness; T: Temperature Change; b: Specific Co-efficient of Thermal Bending

Saddle Deformation

Bowl Deformation

Warpage of 2D artifacts ( basic modes)

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Warpage – Impact and RequirementsRef: Thinking Globally, Measuring Locally

Editorial by Patrick Hassell, AkroMetrix

Impact Low manufacturing yield and high rework of

interconnects– Lack of co-planarity of component footprints– Fine pitch technology– Low solder paste volume

Requirements Managing warpage requirements

– Enforce local warpage requirements– Relax global warpage requirements

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Multi-Representation Architecture (MRA) forDesign Analysis Integration

Tree View

Bare PWB

Electrical Mechanical Manufacturability

Warpage PTH Fatigue

Layered ShellEffective Materials Properties

Finite Element

Manufacturing Product Model

AnalysisProduct Model

Context-BasedAnalysis Model

AnalysisBuilding Blocks

SolutionMethod Model

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Multi-Representation Architecture (MRA) forDesign Analysis Integration

Stepping-Stone Model View

Solution Method Model

ABB SMM

Analysis Building Block

Context-Based Analysis Model

SMMABB

APM ABB

CBAM

APM

Manufacturing Product Model(STEP AP210-based)

Solution Tools(ANSYS, …)

Printed Wiring Assembly (PWA)

Solder Joint

Component

PWB

body3body2

body1

body4

T0

Printed Wiring Board (PWB)

SolderJoint

Component

AnalyzableProduct Model

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Complex Features Affecting Thermo-Mechanical Behavior

PCB outline

Comprised of straight lines and arcs (primitive level)

Mechanical (Tooling / Drilling) Hole

Circuit Traces

land

plated through hole

via

Footprint occurrence

This comprises of four lands, in this case. The component sits atop the lands.

Complete trace curve not shown

M150P2P11184

M150P1P21184

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Example PCA design: Hexapod (from EAGLE displayed in STEP-Book AP210)

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Product Enclosure

External Interfaces

Printed Circuit Assemblies(PCAs/PWAs)

Die/Chip Package

Packaged Part

InterconnectAssembly

Printed Circuit Substrate (PCBs/PWBs)

Die/Chip

STEP AP210 (ISO 10303-210) Domain: Electronics DesignR

~950 standardized concepts (many applicable to other domains)Development investment: O(100 man-years) over ~10 years

2003-04 - Adapted from 2002-04 version by Tom Thurman, Rockwell-Collins

Configuration Controlled Design of Electronic Assemblies,their Interconnection and Packaging

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Use of STEP AP210 (ontology) for MPM / APM description

Standard for Electronic Assembly Interconnect and Packaging Design

Assembly Models

• User View• Design View• Component Placement• Material product• Complex Assemblies with Multiple Interconnect

Component / Part Models• Analysis Support • Package• Material Product• Properties• “White Box”/ “Black Box”• Test Bench

Requirements Models

• Design• Constraints• Interface• Allocation

Functional Models

• Functional Unit• Interface Declaration• Network Listing• Simulation Models• Signals• Test Bench

Interconnect Models• User View• Design View• Bare Board Design• Layout templates• Layers

Configuration Mgmt• Identification• Authority • Effectivity • Control• Net Change

• Geometric Dimensioning and Tolerancing

Design Control

Rules Models• Design• Manufacturing• …

Geometric Models• 2D• 3D• CSG, Brep…• EDIF, IPC, GDSII compatible “trace” model

http://www.ap210.org

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Manufacturing Product Model (MPM) in anAP210 Standards-Based Engineering Framework

XaiToolsPWA-B

Eagle

LKSoft, …Gap-FillingTools

XaiToolsPWA-B LKSoft, …

Traditional Tools Mentor

Graphics

Manufacturing Product Model Components• STEP AP210

STEP-Book AP210,SDAI-Edit,

STI AP210 Viewer, ...

Instance Browser/EditorPWB Stackup Tool,…

ElectricalCAD Tools

pgpdm

Core PDM Tool

AP210interface

Doors

Slate

Systems EngineeringTools

- Eurostep AP233 Demonstrator- XaiTools AP233

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Overall Process -- Circuit Board Stackup Design &Warpage Analysis Using AP210 (WIP)

GIT and NIST EEEL in collaboration with AkroMetrix, InterCAX/LKSoft, and Rockwell Collins

STEP AP210-basedProduct Model

Identification of warpage “hotspots” on a PCB

thickness…

wid

th

length

1 Solution Method Model

ABB SMM

2 Analysis Building Block

4 Context-Based Analysis Model3

SMMABB

APM ABB

CBAM

APM

Design Tools Solution Tools

Printed Wiring Assembly (PWA)

Solder Joint

Component

PWB

body3

body2

body1

body4

T0

Printed Wiring Board (PWB)

SolderJoint

Component

AnalyzableProduct Model

Multi-Representation Architecture

Design-Analysis Integration Methodology

Analysis Building Block Model (idealized bodies with effective material properties)

PCB Warpage Profile(given: thermal profile + boundary conditions)

Validation Measurements in AkroMetrix

TherMoiré oven chamber

Feedback

http://eislab.gatech.edu/projects/

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Setting up context for warpage analysisAPM and ABB Creation

Grid (Sieve) Size

Single Layer View

…

Top view of “effective” grid elements in top layer of the PCB

…

Side view of the PCB with “effective” grid elements across

the stratums

thickness

wid

th

length

Given:

• Thermal loading profile

• Boundary Conditions (mostly displacement)

• Idealize PWB stackup as a layered shell

ABB ModelMPM / APM CBAM

Effective Material Property

Computation

CBAM attributes

• Thermal loading profile

• Boundary Conditions (mostly displacement)

• Idealize PWB stackup as a layered shell

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View of Solution Method ModelLayered shell mesh Geometric constraints

all 6 degrees of freedom locked at midpoint – boundary condition

Currently this model is tool-specific (ANSYS).

Future possibility of AP209-based implementation exists.

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-100

-50

0

50

100

150

200

Tem

per

atu

re (

C)

0

5

10

15

20

25

Model Exp't

Sca

le (

mil

s)

-50 C

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XaiTools PWAB A computer-based framework for multi-fidelity SBD for PWA-B

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ValidationRepresenting Validation Strategies

Metallization Grid

Feature BOM

JUnit-based Test Framework

STEP AP210-based x-ARM instance

Simulation and Experimental

Results

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Enablers for Design Enrichment

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Future ResearchAnalysis Level of Idealization – Grid Dimensions, Vias,… Controlled Meshing (non-tool specific) Printed Circuit Assembly Components

Experimental Validation Initial Conditions and Panelization Boundary Conditions and Reference Plane

Computer-based Engineering Framework

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Acknowledgements

Georgia Tech– Injoong Kim– Miyako Wilson

LKSoftWare Gmbh– Lothar Klein*– Giedrius Liutkus*– Kasparus Rudokas– Tomas Baltramaitas

Rockwell Collins, Inc.–Michael J. Benda*–David D. Sullivan–William W. Bauer–Mark H. Carlson

–Floyd D. Fischer

PDES Inc.Electromechanical Pilot Team*

–Greg Smith (Boeing)–Craig Lanning (Northrop Grumman)–Steve Waterbury (NASA)