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EE141 Microelettronica Packaging
EE141Microelettronica
Packaging
EE141Microelettronica
Interconnect hierarchy in traditional
IC packaging
ChipL
L ´
Bonding wire
Mountingcavity
Leadframe
Pin
•Bond wires (~25m) areused to connect the packageto the chip
• Pads are arranged in a frame around the chip
• Pads are relatively large (~100m in 0.25m technology)with large pitch (100m)
•Many chips areas are‘pad limited’
EE141Microelettronica
Packaging Requirements
Electrical: Low parasitics
Mechanical: Reliable and robust
Thermal: Efficient heat removal
Economical: Cheap
EE141Microelettronica
Bonding Techniques
Lead Frame
Substrate
Die
Pad
Wire Bonding
EE141Microelettronica
Tape-Automated Bonding (TAB)
(a) Polymer Tape with imprinted
(b) Die attachment using solder bumps.
wiring pattern.
Substrate
Die
Solder BumpFilm + Pattern
Sprocket
hole
Polymer film
Lead
frame
Test
pads
EE141Microelettronica
Chip Packaging
EE141Microelettronica
Chip Packaging
An alternative is ‘flip-chip’:
Pads are distributed around the chip
The soldering balls are placed on pads
The chip is ‘flipped’ onto the package
Can have many more pads
EE141Microelettronica
Flip-Chip Bonding
Solder bumps
Substrate
Die
Interconnect
layers
EE141Microelettronica
Package-to-Board Interconnect
(a) Through-Hole Mounting (b) Surface Mount
EE141Microelettronica
Package Types
6
71
2
5
3
4
1 Bare die
2 DIP
3 Quad flat pack
4 Small-outline IC
5 PLCC
6 PGA
7 Leadless carrier
EE141Microelettronica
Chip Socket
84 Pin PLCC SMPGA370 DIL 32
EE141Microelettronica
Parameters of various types of
chip carriers
EE141Microelettronica
Ball grid array packaging
(a) cross section(b) package bottom
EE141Microelettronica
Package Parameters
Typical capacitance and inductance values of package and bonding styles
EE141Microelettronica
Chip Packaging
EE141Microelettronica
Multi-Chip Modules
EE141Microelettronica
Impact of
Technology
Scaling
EE141Microelettronica
Goals of Technology Scaling
Make things cheaper:
Want to sell more functions (transistors)
per chip for the same money
Build same products cheaper, sell the
same part for less money
Price of a transistor has to be reduced
But also want to be faster, smaller,
lower power
EE141Microelettronica
Technology Scaling (1)
Minimum Feature Size
1960 1970 1980 1990 2000 201010
-2
10-1
100
101
102
Year
Min
imum
Featu
re S
ize (
mic
ron)
EE141Microelettronica
Technology Scaling Models
• Full Scaling (Constant Electrical Field)
• Fixed Voltage Scaling
• General Scaling
ideal model — dimensions and voltage scale
together by the same factor S
most common model until recently —
only dimensions scale, voltages remain constant
most realistic for todays situation —voltages and dimensions scale with different factors
EE141Microelettronica
Transistor Scaling (velocity-saturated devices)
EE141Microelettronica
Current-Voltage Relations
NMOS
EE141Microelettronica
Velocity Saturation
x(V/µm)xc
un(m
/s)
usat= 105
Constant mobility (slope = µ)
Constant velocity
IDLong-channel device
Short-channel device
DSV DSAT VGS T
VGS = VDD
- V V
EE141Microelettronica
ID versus VDS
EE141Microelettronica
ID versus VGS
EE141Microelettronica
Supply-Voltage Evolution
EE141Microelettronica
Subthreshold Conduction
II
GS
II
GST
EE141Microelettronica
Subthreshold Leakage Component
EE141Microelettronica
Technology Scaling (2)
Propagation Delaytp decreases by
13%/year
50% every 5 years!
EE141Microelettronica
Power Density Evolution
[1980 – 1995]
EE141Microelettronica
Wire Delay–Gate Delay Ratio Evolution
EE141Microelettronica
MOSFET Technology Projection
EE141Microelettronica
Technology Evolution (2000 data)
18617717116013010690Max P power [W]
1.4
1.2
6-7
1.5-1.8
180
1999
1.7
1.6-1.4
6-7
1.5-1.8
2000
14.9
-3.611-37.1-2.53.5-22.1-1.6
Max frequency
[GHz],Local-Global
2.52.32.12.42.0Bat. power [W]
109-10987Wiring levels
0.3-0.60.5-0.60.6-0.90.9-1.21.2-1.5Supply [V]
30406090130Technology node
[nm]
20142011200820042001Year of
Introduction
