Digital ICIntroduction

1.Introduction

If the automobile had followed the same

development cycle as the computer, a Rolls-

Royce would today cost $100, get one million

miles to the gallon and explode once a year

Most of slides come from Semiconductor Manufacturing Technologyby Michael Quirk and Julian Serda

Digital IC

outline

• Course Introduction

• a brief history

• Design Metrics

• DIC characteristics

• Design partitioning/CMOS logic

• Semiconductor processing

Digital IC

Semiconductor processing

• Semiconductor fabrication

• Layout fundamental

• Semiconductor testing

• Semiconductor assembling

Digital IC

Different Electrical Tests for IC Production

(From Design Stage to Packaged IC)

TestStage of IC

Manufacture

Wafer- or

Chip-LevelTest Description

IC Design Verification Pre-Production Wafer levelCharacterize, debug and verify new chip

design to insure it meets specifications.

In-Line Parametric

TestWafer fabrication Wafer level

Production process verification test

performed early in the fabrication cycle

(near front-end of line) to monitor process.

Wafer Sort (Probe) Wafer fabrication Wafer levelProduct functional test to verify each die

meets product specifications.

Burn-In Reliability Packaged ICPackaged

chip level

ICs powered up and tested at elevated

temperature to stress product to detect

early failures (in some cases, reliability

testing is also done at the wafer level

during in-line parametric testing).

Final Test Packaged ICPackaged

chip level

Product functionality test using product

specifications.

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Digital IC

Automated Electrical Tester

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Wafer Fab Process Flow with Test

Implant

Diffusion

Test/Sort

Etch

Polish

PhotoCompleted wafer

Unpatterned wafer

Wafer start

Thin Films

Wafer Fabrication (front-end)

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Digital IC

Wafer Test

• In-line Parametric Test (a.k.a. wafer electrical

test, WET)

• In-line test structure

• In-line test type

• In-line test data explain

• In-line test equipment

Scribe line with monitor test structures

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Digital IC

In-line Parametric Test

Systems• Probe card interface

• Wafer positioning

• Tester instrumentation

• Computer as host or

server/networkElectronic interface

Instrumentation

Computer

Probe card

Wafer positioning(X, Y, Z, q)

X-Y stageq-Z stage

8

Digital IC

Probe Card for Automatic Tester

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Examples of Test Structure

Test Structure Fault Measurement

Discrete transistorsLeakage current, breakdown voltage, thresholdvoltage and effective channel length

Various line widths Critical dimensions

Box in a box Critical dimensions and overlay registration

Serpentine structure overoxide steps

Continuity and bridging

Resistivity structure Film thicknessCapacitor array structure Insulator materials and oxide integrity

Contact or via string Contact resistance and connections

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Data Trends

• The same die location keeps failing a parameter

on a wafer.

• The same parameter is consistently failing on

different wafers.

• There is excessive variation (e.g., > 10%) in

measurement data from wafer to wafer.

• Lot-to-lot failure for the same parameter,

indicating a major process problem.

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Digital IC

Wafer Sort

• Wafer Sort (a.k.a. wafer probe)

• DC testing

• Output checking

• Function testing

• The Objectives of Wafer Sort

• Chip functionality: verify the operation of all chip functions to insure only

good chips are sent to the next IC manufacturing stage of assembly

and packaging.

• Chip sorting: sort good chips based on their operating speed

performance (this is done by testing at several voltages and varying

timing conditions).

• Fab yield response: Provide important fab yield information to assess

and improve the performance of the overall fabrication process.

• Test coverage: Achieve high test coverage of the internal device nodes

at the lowest cost.

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Digital IC

Wafer Bin Map with Bin Failures

1

1

1

6

1

5

4

1

1

1

1

1

1

1

1

1

1

12

1

1

1

1

1

1

1

1

1

10

1

1

10

3

1

1

1

1

4

1

1

1

10

7

1

1

1

1

1

1

10

1

10

12

1

7

1

1

1

1

1

2

12

6

1

1

1

2

1

1

1

1

1

1

1

7

1

1

3

10

1

1

7

1

1

1

1

1

1

2

Device: Example

Lot: Example

Wafer: 200 mm

Layer: Hardware Bins

Yield: 79.54%

Good: 70

Total: 88

Good

Bad

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Reduced Partial Die on Large Wafer

200 mm 300 mm

14.5% partial die

10.8% partial die

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Reduced Time to Product Maturity for

DRAM Production

-1 0 1 2 3 4 5 6 7

Year

DR

AM

Pro

be

Yie

ld, A

fter

Rep

air

100

80

60

40

20

0

R&D

PilotLine Full Production

16 Mb

256 Mb256 Kb

4 Mb64 Kb

64 Mb

1 Mb

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Digital IC

Semiconductor processing

• Semiconductor fabrication

• Layout fundamental

• Semiconductor testing

• Semiconductor assembling

Digital IC

Packaging Requirements

• Electrical: Low parasitics

• Mechanical: Reliable and robust

• Thermal: Efficient heat removal

• Economical: Cheap

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Digital IC

Important Functions of IC

Packaging• Protection from the environment and

handling damage.

• Interconnections for signals into and out of

the chip.

• Physical support of the chip.

• Heat dissipation.

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Traditional Assembly and Packaging

Wafer Test and Sort

Wire Bond

Die Separation

Plastic Package Final Package and Test

Die Attach

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Typical IC Packages

Quad flat pack(QFP)

Leadless chip carrier(LCC)

Plastic leaded chip carrier(PLCC)

Dual in-line package(DIP)

Thin small outline package(TSOP)

Single in-line package(SIP)

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Digital IC

Levels of IC Packaging

2nd level packaging:

Printed circuit board

assembly

First level packaging:

IC packaging

Final product assembly:

Final assembly of circuit

boards into system

Metal leads for mounting

onto printed circuit board

Pins

Pins are inserted into holes then soldered on rear of PCB.

Surface-mount chips are soldered

on top of tinned pads

on the PCB.

Edge connector plugs into main system.

PCB subassembly

Main electronics assembly board

Leads

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Digital IC

Traditional Assembly

• Wafer preparation (backgrind)

• Die separation

• Die attach

• Wire bonding

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Schematic of the Backgrind Process

Rotating and

oscillating spindle

Wafer on rotating chuck

Downforce

Table rotates only during

indexing of wafers

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Wafer Saw and Sliced Wafer

Wafer

Stage

Blade

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Typical Leadframe for Die Attach

DieLeadLeadframe

Plastic DIP

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Epoxy Die Attach

Die

Epoxy

Leadframe

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Wires Bonded from Chip Bonding Pads

to Leadframe

Moulding compound

LeadframeBonding pad

Die

Bond wire

Pin tip

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Wirebonding Chip to Leadframe

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Digital IC

Traditional Packaging

• Plastic Packaging

• Ceramic Packaging

• TO-Style Metal Package(old)

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General package mode

Plastic Dual In-Line Package (DIP)

for Pin-In-Hole (PIH)1970s-1980s

Single In-Line Package (SIP),

decreasing capacity and cost

Memory application

Thin Small Outline Package (TSOP)

Memory and smartcard Single In-

Line Memory Module (SIMM)

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Digital IC

General package mode

Quad Flatpack (QFP) with Gull

Wing Surface Mount Leads

Plastic Leaded Chip Carrier (PLCC)

with J-Leads for Surface Mount

Leadless Chip Carrier (LCC)

Ceramic interconnect layers

4-layer laminate

Laminated Refractory Ceramic

Process Sequence

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Advanced Packaging

• Flip chip

• Ball grid array (BGA)

• Chip on board (COB)

• Tape automated bonding (TAB)

• Multichip modules (MCM)

• Chip scale packaging (CSP)

• Wafer-level packaging

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Digital IC

Advanced Packaging

Solder bump on bonding padSilicon chip

Substrate

Connecting pin

Metal interconnectionVia

Bonding pad perimeter array

Flip chip bump area array

Flip Chip Package

Flip Chip Area Array Solder

Bumps Versus Wirebond

Solder bump

Chip

Epoxy

Substrate 33/57

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Ball Grid Array

Molded cover

Wire

Substrate

Metal via

Solder ball

Chip

Bonding pad

Epoxy

Thermal via

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Multichip Module (MCM)

MCM substrateIndividual die

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Summary

• MOS Transistors are stack of gate, oxide, silicon

Can be viewed as electrically controlled switches

• Build logic gates out of switches

• Draw masks to specify layout of transistors

• Using different packaging&assembing tech.

• to start designing schematics and layout for a

simple chip!

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