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8/3/2019 Nonlinear Wave Shaping

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Presented by APN Rao, Dept ECE, GRIET, Hyderabad. Jan 2012 1

Nonlinear Waveshaping using Diode Circuits

Text Book:

Pulse, Digital and Switching Waveforms

Jacob Millman, Herbert Taub

McGraw-Hill Kogakusha Ltd (1965)

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Practical Diode

V-I Characteristic

Presented by APN Rao, Dept ECE, GRIET, Hyderabad. Jan 2012 2

Diode

Approximation of Diode Characteristics: Considerations

a) Cut-in Voltage (Vγ): 0.3V(Ge), 0.7V(Si)b) Reverse Saturation (Leakage) Current (Is ): few μA

c) Forward Resistance (Rf ): few Ω

d) Reverse Resistance (Rr): many kΩ

e) Diode Capacitance: few pF

f) Effect of Temperature

V

IIdeal Diode

V-I Characteristic

V

I

Vγ

slope = 1/Rf

slope = 1/Rr

Piece-wise linear

approximation for

large signals

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VR +Vγ

VR +Vγ

vi

vo

Transfer Characteristic

Presented by APN Rao, Dept ECE, GRIET, Hyderabad. Jan 2012 3

Diode Clipper Circuits (Positive)

γ s f r

R γ R

γ

γ

R

assumptions: V 0, I = 0, R = 0, R =

D 'OF

D

F' v V +

'ON' v V +V ; v V +

v

V

V ; v

i

o i

o

i

R

VR

Dvi vo

R

VR

D

vi vo

Exercise:

Similarly analyse

Positive Series

Clipper

PositiveShunt

Clipper

t

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Presented by APN Rao, Dept ECE, GRIET, Hyderabad. Jan 2012 4

Diode Clipper Circuits (Negative)

γ s f r

R γ R

γ

γ

R

assumptions: V 0, I = 0, R = 0, R =

D 'OFF' v V V ;

D 'ON' v V V ; v V

v v

Vi o

i o i

R

VR

Dvi vo

VR - Vγ

VR

- Vγ

vi

voTransfer

Characteristic

R

VR

D

vi vo

Exercise:

Similarly analyse

Negative Series

Clipper

t

NegativeShunt

Clipper

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Presented by APN Rao, Dept ECE, GRIET, Hyderabad. Jan 2012 5

Diode Clippers with Rf ≠ 0 & Rr ≠ ∞

γ s f r

i R o i R i

f i R o i

f

r

R R

RD 'ON' v > V ; v = V + v VR + R

RD 'OF

assumptions: V 0, I = 0, R 0, R

F' v < V ; v = v + V vR + R

R

VR

Dvi vo

Choice of External Resistor R: For clipping operation to be close to ideal, we

should choose R >> Rf ; but to minimize distortion of vi passed, R << Rr is to

be chosen. An optimal choice is R = (Rf Rr)1/2

Circuit analysis is done replacing diode with Rf when forward-biased and with Rr

when reverse-biased.

VR

VR

vi

vo0

f

f

Rslope

R R

< 1r

r

Rslope

R R

In forward biased region, imperfect clipping

takes place since slope ≠ 0, and in reverse

biased region waveform distortion occurs since

slope ≠ 1. Ex: Carry out similar analysis for the

other diode clippers.

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Presented by APN Rao, Dept ECE, GRIET, Hyderabad. Jan 2012 6

Effect of Diode Capacitance

Diode capacitance (in pF) shunts the diode, and acts as a short for any discontinuities

in input voltage. High frequency components are passed even when diode is reversebiased. Depending on location of diode in the circuit, waveshape changes will occur.

Portions of the waveform will be depend on charging/discharging process of the

diodecapacitance.

Diode Clippers with Is = non-zero constantR

VR

Dvi vo

γ s f r

i R γ o i

R γ o

s

i R γD 'ON' v > V

assumptio

D

ns: V 0, I 0,

'OFF'

R 0, R

v < V + V

+ V ; v

;

=

v =

V +

+

V

v I R

For Is = non-zero constant, the output when diode is in OFF region gets modified.

Exercise: Analyse the other three diode clipperssimilarly.

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Effect of Diode Capacitance: Example

RD

vi vo

C1

C2R

Rf

vi vo

C1

C2 R

Rr

vi vo

C1

C2

C1 = Diode capacitance (pF)

C2 = Input capacitance (pF)

Equivalent Circuit for D ‘ON’ Equivalent Circuit for D ‘OFF’

+5 V

-5 V

vi

5V

0 V

2 V

vo

τ1 = 2.5ns

τ2 = 25μs3 V

Example: C1= 5 pF, C2 = 20

pF, Rf = 100 Ω, R = 1 MΩ, Rr

= ∞. Find and sketch

response to input squarepulse ±10V.

Exercise: Repeat the above problem with diode and R interchanged in the negative

series clipper circuit shown.

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Two-level Diode Clippers: ExamplesR

VR1

D1vi vo

VR2

D2

vo

viVR2

VR2

VR1

VR1

Note: Two independent clipping

levels. Above circuit can eliminate

noise riding The peaks of a squarewave.(Assumed VR2 > VR1)

D1 D2 vo

vi ≤ VR1 ON OFF ≈ VR1

VR1 ≤ vi ≤ VR2 OFF OFF vi

vi ≥ VR2 OFF ON ≈ VR2

R

Z1

vi vo

Z2

Zener diode-clipper

Zener voltages VZ1 and VZ2

Z1 Z2 vo

vi ≥ VZ2 + Vγ ON breakdown VZ2 + Vγ

vi ≤ -(VZ1 + Vγ ) breakdown ON -(VZ1 + Vγ )

VZ2 + Vγ

≥ vi ≥ -(VZ1 + Vγ )OFF/ON ON/OFF vi

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Two-level Diode Clippers: Examples

Rvi vo

D1 D2 vo

vi ≤ -Vγ ON OFF vi + Vγ

-Vγ ≤ vi ≤ Vγ OFF OFF 0

vi ≥ Vγ OFF ON vi - Vγ

D1

D2

Vγ ≠ 0

(Exercise: Sketch transfer characteristic.)Noise Clipper: Eliminates noise of small amplitudes.

vi vo

100V25V

200K100K

D1 D2Solution:

Assuming ideal diodes,

vi ≤ 25 V v0 = 50 V

25V ≤ vi ≤ 100 V v0 = v i

v ≥ 100 v0 = 100 V

(Exercise: Sketch the

transfer characteristic)

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Clamping Circuit: Ideal Diode

Analysis assuming ideal diode

t < t 1: D is forward biased. C

charges instantaneously (with

zero time-constant ) to input

voltage. vC = v i ; vo = vi – vC = 0

t = t 1: v i reaches first peak = +V

volts. vC = V

t > t 1: D is reverse biased. C

has no discharge path. vC =

constant = V; vo = vi – V; output

positive peaks are clamped to

0 volt level. Hence called

Positive Clamper

vi

vc

vo = vi - vc

+V

-V

0V

-2V

+V

0V

t

t

t

t1

Exercise: Analyze and verify that

the circuit with diode reversed

operates asa negative clamper.

vi vo

C

D

vc+ -

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Clamping Circuit: Ideal Diode

Increased amplitude peaks are clamped by instantaneous charging ofcapacitor. However, since discharge path is not available, clamping is

ineffective for decreasing amplitude waveforms.

Case of decreasing amplitudeCase of increasing amplitude

vi

vo

0 V

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Clamping Circuit: Non-ideal Diode

With Rf ≠ 0 and Rr ≠∞, the capacitor-diode circuit operates as a high-pass circuit

switching between diode ON/OFF states with effective resistance alternating

between Rf andRr .

Equivalent circuits for analysis

when

diode

forwardbiased

when

diode

reversebiased

Biasing condition of diode depends on polarity of vo = vi – vC.

(ON if vo positive and OFF if negative)

vi vo

C

Rf D ‘ON’

τf = Rf C

vi vo

C

RrD ‘OFF’

τr = Rr C

With finite Rf and Rr ,the capacitor at any instant is either charging or discharging,

hence is vC is never constant. The dc (average) level of input waveform gets shifted

by the dc (average) level of capacitor voltage.

For effective clamping of increasing or decreasing amplitude waveform-peaks, bothcharging and discharging time-constants have to be reasonably small. For this

purpose, the diode is shunted with an external resistance R such that Rf << R << Rr .

Analysis at input discontinuities: If the discontinuity includes both forward and

reverse-biased conditions, both the above circuits need to be used, using the

principlethat capacitor voltage does not change during the transition.

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Practical Clamping Circuit: with Rs ≠ 0

Charging/ discharging time-constantsDiode ON (vo > 0) : (Rf +Rs)C

Diode OFF (vo < 0) : (R+Rs)C

Example: Rs = Rf = 100 Ω, R = 1 0 K , C = 1

μF. Find response (first two cycles) to a

symmetric square wave input 0-10 V,frequency = 5 kHz. Capacitor uncharged at

t = 0 .

vs vo

C

D R

vs

vo

C

Rf

D ‘ON’

τf =

(Rf +Rs)C

Rs

vs

vo

C

R

D ‘OFF’

τr =

(R +Rs)C

Rs

Rs

53 3 1.8 1.8 1.1

− 4

− 6.4

− 7.8

10

t0

100 μs100 μs

vo

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Steady State Analysis: Clamping Circuit TheoremThe capacitor voltage varies continuously, as charging / discharging current is always

present. The average (dc) level of input periodic waveform is biased by the average

(dc) level of the capacitor v

at steady state

oltage. Steady

, the net charg

state is reached when average

e acquired by the capacitor

ov

capacitor voltage

r

er a cycle must be

eaches a st

zero.

eady value. Thus,

This principle is the ba .sis of Clamping Circuit Theorem

vs vo

C

D

R

if ir

r f f

f o r o

As R >> R >> R , effective resistance = R while charging and R while discharging.

Let charging current = i (D "ON", v > 0) & discharging current = i (D"OFF",v < 0)At steady state, net charge gaine

" " " "

d by C should = 0 f r

D ON D OFF

i dt i dt

0 0

0 0

" " " "

(with D "ON"), (with D"OFF")

Define A , and A

Then

o o

f r f r

f

f of r or

v v

f r

D ON D OFF

f f

r

v vi i

R R

v dt v dt

i dt i dt A R

A R

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V′ V′

V′′ V′′ V′′

V1

V2

V1′

V2′ V2′

V1

V2

V1′

vs

vo

T1 T2V

Presented by APN Rao, Dept ECE, GRIET, Hyderabad. Jan 2012 15

Steady State Response to Square Wave Input

1

f s

2

s

T

R + R C1 1

T

R + R C

2 2

f s s1 2

f

f s s1 2

f

V V e (1)

V V e (2)

R + R R + RV = V V (3)

R R

R + R R + RV = V V (4)

R R

Equations 3 and 4 are derived using the principle that capacitor voltage is unaffected during

discontinuous changes at input.

sf

f s

1 1 2 2From 3 & 4, and defining f V V and r V V

R + RRf r If R 0, f r

R +R

, we get

.R

s

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R

f R 1 f

r R 2

R

A Rholds if A and A are computed

A R

with respect to dc level V . If A and A are

with respect to zero level, the relatio

Positive peaks are clamped at V

A V T R=

n beco

A + V T

e

R

m s

f f

f r

r

f r

Presented by APN Rao, Dept ECE, GRIET, Hyderabad. Jan 2012 16

Introducing Fixed VR

vs vo

C

DR

if ir

VR

vs vo

C

D

R

if ir

VR

X

X

f R 1

f

f

r

R

At x-x, dc level of waveform is zero

(highpass effect). With the conditions that

the amplitude is at least V and R >> R ,

and V 0, clam

A

ping the

V

ore

+V

m becom

T R=A

e

R

s

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Transmission (Attenuation) Factors

o s o s

o s

s

f

f s

s

v (R 0) v (R 0) when diode is forward biased.

= v (R 0) when diode is reverse biased.

Non-zero R causes unequal attenuation to different parts of

wavef

R

R + RR

R

orm and

+

t r

R

he ef

o i

ore causes distortion.

(Note: This attenuation is on v , not on v )

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