Norhayati Soin 06 KEEE 4426 WEEK 13/2 24/03/2006 CHAPTER 5 Microelectronic Design Technology.

Norhayati Soin 06 KEEE 4426 WEEK 13/2 24/03/2006

CHAPTER 5

Microelectronic Design Technology


Classifications of Integrated Circuits

Memory chips (SRAM, DRAM, Flash, ROM, PROM)

Standard Components (74LS..)

Application-Specific Integrated Circuits— Widely used in communication, network, and multimedia systems

— For a given application, ASIC solutions are normally more effective than the solutions based on running software on microprocessors

— Many chips in cellular phones, network routers, and game consoles are ASICs

— Most SoC (Systems-on-a-Chip) chips are ASICs


Implementation choices


ASICs vs. FPLDs (+ pizza equivalent)

Full-custom ASICPrepare pizza sauce, toppings, doughfrom scratch; takes a long time

Standard-cell-based ASICChoose from limited selection of toppingsand dough; less work but still slow

Gate-array-based ASICAdd canned toppings to pre-cookedcrusts; save some time and cost

Field-programmable logic device Frozen pizza — limited selection, trivial tocook, very cheap


ASIC Design Methodologies

ASIC Design Methodology

This approach is extremely slow, expensive

It is only used to design very high performance systems

Full-custom design

This approach is reasonable fast, less expensive

Most ASICs are currently designed using this method

Standard-cell based design

This approach is fast and less expensive

ASIC performance are relatively slow

Gate-array based design

The design process is very fast and cost effective

ASIC performance are slow

FPGA based design


ASIC Design Flow1.Design entry. Using a hardware description language (HDL) or

schematic entry.

2. Logic synthesis. Produces a netlist—logic cells and their connections.

3. System partitioning. Divide a large system into ASIC-sized pieces.4. Prelayout simulation. Check to see if the design functions correctly.5. Floorplanning. Arrange the blocks of the netlist on the chip.6. Placement. Decide the locations of cells in a block.7. Routing. Make the connections between cells and blocks.8. Extraction. Determine the resistance and capacitance of the

interconnect.9. Postlayout simulation. Check to see the design still works with the

added loads of the interconnect.


ASIC Design Flow


Full-Custom Design Methodology

Function Partition

Schematic Design

Function And Timing verification

Pass

Fail

Including transistor sizing

Layout DesignIncluding placement & routing

Post-Layoutsimulation

Pass

Fail

Go to fabrication

ASIC Chips

It is a time consuming manual process, not pre-developed libraries needed.


Full-Custom Design Methodology

Design a chip from scratch.

Custom mask layers are created in order to fabricate a full-custom IC.

Engineers design some or all of the logic cells, circuits, and the chip layout specifically for a full-custom IC.

Advantages: complete flexibility, high degree of optimization in performance and area.

Disadvantages: large amount of design effort, expensive.


Standard-Cell Based Design Methodology

Use pre-developed logic cells from standard-cell library as building blocks. As full-custom design, all mask layers need to be customized to fabricate a new chip.

Advantages: save design time and money, reduce risk compared to full-custom design.

Disadvantages: still incurs high non-recurring-engineering (NRE) cost and long manufacture time.

A

B CD

AD

Library Cells

D

A B

C


Gate-Array Based Design Methodology

Generating schematic (netlist)

The netlist can be designed using full-custom or standard-cell based design method

Placement & Routing

Post-Layout verification

Make the final connections for thepre-fabricated gate array base

ASIC Chips

This approach is faster than the standard-cell based approach because part of the fabrication process has been complete.


Gate-Array Based Design Methodology Parts of the chip (transistors) are pre-fabricated, and other parts (wires) are custom fabricated for a particular customer’s circuit.

Advantages: cost saving (fabrication cost of a large number of identical template wafers is amortized over different customers), shorter manufacture lead time.

Disadvantages: performance not as good as full-custom or standard-cell-based ICs.

Gate Array Sea-of-Gates


FPGA Based Design Methodology

Schematic Capture

HDL coding &Logic Synthesis

netlist

ImplementationTechnology mappingPlacement & routing

Verification Timing verification

Pass

Fail

Generate FPGA Bit Stream

Download

FPGA

This approach has extremely fast turn-out time since FPGA devices has been fabricated.


Comparison of Design Methodologies

Full-custom

design

Standard-cell

based design

Gate-array

based design

FPGA-based

design

Speed +++ ++ + -

Integration density +++ ++ + --

High-volume device cost

++ ++ + +

low-volume device cost

--- -- + +++

Custom mask layer All All Some None

Fabrication time --- -- - +++

Time to Market --- -- ++ +++

Risk reduction --- -- - +++

Future design modification

--- -- - +++

+ desirable; - not desirable


Why do we want FPGAs

Fast turn-out time The ability of re-programming

The capability of dynamic reconfiguration

Advantages of using FPGAs

FPGA Applications

Ideal platform for prototyping Providing fast implementation to reduce time-to-market

Cost effective solutions for products with small volumes on demand

Implementing hardware systems requiring re-programming flexibility Implementing dynamically re-configurable systems


Design Constraints for Digital ICs

CLK

Vin1Vin2Vin3

Vout1

Vout2

Delay (speed) constraints

Power constraints

Area constraints

— For example, the delay from Vin1 to Vout1 should be smaller than 10 ns; the clock frequency should be greater 100MHz

Circuit Under construction


How to Find Circuits Complying with Design Constraints

Full-custom approach Standard-cell based approach

Gate-array approach

FPGA approach

1. It heavily depends on designers’ expertise.

2. Finding a proper circuitimplementation can bevery time consuming.

3. Very creative circuit implementations can beachieved.

1. These approaches heavily use design automation techniques to search circuits complying with constraints.

2. They are time saving approaches.3. These approaches require

pre-developed technology libraries.4. The quality of the final implementation

depends on algorithms and librariesused in the search.


Example: How to Search a Proper Circuit Implementation in FPGA Design Flow

Given Logic Function

FPGA Library Components

Design Constraints

a

b

c

d

e

— This circuit is either from schematic capture or from logic synthesis

— The library contains five components— Three inverters at size 1, 3, 5— Two two-input NAND gates at size 1 and 3

— The maximum delay between an input and an output should not exceed 5 ns



Step 1: Use the available logic gates to implement the given function. (Technology Mapping)

Step 2: Select proper size for each gate used in the above circuit. (Gate Sizing)

a

b

c

d

e

1X 3X

1X

1X

3X

— After this step, the circuit can be simulated to verify that it complies with timing constraints.— In the simulation, the parasitic capacitance and resistance on interconnects are estimated (Estimated wire load)

a

b

c

d

e

INV1

INV2

INV3

NAND1

NAND2



Step 3: Determine where to place these gates and how to connect them (Placement & Routing).

INV1

INV2 INV3

NAND1

NA

ND

2

— Some algorithms first place the components and then route the interconnects.— Some algorithms perform the placement and routing simultaneously

Steps 1, 2, and 3 are included in the implementation phase of the FPGA design Flow

Step 4: Perform post-layout simulation to verify that the generated circuit complies with timing constraints

— Since detail information of each interconnect is available, the circuit can be simulated with accurate wire load.— The process that writes the accurate wire load into the circuit netlist is called back annotation


Programmable Logic Devices (PLDs)


Programmable Logic Devices (PLDs)

Standard ICs, available in standard configurations, sold in high volume

•No customized cells or masks, just a single large block of programmable interconnect

•Can be configured / programmed tocreate a specialized device

•Fast turn-around timeExamplesMask-programmable ROM — programmed when ordered

Programmable ROM — programmed electrically, erased electrically or using ultraviolet light, all by customer


Definitions

Field Programmable Device (FPD):

— a general term that refers to any type of integrated

circuit used for implementing digital hardware, where the

chip can be configured by the end user to realize

different designs. Programming of such a device often

involves placing the chip into a special programming unit,

but some chips can also be configured “in-system”.

Another name for FPDs is programmable logic devices

(PLDs).

Source: S. Brown and J. Rose, FPGA and CPLD Architectures: A Tutorial, IEEE Design and Test of Computer, 1996


Classifications PLA — a Programmable Logic Array (PLA) is a relatively small FPD that contains two levels of logic, an AND- plane and an OR-plane, where both levels are programmable

PAL — a Programmable Array Logic (PAL) is a relatively small FPD that has a programmable AND-plane followed by a fixed OR-plane

SPLD — refers to any type of Simple PLD, usually either a PLA or PAL

CPLD — a more Complex PLD that consists of an arrangement of multiple SPLD-like blocks on a single chip.

FPGA — a Field-Programmable Gate Array is an FPD featuring a general structure that allows very high logic capacity.


Programmable Logic Array (PLA)

Programmable AND Plane

X Y O1 O2 O3 O4

Programmable Node

Programmable OR Plane

Connect

Disconnect

X X Y Y

XY

XY XY

XYXY

Un-programmed


Programmable Logic Array (PLA)

Programmable AND Plane Programmable OR Plane

X Y Z XY+YZ ? ?

XZ+XYZ

YZ

XZ

XYZ

XY


PALProgrammable AND Plane

X Y O1 O2 O3 O4

Fix OR Plane


PAL with Logic Expanders

Programmable AND Plane

Logic expanders

Fix OR Plane

?


PLA v.s. PAL

PLAs are more flexible than PALs since both AND & OR planes are programmable in PLAs.

Because both AND & OR planes are programmable, PLAs are expensive to fabricate and have large propagation delay.

By using fix OR gates, PALs are cheaper and faster than PLAs.

Logic expanders increase the flexibilities of PALs, but result in significant propagation delay.

PALs usually contain D flip-flops connected to the outputs of OR gates to implement sequential circuits.

PLAs and PALs are usually referred to as SPLD.


Complex PLD (CPLD)

PAL-likeblock

PAL-likeblock

PAL-likeblock

PAL-likeblock

I/O block

I/O block

I/O block

I/O block

Programmable interconnect

A CPLD comprises multiple PAL-like blocks on a single chip with programmable interconnect to connect the blocks.

CPLD Architecture


FPGA Overview

Simplified version of FPGA internal architecture:

• Basic idea: two-dimensional array of logic blocks and flip-flops with a means for the user to configure:

1. the interconnection between the logic blocks,

2. the function of each block.


FPGA

FPGA consists of an array of programmable basic logic cells surrounded by programmable interconnect.

FPGA Structure

Logic cell

Programmable interconnect

I/O Cell


FPGA

Families of FPGA’s differ in:

•Physical means of implementing user programmability,arrangement of interconnection wires, and the basic functionality of the logic blocks.

•Most significant difference is in the method for providing flexible blocks and connections


FPGA v.s. CPLD

Capacitance

SPLDs CPLDs FPGAs

Equivalent gates 0 ~ 200 200 ~ 12,000 1000 ~ 1,000,000

Applications

CPLDs FPGAs

1. Implement random glue logics or Replace circuits previously implemented by multiple SPLDs

2. Circuits that can exploit wide AND/OR gates, and do not need a very large number of flip-flops are good candidates for implementation in CPLDs.

1. FPGAs can be used in various applications: prototyping, FPGA-based computers, on-site hardware re-configuration, DSP, logic emulation, network components, etc.


Programming Technologies


Programming Techniques in Configurable ICs

Poly-Diffusion Antifuse

Metal-Metal Antifuse

SRAM-Based Programming Technique

EPROM-based Programming Technique

EEPROM-based Programming Technique


Poly-Diffusion Antifuse An antifuse is the opposite of a regular fuse. It is an open path until a programming current is forced through it by applying a high programming voltage across it.

Advantage: small (allow denser switch population).

Disadvantage: only one-time programmable.

Antifuse

wire

wireDiffusion

Oxide

Polysilicon Dielectric


Example: Antifuse Techniques in PAL & PLA

X X Y Y

XY

Implementation of wired-AND gate

X X Y Y

Burn thisantifuse

Burn thisantifuse


Metal-Metal Antifuse Cross section of a metal-metal antifuse

Metal 2Oxide

Metal 1 Dielectric

Parasitic effects of antifuse

wire

wire

wire

wire

Parasitic resistance

Parasitic capacitance

Antifuse is programmed to be ON Antifuse is programmed to be OFF


SRAM-Based Programming technique Use SRAM cells to control pass transistors or multiplexers by the bit-content in the SRAM cells.

Advantage: re-programmable.

Disadvantage: occupy more space.


Example: SRAM-Controlled Programmable Switch


EPROM & EEPROM Programming technique An EPROM (EEPROM) cell looks like a normal MOS transistor except that it has a second, floating, gate.

To program an EPROM (or EEPROM) cell, apply a high voltage to the drain of the transistor. It results in electrons trapped in the floating gate and consequently increasing the the threshold voltage.

To erase an EPROM cell, expose the chip to UV light.

To erase an EEPROM cell, electrical field is used to remove electrons from the floating gate.


EPROM & EEPROM Programming technique

X X Y Y

XY

Implementation of wired-AND gate

X X Y Y

HighVt

LowVt

LowVt

HighVt


Comparison of Different Programming Techniques

Programming technology

SRAMPoly-

Diffusion antifuse

Metal-Meta antifuse

EPROM EEPROM

Manufacturing

Complexity+ - - - -

Re-programmable?Yes

In circuit No No

Yes

Out of circuit

Yes

In circuit

Physical size Large (12X) Small (2X) Small (1X) Small Small

ON resistance () 600–800 100–500 30–801-4K

1-4K

OFF capacitance (fF) 10–50 3–5 110–50

10–50

Power consumption ++ + + - -

Volatile? Yes No No No No

+ Desirable; - no desirable


ASICs vs. FPLDs

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Norhayati Soin 06 KEEE 4426 WEEK 13/2 24/03/2006 CHAPTER 5 Microelectronic Design Technology.

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