Homework #5 Solution CSE140 Fall 2014
Note: Total 60 points for trial. (Total 100 points) 1: 20 points for trial 1(1): 10 points for correctness 1(2): 30 points for correctness 2(1): 10 points 2(2): 30 points
1. System Design: Implement the following algorithm.
Alg(X, Y, Z, req, ack) Input X[7:0], Y[7:0], req; Output Z[7:0], ack; Local-object A[7:0], B[7:0]; S1: If req’, goto S1 || ack ⇐ 1; S2: ack ⇐ 0 || A ⇐ X || B ⇐ Y; S3: If (A>0), goto S5; S4: A ⇐ A+B || goto S3; S5: Z ⇐ A || ack ⇐ 1 || goto S1; end Alg
(1). Design a data subsystem that is adequate to execute the algorithm and draw the schematic diagram.
Relationship between statement, operation and control. State Statement Operation Control
S2 A ⇐ X A ← Load(X) C0=1 and C2=0 S2 B ⇐ Y B ← Load(Y) C1=1 S3 A > 0 Comp(A, 0) S4 A ⇐ A+B A ← Add(A, B) C0=1 and C2=1 S5 Z ⇐ A Wires ack =1
Note: C0 is for register A, C1 is for register B, and C2 is for MUX.
Schematic diagram for data subsystem.
Rubric
• Table does not deduct any points. • If the diagram is fully correct, then 10 points.
NOTE: The implementation for A>0 can be done by OR together from A[n-‐2] to A[0] and then AND with A'[n-‐1].
(2). Design the control subsystem. (i) Draw the state diagram; (ii) implement the control subsystem with the style of one hot encoding. Draw the logic diagram to demonstrate the design.
State diagram.
Table for control subsystem. C0 C1 C2 ack
S1 0 0 X 1 S2 1 1 0 0 S3 0 0 X 0 S4 1 0 1 0 S5 0 0 X 1
Note: C0 is for register A, C1 is for register B, and C2 is for MUX.
Logic Diagram.
Rubric
• State diagram, table, and logic diagram have 10 points, respectively (i.e., total 30 points). • If label is missing/incorrect, each deducts 2 points.
2. System Design: Implement the following algorithm.
Alg(X, Y, req, W, U, ack) Input X[7:0], Y[7:0], req; Output W[7:0], U[7:0], ack; Local-object A[7:0], B[7:0], C[3:0], D[7:0]; S1: If req’, goto S1 || ack ⇐ 1; S2: ack ⇐ 0 || A ⇐ X || B ⇐ Y || C ⇐ (0111) || D ⇐ Clear(D); S3: If (A < B) goto S5; S4: A ⇐ A - B || D ⇐ D+1; S5: If (C==0), goto S7 || C ⇐ C-1; S6: B ⇐ Shift(B, R, 1) || D ⇐ Shift(D, L, 1) || goto S3; S7: W ⇐ A || U ⇐ D || ack ⇐ 1 || goto S1; end Alg
(1). Design a data subsystem that is adequate to execute the algorithm. Draw the schematic diagram to show the design.
Relationship between statement, operation and control. State Statement Operation Control
S2 A ⇐ X A ← Load(X) C0=1 and C5=0 S2 B ⇐ Y B ← Load(Y) C1=1 and C6=0 S2 C ⇐ (0111) C ← Load(0111) C2=1 and C7=0 S2 D ⇐ Clear(D) Clear(D) C3=0 and C4=1 S3 A < B Comp(A, B) S4 A ⇐ A-B A ← Sub(A, B) C0=1 and C5=1 S4 D ⇐ D+1 D ← Inc(D) C3=1, C4=0 and C8=0 S5 C == 0 Comp(C, 0) S5 C ⇐ C-1 C ← Dec(C) C2=1 and C7=1 S6 B ⇐ Shift(B, R, 1) B ← SHR(B) C1=1 and C6=1 S6 D ⇐ Shift(D, L, 1) D ← SHL(D) C3=1, C4=0 and C8=1 S7 W ⇐ A Wires S7 U ⇐ D Wires
Note: C0 is LD of register A, C1 is LD of register B, C2 is LD of register C, and C3 is LD of register D. C4 is CLR of register D. C5 is MUXing X and A, C6 is MUXing Y and B, C7 is MUXing C, and C8 is MUXing D.
Schematic diagram for data subsystem.
NOTE: The implementation for C==0, we can NOR together from C[n-‐1] to C[0].
(2). Design the control subsystem. (i) Draw the state diagram; (ii) implement the control subsystem with the style of one hot encoding. Draw the logic diagram to demonstrate the design.
State diagram.
Table for control subsystem.
State C0 C1 C2 C3 C4 C5 C6 C7 C8 ack LD, reg A LD, reg B LD, reg C LD, reg D CLR, reg D Sel, MUX at A Sel, MUX at B Sel, MUX at C Sel, MUX at D
S1 0 0 0 0 0 X X X X 1 S2 1 1 1 0 1 0 0 0 X 0 S3 0 0 0 0 0 X X X X 0 S4 1 0 0 1 0 1 X X 0 0 S5 0 0 1 0 0 X X 1 X 0 S6 0 1 0 1 0 X 1 X 1 0 S7 0 0 0 0 0 X X X X 1
Note: C0 is LD of register A, C1 is LD of register B, C2 is LD of register C, and C3 is LD of register D. C4 is CLR of register D. C5 is for MUXing X and A, C6 is for MUXing Y and B, C7 is for MUXing C, and C8 is for MUXing D.
Logic Diagram.
