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Novel Isolated Bidirectional Integrated DualThree-Phase Active Bridge (D3AB) PFC Rectifier
F. Krismer, E. Hatipoglu, and J. W. KolarPower Electronic Systems Laboratory, ETH Zurich, Switzerland
Abstract—This Paper proposes a novel Dual Three-PhaseActive Bridge (D3AB) PFC rectifier topology for a 400Vdc distribution system, which features galvanic isolation, bidi-rectional power conversion capability, a high level of componentintegration, and can be dimensioned with respect to high effi-ciency. In the course of a comprehensive and in-depth analyticalinvestigation, the working principle of the D3AB PFC rectifieris described in order to enable converter modelling and thederivation of mathematical expressions and limitations neededfor converter design and optimization. The developed convertermodels are verified by means of circuit simulations. An overalloptimization of a system with 400V line-to-line input voltage,400V dc output, and Pout = 8kW rated power with respectto efficiency and power density reveals the feasibility of a full-load efficiency of 98.1% and a power density of 4 kW/dm3 ifSiC MOSFETs are used. The finally presented design is foundto achieve efficiencies greater than 98% for Pout > 1.7 kW.
I. INTRODUCTION
Recent efforts with regard to a more sustainable electricpower generation propose the installation of distributed dc mi-crogrids in order to effectively utilize distributed renewableenergy sources [1]. A dc microgrid architecture typicallyincorporates dc sources (e.g. photovoltaic, fuel cell), energystorages (e.g. batteries), and loads (e.g. household appliances,IT equipment, electric vehicles) and employs an isolated bidi-rectional rectifier system to establish energy transfer betweenthe dc grid and the three-phase ac mains.
This paper evaluates a novel topology of a grid-connected,bidirectional, and isolated three-phase power factor corrected(PFC) rectifier with a rated power of Pout = 8 kW andfurther specifications as listed in Tab. I, which fulfills therequirements of bidirectional conversion capability and gal-vanic isolation with very low complexity. Due to the versatilityof the proposed system, it is suitable for various further
a
b
c
+
−−
three-phasemains
dc port 1 dc port 2
ac port
dc distributionsystem
1+ – Vdc2 2
1− – Vdc2 2
Lm = Lac
Lσ
+
−va1 Cf1
+−
va2 Cf2
+− vLaiLa
iLac,a
iLσ,a
primary side secondary side
Fig. 1: Proposed bidirectional converter topology with a three-phase ac input port, a dc output port 1 and an isolated dc output port 2.
applications including PFC rectifiers for common dc busarchitectures as, for example, used in efficiency-optimizedmulti-axis drive systems [2], where it is reasonable to consideradvanced rectifier topologies to define the electric potentialof a dc terminal, include a battery to buffer outages, etc.Furthermore, the system could e.g. be implemented for batterychargers of plug-in hybrid electric vehicles [3].
Conventional realizations of three-phase and isolated ac–dcrectifiers are two-stage solutions, with grid-side rectifiers andseries-connected isolated dc–dc converters [4], [5], [6]. Two-stage converter systems feature the advantages of decoupledfunctional parts, at the cost of higher expected losses dueto the high number of power components in the currentpath. State-of-the-art research with regard to more efficientconverter topologies reveals various solutions that combinePFC functionality, galvanic isolation, and voltage conver-sion in a single stage. In this context, isolated single-stagePFC rectifiers, based on isolated Swiss-forward or matrix-type topologies [7], [8], [9], represent suitable but complexsolutions. With regard to reduced converter complexity, adirect connection of the high frequency (HF) transformer of asingle-phase dc–dc converter to a three-phase PFC rectifieris proposed in [10], which, due to the asymmetry of theconverter, is considered more viable for lower power levels.Further level of integration is achieved with a topology withcoupled input inductors proposed in [11]. There, the isolateddc port is immediately coupled at the ac port in order to reducethe number of power components in the current path andachieve increased efficiency. The required coupled inductorsand the high number of IGBTs (24), though, render thepresented converter structure comparably complex.
TABLE I: Specifications of the D3AB PFC rectifier.
Nominal mains line-to-phase voltage (rms value) Vac = 230 V
Mains frequency fm = 50 Hz
Nominal output dc voltage, port 1 (not isolated) Vdc1 = 800 V
Nominal output dc voltage, port 2 (galv. isolated) Vdc2 = 400 V
Nominal output power Pout = 8 kW
This paper proposes a novel isolated bidirectional DualThree-Phase Active Bridge (D3AB) PFC rectifier topology,depicted in Fig. 1, that aims for high level of integrationand, for this, integrates the functionalities of PFC inductorsand HF transformers. Thus, the system essentially combinesthe functionalities of a bidirectional three-phase PFC rectifierand a three-phase Dual Active Bridge (DAB) converter andprovides three power ports, i.e, the ac (input) port, a dc (out-put) port without isolation, and an isolated dc (output) port.With a total of twelve power MOSFETs, and since thetwo-level three-phase rectifier structure facilitates the use ofconventional 6-pack power modules, the proposed structurefeatures reduced realization complexity compared to state-of-the-art solutions. The paper is organized as follows. Sec-tion II presents a comprehensive description of the proposedconverter system and, for this purpose, first investigates theproperties of a single-phase version of the system and thenextends the analysis to the three-phase system. Subsequently,Section III summarizes results of a converter optimizationwith respect to efficiency and power density. Section IV,finally, evaluates a selected design of the D3AB PFC rectifierwith regard to losses, volumes, and efficiency in order toassess the suitability of the proposed concept for the givenapplication.
II. OPERATING PRINCIPLE
The input inductors, Lac, of a conventional three-phasePFC rectifier without galvanic isolation (and filter capacitorsconnected to the dc output midpoint, i.e., the primary-side partof the converter depicted in Fig. 1), are subject to an inductorvoltage, vL, with nearly zero local average value, 〈vL〉 ≈ 0(angle brackets denote the average over one switching period),but large HF spectral components at the switching frequency(fs = 35 kHz) and multiples thereof. For the purpose of illus-tration, Fig. 2(a) depicts the instantaneous and local averagevalues of the voltage across the input inductor of phase a overone mains period for rated operation according to Tab. I andFig. 2(b) shows the corresponding spectrum. The proposedisolated converter topology is derived based on the idea thatthe input inductors are replaced by transformers in order totake advantage of the applied HF voltages. The secondary-side windings are connected to a second three-phase PFCrectifier, which, in combination with the transformers’ strayinductances Lσ, realizes a converter structure similar to athree-phase DAB converter. It is worth to note that Fig. 1illustrates only one possible realization of the D3AB PFCrectifier. Variations of this concept may only use differential orcommon mode voltage components for energy transfer and/oremploy different three-phase transformers, e.g., with delta-connected windings on the secondary side [12].
In this work, the corresponding power transistors at theconverter’s primary and secondary sides operate with sameduty cycles. For this reason,
va,b,c1
Vdc1=va,b,c2
Vdc2(1)
applies. The gate signals of the six corresponding primary-and secondary-side transistors are subject to a common phaseshift, ϕ, in order to facilitate output power control at dc port 2.
Based on the assumption that the capacitances of the splitdc-link are sufficiently large to achieve negligible fluctuationsof the dc-link capacitor voltages, the analysis can be confinedto the single-phase system with separated input inductor andHF transformer shown in Fig. 3. With this modification
f [Hz]10 k 30 k 100 k 300 k 1 M
1 k
100
10
1
100 m
V Lac
,aˆ
[V]
(b)
tTm/4 Tm/2 3Tm/4 Tm0
400
200
0
-200
-400
v Lac
,a [V
]
(a)
⟨vLa⟩ ≈ 0
vLa
⟨vLa⟩ ≈ 0
vLa
Fig. 2: (a) Instantaneous and local average values of the voltage across Lac;(b) spectrum of vLa (operating parameters according to Tab. I, fs = 35 kHz).
Lac LσCf1 Cf2
n = N1/N2
+
−
+
−
+
−
+ −vCf1i1 + −vCf2vhf1
+
−
vsw1+
−
vsw2+
−vhf2
+
−
+
−
+
−
vac
Vdc1——2
Vdc1——2
Vdc2——2
Vdc2——2
i2
dc port 1
dc port 2
Fig. 3: Single-phase system with input inductor Lac, primary- and secondary-side low-frequency blocking and filter capacitors Cf1 and Cf2, and HF trans-former.
a comprehensible description of the operating principle isfeasible and the derived results can be directly applied tothe three-phase converter of Fig. 1. The converter of Fig. 3has been documented with regard to dc–dc operation, forD1 = D2 = 0.5 [13] and arbitrary (but equal) duty cycles,0 < D = D1 = D2 < 1 [14]; its extension to a dc–dcconverter with a three-phase HF dc-link is investigated in [15].Section II-A revisits its main operating principles for dc–dcoperation in order to allow for a comprehensible extensionto ac–dc operation of single- and three-phase PFC rectifiersystems in Sections II-B and II-C, respectively.
A. Single-phase system at dc–dc operation
Fig. 4 illustrates voltage and current waveforms simulatedfor the single-phase converter system of Fig. 3 at a selectedoperating point. The ac input voltage, vac, changes slowlywith respect to the switching period, Ts, and can thus beconsidered as constant during one switching period. Theconverter features four degrees of freedom for the controlof the output power, i.e., switching frequency, fs, input- andoutput-side duty cycles D1 and D2, and phase shift angle, ϕ.
The filter capacitors Cf1 and Cf2 are blocking the dc volt-age components, VCf1 and VCf2, in order to avoid saturationof the transformer core. Thus, the HF voltages,
vhf1 = vsw1 − VCf1, (2)vhf2 = vsw2 + VCf2, (3)
400600
2000
-200-400-600
v hf [
V]
i 1 [A
]
0102030
-10-20-30
vhf1 n vhf2i1
0 Ts/4 Ts/2 3Ts/4 Ts
D2Ts/2 D2Ts/2D1Ts/2 D1Ts/2
φTs/(2)
Fig. 4: Definitions of D1, D2, and ϕ using simulated waveforms of vhf1,vhf2, and i1 over one switching period, Ts. Considered operating conditions:fs = 35 kHz, Lσ = 58µH, n = 2, vac(t) = 325V sin(t 2π50Hz), t =5ms, Vdc1 = 800V, Vdc2 = 400V, and ϕ = 22.
result at the HF transformer of the DAB, cf. Fig. 3. Theanalysis of the lossless converter is similar to the analysisof a conventional DAB converter. For D = D1 = D2, theexpression for the output power is
P1φ =nVdc1Vdc2
2fsLσ
ϕ
2π
(2D(1−D)− |ϕ|
2π
), (4)
which is found to be valid for|ϕ|2π
< min(D, 1−D). (5)
Fig. 5 evaluates (4) with respect to different duty cycles andphase shift angles. A close inspection of the curves in Fig. 5reveals that maximum power results for a phase shift angle thatmeets condition (5). For a given duty cycle, the expression
P1φ,max =nVdc1Vdc2ϕ
2P1φ,max
8π2fsLσ(6)
withϕP1φ,max = 2πD(1−D) (7)
applies for maximum power. As with all DAB converters, theinductor Lσ limits the maximum output power.
B. Single-phase system at ac–dc operation
The investigated system is operated with ac input voltage,vac(t) = Vm,pk sin (2πfmt) , (8)
cf. Fig. 6(a) and therefore, the above presented derivations fordc–dc operation need to be extended accordingly. For the sakeof brevity, basic sinusoidal modulation is considered, i.e., theinput and output stages apply a time-varying duty cycle,
D1 = D2 ≈1
2
(1 +
vac(t)
Vdc1/2
), (9)
in order to achieve a sinusoidal phase current with unity powerfactor.
Fig. 6(b) shows the calculated waveform of the primary-side current i1 over a mains period, for ϕ = 22 = constant.The filter capacitors Cf1 and Cf2 are blocking the low-frequency (LF) voltage components and with (1) and (9),
〈vCf1〉(t) =Vdc2
Vdc1〈vCf1〉(t) = vac(t) (10)
applies. For this reason, the HF transformer currents aresubject to LF offsets caused by superimposed LF capacitorcurrents,
ilf1 = Cf1d〈vCf1〉
dt, ilf2 = Cf2
d〈vCf2〉dt
, (11)
cf. Fig. 6(c). Thus, the analytical investigation for dc–dcoperation presented in Section II-A is extended with respectto the time varying duty cycle and the capacitor currents. The
P 1ϕ [
kW]
00 π / 2 3 π / 4π / 4 π
φ
2.5
5
7.5
10
D = 0.1, 0.9D = 0.2, 0.8
D = 0.3, 0.7
D = 0.5
D = 0.4, 0.6
Fig. 5: Average power over one switching period as a function of the phaseshift angle ϕ, for different values of D = D1 = D2, fs = 35 kHz, Lσ =58µH, n = 2, and dc voltages according to Tab. I. The thin black linedenotes the trajectory of maximum power and the dashed line denotes thedelimitation of the validity range of (4), according to (5).
respective analysis reveals that the superimposed LF capacitorcurrents have no impact on the current power level, for which
〈p1φ〉 = P1φ,dc + P1φ,ac,pk cos(4πfmt) (12)
P1φ,dc =nVdc1Vdc2
2fsLσ
ϕ
2π
[1
2−(Vm,pk
Vdc1
)2
− |ϕ|2π
], (13)
P1φ,ac,pk =nVdc1Vdc2
2fsLσ
ϕ
2π
(Vm,pk
Vdc1
)2
, (14)
is derived.
According to (12), (13), and (14) and for constant phaseshift angle ϕ,
|ϕ|π
=1
2−(Vm,pk
Vdc1
)2
−
√√√√(V 2dc1 − 2V 2
m,pk
)2
4V 4dc1
− 8fsLσP1φ,dc
nVdc1Vdc2,
(15)the local average of the instantaneous power of the single-phase PFC rectifier, 〈p1φ〉 is a sinusoidal function with twicethe mains frequency, amplitude P1φ,ac,pk, and dc offset P1φ,dc.In this regard, a detailed analysis reveals that power limitationrelevant for the design of Lσ occurs at the maximum valuesof |vac|, since the maximum possible output power decreasesconsiderably for duty cycles approaching 0 or 1, cf. Fig. 5.With this and expressions (6) and (7), the useful range for ϕis limited to
|ϕ|2π
<1
4−(Vm,pk
Vdc1
)2
(16)
and with (13), a condition for Lσ results,
Lσ <nVdc1Vdc2
8fsP1φ,dc
[1
4−(Vm,pk
Vdc1
)2]
. (17)
C. Three-phase system
It would be straight-forward to use three of the single-phase rectifiers given in Fig. 3 to realize an isolated three-phase PFC rectifier system. With dedicated input inductors,Lac, and DAB transformers, however, the resulting systemwould require increased total converter volume, since it wouldnot take advantage of the HF voltage applied to the inputinductors. For this reason, the remaining part of the papersolely considers the topology of Fig. 1. Nevertheless, theresults derived in Sections II-A and II-B directly apply, merelythe waveforms of the input currents, iLa,b,c, change, due tothe superposition of the currents through Lac and Lσ,
iLa,b,c = iLac,a,b,c − iLσ,a,b,c. (18)
Fig. 7 depicts characteristic waveforms obtained fromcircuit simulation using operating conditions and settings
0
Tm/4 Tm/2 3Tm/4 Tm0
t
-30
-100
102030
-20
i 1 [A
](a)
(b)
400600
2000
-200-400-600-800
v hf [
V]
(c)Tm / 4
vhf1 n vhf2
Tm / 2
Ts
Ts
t
t
i 1 [A
]
0102030
-10-20-30-40
ilf1
vac
i1
ilf1ilf1
ilf1
vhf1 nvhf2
i1i1
Fig. 6: Voltage and current waveforms determined for the single-phasesystem. (a) Sinusoidal input voltage over a mains period Tm. (b) Primary-side transformer current i1 over a mains period. (c) i1 and primary- andsecondary-side HF transformer voltages vhf1 and vhf2 over a switching periodTs at t = Tm/4 and t = Tm/2, respectively.
according to Tables I and III. According to Figs. 7(a) and (b),the three-phase voltages are phase shifted by 120 and theprimary- and secondary-side capacitor voltages are propor-tional, cf. (10). Fig. 7(c) illustrates the input currents, iLa,b,c,at rated power and reveals that, with the considered value ofLac, Zero Voltage Switching (ZVS) is partly lost at the primaryside.1 Detailed waveforms of the input currents at t = 0 andt = 5 ms are shown in Fig. 7(d) and clearly disclose thesuperposition of iLac,a and iLσ,a according to (18). Fig. 7(e)illustrates the time-varying output power levels of each phase,〈p1φa,b,c〉, which are sinusoidal and phase shifted by 120.For this reason, constant total power results,
Pout = 3P1φ,dc. (19)It is worth mentioning that the output power of each phaseis maximal at the zero crossing of the corresponding phasevoltage, which is due to D = 0.5, cf. (4). Furthermore,with the considered specifications and converter settings, theamplitude of the sinusoidal characteristic superimposed on〈p1φa,b,c〉 is less than its average value (1.6 kW < 2.7 kW).
III. OPTIMIZED CONVERTER DESIGN
In this Section, the investigated D3AB PFC rectifier isoptimized with regard to efficiency and power density; the op-timization objective is maximum power density at a converterefficiency of 98%. The implemented optimization procedureemploys analytical expressions to calculate the componentcurrents, which have been verified at different operating pointsusing a circuit simulator, revealing a high accordance witherrors of less than 2%. With known currents, the below listedcomponent models are evaluated with regard to losses andvolumes:
1Full ZVS requires a minimum current, which is indicated in Fig. 7(c) anddescribed in Section III-A.
t
t = 0 t = Tm/440200
-20-40(d)
tTm/4 Tm/2 3Tm/4 Tm00
8.0
6.0
4.0
2.0
P [k
W]
(e)
Pout
t
Tm/4 Tm/2 3Tm/4 Tm0
400200
0-200-400
v [V
]
(b)
t
Tm/4 Tm/2 3Tm/4 Tm0
400200
0-200-400
v [V
]
(a)
va1 vb1 vc1
Ts Ts
i La [A
]
t
Tm/4 Tm/2 3Tm/4 Tm0
40
20
0
-20
-40
i [A
]
(c)
iLa iLb iLc
⟨iLa⟩ ⟨iLb⟩ ⟨iLc⟩⟨iLa⟩ ⟨iLb⟩ ⟨iLc⟩
iLa iLb iLc
ZVS ZVSno ZVSnoZVS
noZVSZVS ZVSno ZVS
noZVS
noZVS
⟨p1φ,a⟩ ⟨p1φ,c⟩ ⟨p1φ,b⟩
va2 vb2 vc2
Fig. 7: Simulation results for the operating conditions and settings accordingto Tables I and III: (a) primary-side capacitor voltages; (b) secondary-sidecapacitor voltages; (c) input currents (= primary-side transformer currents;cf. Fig. 1); (d) magnified input current of phase a during 0 < t < Ts and5ms < t < 5ms+Ts, revealing the input current of the PFC rectifier (withcurrent ripple) and the superimposed HF DAB transformer current, whichshows a deviation from the ideal shape that originates from the series resonantcircuit formed with Lσ and the filter capacitors Cf1 and Cf2; (e) local averagevalues of the instantaneous power levels of each phase and total output power.
• Semiconductors and cooling system in Section III-A,• Magnetic components in Section III-B,• Capacitors in Section III-C,• EMI filter, gate drivers, and control in Section III-D.
A fully generalized converter optimization would featurea great number of open design parameters. Due to given spec-ifications, known converter characteristics, and/or availablecomponents, however, a great number of design parameterscan be readily defined. In this regard, Vdc1 is set to 800 Vin order to feature reasonable duty cycles with sufficientmargins to 0 and 1, cf. (9), and still enable the use ofpower semiconductors with a blocking voltage of 1200 V.
Furthermore, it is known that DAB converters achieve mostefficient operation for Vdc1/(nVdc2) ≈ 1. Thus, with regard tothe specified output voltage, Vdc2 = 400 V, the turns ratio isset to n = N1/N2 = 2. Furthermore, (17) limits the maximumvalue of Lσ for given output power. The considered converterinductance is set to 80% of the maximum value,
fsLσ = 80% (fsLσ)max = 80%nVdc1Vdc2
8P/3
[1
4−(Vm,pk
Vdc1
)2]
,
to ensure controllability of the converter.
A. Semiconductors and cooling system
SiC power MOSFETs are used on the primary and sec-ondary sides in order to take advantage of their low conductionand switching losses. Initial calculations of semiconductorlosses reveal that low conduction and switching losses areachievable if single 25 mΩ/1200 V-devices (C2M0025120Dby Cree) and 10 mΩ/900 V-devices (C3M0010090K by Cree)realize each switch on the primary and secondary sides,respectively. Using devices with increased on-state resistanceswould be possible with regard to the devices’ rated currentsand losses, however, reduced efficiencies would result. Con-versely, the use of multiple MOSFETs connected in parallelwould attain only limited improvements that may not justifythe increased effort.2
The conduction losses are calculated based on the devices’on-state resistances at junction temperatures of 125C,
The calculation of the switching losses is based on mea-sured switching losses for the considered devices from [16],[17] and depicted in Fig. 8. The considered polynomials are
Esw =
233µJ− 15.1 µJA ID + 281 nJ
A2 I2D ∀ ID ≤ 0.53 A,
12µJ + 212µJ(
2.3 A−ID1.77 A
)2 ∀ 0.53 A < ID < 2.3 A,17.1µJ− 2.53 µJ
A ID + 136 nJA2 I
2D ∀ ID ≥ 2.3 A.
(20)for the 25 mΩ/1200 V-device, for operation with 800 V andTj = 125C and
Esw =
164µJ− 4.48 µJA ID + 2.85 nJ
A2 I2D ∀ I ≤ 1.2 A,
3.4µJ + 155µJ(
2.8 A−ID1.6 A
)2 ∀ 1.2 A < I < 2.8 A,964 nJ + 837 nJ
A ID + 10.1 nJA2 I
2D ∀ I ≥ 4.5 A.
(21)for the 10 mΩ/900 V-device (VDS = 400 V, Tj = 70C).Negative values of the instantaneous drain current duringswitching, ID, denote switching operations where ZVS cannotbe attained, i.e. turn-on losses occur, and ID > 0 denoteswitching operations where ZVS is in principle feasible.However, a minimum current is required for ZVS to fullycharge and discharge the MOSFET’s output capacitances. Inthis regard, the second polynomials in (20) and (21) representpartial ZVS that are approximated based on quadratic inter-polations for a dead time interval of 200 ns. Remark: sincethe MOSFETs are used without external capacitors increasingCoss, the very low loss property of ZVS is lost at high positivecurrents, due to turn-off losses (approximately at ID > 20 Ain Fig. 8).
2Even increased switching losses would result on the primary side, dueto time intervals where turn-on losses occur, cf. Fig. 7. As a result, optimaldesigns would employ increased current ripples.
-40 -20 0 20 40 60
0.40.30.20.10.0
(b)
ID
0.6
0.4
0.2
0.0
E sw [m
J]
(a)
ID
-20 -10 0 IZVS,min 10 20 30
E sw [m
J]
≈ ZVS range EoffEon
Fig. 8: (a) Switching losses of the 25mΩ/1200V SiC MOSFETC2M0025120D for operation with 800V and Tj = 125C and (b) the10mΩ/900V SiC MOSFET C3M0010090K for operation with 400V andTj = 70C, with respect to the drain current, ID, at the switching instant. BothFigures depict measured results from [16], [17] for ID < 0 and ID > IZVS,min.For 0 ≤ ID ≤ IZVS,min the switching losses for partial ZVS are interpolatedfor an assumed dead time interval of 200 ns.
TABLE II: Expressions used for scaling all lengths, areas, and volumesof the considered magnetic components (based on two stacked E 55/28/21cores).
Core volume Vc = 435× 10−3Vbox
Core cross section Ac = 206× 10−3V2/3
box
Available winding cross section of coil former Aw = 95.2× 10−3V2/3
box
Height of core window hw = 158× 10−3V1/3
box
Width of core window Aw = 631× 10−3V1/3
box
Average turn length lavg = 2.64V1/3
box
Open surface to ambient Aopen = 5.51V2/3
box
The volume of the cooling system for power semiconduc-tors with total losses of Psemi,total is considered by means of aCooling System Performance Index (thermal conductance pervolume), CSPI , of 13 W
dm3 K and a considered temperaturedifference between heat sink and ambient of ∆Ths–a = 50C,
Vcooling system =Psemi,total
∆Ths–a × CSPI. (22)
B. Magnetic components
This paper uses a unified scaled model for all magneticcomponents. The scaled model is parameterized accordingto the geometrical properties of the transformers realizedin [8], which are compose of two stacked E 55/28/21 cores(boxed volume, Vbox, is 200 cm3) and achieve efficiencies of99.6% for an isolated three-phase PFC rectifier with a ratedpower of 7.5 kW. For a given value of Vbox, all lengths,areas, and volumes of the magnetic component are determinedaccording to the expressions listed in Tab. II. The inputinductors/transformers of the D3AB PFC rectifier and theDAB converter inductors, Lσ, are considered separately inorder to take the additional volumes and losses due to Lσ
into account.
The employed component model calculates the corelosses with the improved Generalized Steinmetz Equation(iGSE) [18] and the Steinmetz parameters
k = 1.02, α = 1.4745, and β = 2.6607 (23)for the considered N95 ferrite core material (extracted forf = 25 kHz, Bpk = 300 mT, and Tc = 80C with a softwaretool provided by TDK/EPCOS [19]). The copper losses are
determined using simplified expressions for HF skin- andproximity effects derived in [20], which assume a distributedair gap. The computation of the copper losses considers thefirst 30 harmonic components of each conductor current; theconductors employ HF litz wires with single strand diametersof 0.1 mm.
The automated design procedure further takes an effectivecopper area of 38%×Aw (Aw is the cross section of the corewindow, cf. Tab. II), a copper temperature of 100C, a max-imum flux density of 300 mT, and a maximum temperaturerise of the component’s surface of 50C into account. Thesurface temperature rise is approximated according to [21],
∆T =
(P/1 mW
Aopen/1 cm2
) 11.1
× 1C < 60C. (24)
In a first step, the design procedure scans a wide rangeof values for Vbox in order to determine a boxed volume thatleads to a design close to the thermal limitation, Vbox,0. For thispurpose, geometric sequences are used for Vbox with commonratios of 0.5 (initial coarse scan starting from Vbox = 10 dm3)and 1.1 (subsequent fine scan). For each given value ofVbox an inner loop determines the optimal number of turnswith respect to minimum total losses. In case of the inputinductors/transformers, the available cross section of the corewindow is divided to the windings of primary and secondarysides such that same current densities result. Finally, the airgap length is determined to achieve the specified inductance.
Losses of magnetic components decrease with increasingvolume. For this reason, the copper and core losses arecalculated for further 29 magnetic components with increasingboxed volumes according to
Vbox,i = Vbox,0 × 1.1i ∀ i ∈ 1, 2, 3, . . . 29 (25)and for optimized numbers of turns. The resulting volumes,losses, and design configurations (e.g. numbers of turns)are stored and the data transferred to the main converteroptimization procedure.
C. Capacitors
The capacitors of the considered converter are subject torelatively high currents. In order to still achieve high powerdensity, ceramic and film capacitors have been selected, whichare listed below:
• Cf1: 1×B32754C2106K000 (film capacitor, 10µF,250 Vac, 12 A, EPCOS),
• Cf2: 25×KR355WD72W125MH01 (ceramic cap.,0.85µF at 163 V, 450 Vdc, ≈ 2 A at 50 kHz, Murata),
• Cdc2: 1×CeraLinkTM SP500 (same as Cdc1; note: capac-itance drops to 8.4µF at 200 V).
The total volume of all capacitors is 160 cm3, which includesan additional volume of 30 cm3 for damping networks, anelectrolytic output capacitor (120µF, 450 Vdc), and two SMDinductors that decouple the electrolytic capacitor from theCeraLinkTM capacitors (Cdc2). The final design suggested byoptimization has been successfully tested with comprehensivecircuit simulation, using the above capacitance values, reveal-ing only minor differences in terms of rms values and losses(conduction, switching, and core). It is worth to note that theoptimization does not consider capacitor losses, due to theircomparably low contribution to the total losses.
D. Remaining components
The volumes and losses of EMI filter, gate drivers, andcontrol have been adopted from [22], due to similar specifi-cations and optimization objectives:
Vi, (30)i.e., 15% of the volume is considered to be unused.
E. Optimization
Based on the above considerations and assumptions, it isfound that the switching frequency, fs, the input current ripple,
r =∆ILac,pkpk
2P3Vm,pk
=∆ILac,pkpk
Im,pk, (31)
and the considered boxed volumes of the magnetic compo-nents remain for optimization of efficiency and power density.The considered settings are defined with
150, 175, 200, 225, 250, 275, 300%, (33)where the listed switching frequencies are preselected withregard to small volume EMI filters (cf. Fig. 12 in [23]).The sets defined for fs and r lead to 72 different settings.Furthermore, 900 combinations of different designs result forthe input inductors/transformers and the DAB inductors (30for each, cf. Section III-B) for given values of fs and r, which,in total, yields 64800 results. Fig. 9 depicts the correspondingresults and discloses the η-ρ Pareto front for the investigatedconverter system.
The orange star in Fig. 9 marks the selected operatingpoint, which achieves η = 98.1% and ρ = 4 kW/dm3 atfs = 35 kHz, r = 175%, and for magnetic componentswith maximum power density, i.e., operated at their thermallimitation. The resulting Pareto-optimal design points revealincreasing efficiency for decreasing power density, which isdirectly related to the similar η-ρ characteristics of magneticcomponents. From a detailed inspection of the design pointson the Pareto front it becomes apparent that design pointswith Pareto-optimal power density and very high efficiencyare obtained for reduced switching frequencies (switchinglosses, core losses) and reduced current ripples (rms currents,conduction and copper losses, core losses; reduced switchingfrequencies overcompensate the increases of switching lossesby reason of reduced current ripples).
The red triangles in Fig. 9 mark results with constantswitching frequency of 35 kHz, magnetic components withmaximum power densities, and different values of r. It canbe observed that reduced power densities and efficienciesresult for r < 175%. The reduced power densities are mainlyaddressed to increased boxed volumes of the PFC inputinductors and the reduced efficiencies originate from both,the PFC input inductors due to the required increased energystorage capability and the semiconductors on the primary side,which generate increased switching losses due to an increaseof the region where ZVS is lost, cf. Fig. 7. Slightly reducedconverter volumes are feasible for r > 175%, however, theefficiency quickly decreases by reason of large rms currents.
η [%
]
98.0
98.2
98.6
98.4
r = 75%
r = 275%
r = 175%fs = 23 kHz
fs ≤ 35 kHz
fs = 47 kHz
fs ≤ 27 kHz
fs ≤ 23 kHz
2.0 3.02.5 3.5ρ [kW/dm3]
4.0
r ≤ 150% r ≤ 175% r ≤ 200%
Fig. 9: Efficiencies, power densities, and η-ρ Pareto front determined for theD3AB PFC rectifier.
The cyan circles mark results with constant current rippleof 175%, magnetic components with maximum power densi-ties, and different switching frequencies. It can be seen thata considerably reduced switching frequency of 23 kHz stillfacilitates a relatively high power density of 3.6 kW/dm3.In this regard it is found that Pareto-optimal designs withvery high efficiencies not only require reduced switchingfrequencies and power densities but also magnetic componentswith increased boxed volumes.
IV. DISCUSSION OF DESIGN RESULT
Tab. III lists the design results at the selected operatingpoint identified in Fig. 9 and Figs. 10(a) and (b) depict thecorresponding component losses and volumes, respectively.According to Fig. 10(a), more than half of the total lossesare attributed to the semiconductor losses which are mainlygenerated in the power MOSFETs on the primary side. Areduction of the primary-side conduction losses could beachieved by increasing the corresponding chip sizes, which,however, would increase the switching losses. The magneticcomponents generate one third of the losses; here, lossesmainly occur in the windings of the input inductors, whichare already operated with maximum flux densities of 300 mT,i.e., a further increase of the core losses is not feasible.
Approximately two thirds of the converter volume arerequired for passive components (magnetics, capacitors, EMIfilter). Due to comparably low semiconductor losses (84 Wat rated power), a cooling system with a comparably smallvolume can be employed, e.g., using double-sided cooling asmall fan with an edge length of 30 mm, which is found toenable the realization of a cooling system with the calculatedlow volume of 130 cm3 and still provides a sufficiently largebase plates to accomodate all 12 MOSFETs.
Fig. 11(a) and (b) depict the calculated characterists ofefficiency and selected components’ losses with respect tothe output power and reveal that η > 98% is feasible forPout > 2.3 kW. According to Fig. 11(b), substantial conduc-tion losses and losses in the magnetic components remain atvery low power, due to the inductor current ripples. However,increasing switching losses are observed for decreasing outputpower and Pout < 2 kW. A close investigation reveals that thecurrents during switching of the secondary-side MOSFETs areinsufficient for ZVS, cf. Fig. 12(a) and Fig. 8(b). ZVS could
(a)
(b)
3×PLσ,wdg(7 W)
3×PLac,wdg(32 W)
3×PLσ,core(5 W)
3×PLac,core(8 W) Psw,sec
(6 W)Pcond,sec(14 W)
Pcond,prim(34 W)
gate drivers,control, fan(12 W)
gate drivers,control(0.3 dm3)
coolingsystem(0.13 dm3)
EMI filter(0.35 dm3)unused(0.26 dm3)
3×Lσ(0.12 dm3)
3×Lac(0.67 dm3)
capacitors(0.16 dm3)
EMI filter(5 W)
Psw,prim(31 W)
Fig. 10: (a) Component losses and (b) volumes for the selected design pointwith η = 98.1% and ρ = 4kW/dm3.
2.0 4.0 6.0 8.01.0 3.0 5.0 7.00
5040302010
60
P los
s [W
]
Pout [kW](b)
Pcond
Pmag
Psw|n=2Psw|n=2.1
2.0 4.0 6.0 8.01.0 3.0 5.0 7.095
99989796
100η
[%]
Pout [kW](a)
0.0
0.0
n = 2.1
n = 2.0
Fig. 11: (a) Total converter efficiency and (b) characteristics of selectedcomponents’ losses with respect to output power.
be attained if three inductors would be placed in parallel tothe three transformers’ secondary windings. According to theresults of an analytical investigation of the equivalent circuitof a transformer, however, the same effect can be achievedfor a slight adjustment of the transformers’ turns ratios, fromn = 2 to n = 2.1, cf. Fig. 12(b). With this minor adjustment,a substantial efficiency improvement is achieved at low outputpower levels, i.e., η > 98% for Pout > 1.7 kW.
V. CONCLUSION
This paper proposes and analyzes a novel three-level andthree-port isolated and bidirectional PFC rectifier topology(D3AB PFC rectifier), which can be realized with standard 6-pack power modules on the primary and secondary sides, em-ploys integrated input inductors and HF transformers, and/orfeatures galvanic isolation and high efficiency. The givenin-depth description of the working principle of the D3ABPFC rectifier allows the derivation of key expressions needed
TABLE III: Summary of results for the selected converter design, cf. Fig. 9.
General results and rms currentsSwitching frequency fs = 35 kHz
Current ripple r = 175%
Calculated efficiency at rated load η = 98.1%
Calculated total power density ρ = 4 kW/dm3
Transformer rms current, prim. and sec. sides Itr1,2 = 17.2 A, 19.2 AMOSFET rms currents,prim. and sec. sides IT,prim,sec = 12.2 A, 13.6 AMagnetic input inductor/transformer Lac
Inductance Lac = 195µH
Boxed volume Vbox = 223 cm3
Number of turns, prim. and sec. sides N1,2 = 20, 10Air gap length lair = 1.9 mm
Conductors, prim. and sec. sides (HF litz wires) 547, 610 × 0.1 mm
Copper losses Pw = 10.6 W
Core losses Pc = 2.5 W
Calculated temperature rise ∆T = 44CDAB inductor Lσ/n
2 (placed on the secondary side)Inductance Lσ = 14.5µH
Boxed volume Vbox = 41 cm3
Number of turns N = 9
Air gap length lair = 1.7 mm
Conductor: HF litz wire 610× 0.1 mm
Copper losses Pw = 2.4 W
Core losses Pc = 1.8 W
Calculated temperature rise ∆T = 44C
t
t0
420
-2-4
(a)
i 2 [A
]
t0+Ts t0+2Ts t0
420
-2-4
(b)t0+Ts t0+2Ts
ZVSpartial ZVS
partial ZVS ZVS
Fig. 12: Calculated current at the transformer’s secondary side for Pout =500W, t0 = 2.5ms, operating conditions and parameters according to Tab. Iand Tab. III, and different turns ratios: (a) n = 2, (b) n = 2.1.
to design the converter system with respect to optimizedperformance values, e.g. efficiency and power density, whichserves as a basis for the converter optimization presented inthe second part of this paper. According to the calculatedresults, a full-load efficiency of 98.1% and a power den-sity of 4 kW/dm3 can be achieved for the PFC rectifier ifSiC MOSFETs are used (25 mΩ/1200 V and 10 mΩ/900 Vdevices on primary and secondary sides, respectively). Thepresented design is found to achieve efficiencies greater than98 % for Pout > 1.7 kW.
The discussions given in this paper are confined to thebasic structure, operating behavior, and design of the newtopology. Further research will focus on the investigationof prospective efficiency and/or power density improvementsthat can be achieved with modified topologies and alternativecontrol schemes that take advantage of currently unuseddegrees of freedom of the considered converter system. Cor-responding examples include realizations where only CM orDM components are utilized for energy transfer and alternativecontrol schemes with non-constant values of the phase shiftand different duty cycles, D1 6= D2.
REFERENCES
[1] S. Pannala, N. Padhy, and P. Agarwal, “Peak Energy Managementusing Renewable Integrated DC Microgrid,” IEEE Trans. Smart Grid,accepted for future publication, 12 pages.
[2] C. Nelson. Multi-Axis Drive Applications Using Common DC Bus.Accessed: March 9, 2018. [Online]. Available:
https://www.industry.usa.siemens.com/drives/us/en/electric-drives/ac-drives/ac-drives-apps/multi-axis-common-dc-bus/Documents/Common DC bus paper.pdf
[3] R. Razi, B. Asaei, and M. R. Nikzad, “A new battery charger for plug-in hybrid electric vehicle application using back to back converter ina utility connected micro-grid,” in Proc. IEEE Power Electron., DriveSys. & Tech. Conf. (PEDSTC), Mashhad, Iran, 14–16 Feb. 2017, pp.13–18.
[4] R. Yamada, Y. Nemoto, S. Fujita, and Q. Wang, “A Battery Chargerwith 3-Phase 3-Level T-type PFC,” in Proc. IEEE Int. Telecom. EnergyConf. (INTELEC), Osaka, Japan, 18–22 Oct. 2015, 5 pages.
[5] S. Madhusoodhanan, A. Tripathi, K. Mainali, A. Kadavelugu, D. Patel,S. Bhattacharya, and K. Hatua, “Three-Phase 4.16 kV Medium VoltageGrid Tied AC-DC Converter Based on 15 kV/40 A SiC IGBTs,” inProc. IEEE Energy Convers. Congr. and Expo. (ECCE USA), Montreal,QC, 20–24 Sept. 2015, pp. 6675–6682.
[6] M. Kumar, L. Huber, M. M. Jovanovic, D. Ping, and G. Liu, “Analysis,Design, and Evaluation of Three-Phase Three-Wire Isolated AC-DCConverter Implemented with Three Single-Phase Converter Modules,”in Proc. IEEE Applied Power Electron. Conf. and Expo. (APEC), LongBeach, CA, 20–24 March 2016, pp. 38–45.
[7] M. Silva, N. Hensgens, J. Oliver, P. Alou, O. Garcıa, and J. A.Cobos, “Isolated Swiss-Forward Three-Phase Rectifier for AircraftApplications,” in Proc. IEEE Applied Power Electron. Conf. and Expo.(APEC), Fort Worth, TX, 16–20 March 2014, pp. 951–958.
[8] L. Schrittwieser, P. Cortes, L. Fassler, D. Bortis, and J. W. Kolar,“Modulation and Control of a Three-Phase Phase-Modular IsolatedMatrix-Type PFC Rectifier,” IEEE Trans. Power Electron., vol. 33,no. 6, pp. 4703–4715, June 2018.
[9] A. K. Singh, P. Das, and S. K. Panda, “A Novel Matrix Based IsolatedThree Phase AC-DC Converter with Reduced Switching Losses,”in Proc. IEEE Applied Power Electron. Conf. and Expo. (APEC),Charlotte, NC, 15–19 March 2015, pp. 1875–1880.
[10] Z. Zhang, A. Mallik, and A. Khaligh, “A High Step-Down IsolatedThree-Phase AC-DC Converter,” IEEE Trans. Emerg. Sel. Topics PowerElectron., vol. 6, no. 1, pp. 129–139, March 2018.
[11] D. S. Oliveira and B. R. de Almeida, “A Bidirectional Single-StageThree-Phase AC / DC Converter with High-Frequency Isolation andPFC,” in Proc. Int. Power Electron. Conf. (PCIM Europe), Nuremberg,Germany, 19–21 May 2015, pp. 1122–1129.
[12] J. Jacobs, M. Thommes, and R. De Doncker, “A Transformer Com-parison for Three-Phase Single Active Bridges,” in Proc. Europ. Conf.Power Electron. Appl. (EPE), Dresden, Germany, 11–14 Sept. 2005,10 pages.
[13] F. Z. Peng, H. Li, G.-J. Su, and J. S. Lawler, “A new ZVS bidirectionalDC-DC Converter for Fuel Cell and Battery Application,” IEEE Trans.Power Electron., vol. 19, no. 1, pp. 54–65, Jan. 2004.
[14] H. Li, F. Z. Peng, and J. S. Lawler, “A Natural ZVS Medium-PowerBidirectional DC-DC Converter with Minimum Number of Devices,”IEEE Trans. Ind. Appl., vol. 39, no. 2, pp. 525–535, March 2003.
[15] Z. Wang and H. Li, “A Soft Switching Three-phase Current-fedBidirectional DC-DC Converter with High Efficiency over a Wide InputVoltage Range,” IEEE Trans. Power Electron., vol. 27, no. 2, pp. 669–684, Feb. 2012.
[16] J. Azurza Anderson, C. Gammeter, L. Schrittwieser, and J. W. Kolar,“Accurate Calorimetric Switching Loss Measurement for 900 V 10 mΩSiC MOSFETs,” IEEE Trans. Power Electron., vol. 32, no. 12, pp.8963–8968, Dec. 2017.
[17] J. Azurza Anderson, L. Schrittwieser, C. Gammeter, G. Deboy, andJ. W. Kolar, “Relating the Figure of Merit of Power MOSFETs to theMaximally Achievable Efficiency of Converters,” under review for theCPSS Trans. on Power Electron. and Appl.
[18] K. Venkatachalam, C. R. Sullivan, T. Abdallah, and H. Tacca, “AccuratePrediction of Ferrite Core Loss with Nonsinusoidal Waveforms usingonly Steinmetz Parameters,” in Proc. IEEE Workshop Comput. PowerElectron., Mayaguez, Puerto Rico, 3–4 June 2002, pp. 36–41.
[20] M. Leibl, “Three-Phase PFC Rectifier and High-Voltage Generator forX-Ray Systems,” Ph.D. dissertation, ETH Zurich, 2017.
[21] A. Van den Bossche and V. C. Valchev, Inductors and transformers forpower electronics. New York: Taylor & Francis, 2005.
[22] L. Schrittwieser, M. Leibl, M. Haider, F. Thony, J. W. Kolar, andT. B. Soeiro, “99.3% Efficient Three-Phase Buck-Type All-SiC SWISSRectifier for DC Distribution Systems,” IEEE Trans. Power Electron.,accepted for future publication, 15 pages.
[23] J. W. Kolar, F. Krismer, Y. Lobsiger, J. Muhlethaler, T. Nussbaumer,and J. Minibock, “Extreme Efficiency Power Electronics,” in Proc. Int.Conf. Integr. Power Electron. Sys. (CIPS), Nuremberg, Germany, 6–8 March 2012, 22 pages.
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