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November 23, 2005 Egor Bondarev, Michel Chaudron, Peter de With
Scenario-based PA Method for Dynamic Component-Based Systems
Egor Bondarev, Michel Chaudron, Peter de [email protected]
Eindhoven University of Technology, The Netherlands
November 23, 2005 Egor Bondarev, Michel Chaudron, Peter de With
Problem Statement
- To accurately predict the performance attributes
- of software component-based systems
- built on multiprocessor architectures
Performance attributes• Timing behaviour, • Processor usage, • Memory consumption, • Bus load
November 23, 2005 Egor Bondarev, Michel Chaudron, Peter de With
Example Problem: Car Navigation System (CNS)
Software Logical View
Map DBLegend:
MMI
NAV
RAD
-- software component
-- provides and requires interfaces
-- terrestrial antenna
-- outside communication
-- component binding
Graphicalscreen
November 23, 2005 Egor Bondarev, Michel Chaudron, Peter de With
CNS: Architectural Alternatives
72 kbps
Architecture A
72 kbps
Architecture B57 kbps
72 kbps
Architecture C
72 kbps
Architecture D Arc
hit
ectu
re E
22 MIPS
MMI_Inst
113 MIPS 11 MIPS
260 MIPS
22 MIPS
113 MIPS
22 MIPS 113 MIPS
260 MIPS
NAV_Inst RAD_Inst
MMI_Inst
NAV_Inst
11 MIPS
RAD_Inst
NAV_Inst
RAD_Inst
MMI_Inst NAV_Inst
130 MIPS
MMI_Inst
RAD_Inst
MMI_Inst
RAD_Inst
NAV_Inst
B)
1. Predict performance for every alternative
2. Find optimal alternatives in terms of:Resource usage+ Performance + Robustness + …
November 23, 2005 Egor Bondarev, Michel Chaudron, Peter de With
Proposed Solution
1. Models for both software- and hardware components.
2. Scenarios-based evaluation• The designer can focus on critical run-time configurations.
• Allows trade-off between modeling effort and accuracy.
3. Simulation of scenarios + schedulability analysis
Based on the following concepts
November 23, 2005 Egor Bondarev, Michel Chaudron, Peter de With
Performance Prediction Approach (2/2)
Repository
Communication HWComponents
Memory and Storage HWComponents
Processing HW Components
Software Components
Input
Applicationrequirements
Design (assemble)
Real-timeapplication
Models
Component Resource model
Component Resource model
Component Behaviour model
Component Behaviour model
has
has
Compile models /reconstruct tasks
Executionarchitecture (tasks)
Simulate taskexecution
Task executiontimeline
Validate
Real-time and performanceproperties
Analyze
predicted for
ConstructApplication
Scenario modelApplication
Scenario model
!!!
Real-time awarecomponents
Real-time awarecomponents
Select
Repository
Communication HWComponents
Memory and Storage HWComponents
Processing HW Components
Software Components
November 23, 2005 Egor Bondarev, Michel Chaudron, Peter de With
Behaviour and Resource ModelsBehavourModel_MPEG4Decoder_Component
behaviour
operation IDecode.decodeFrame()
calls IBufferAccess.getElement()
passedBits = 0
returnedBits = 1024
synchronous = TRUE
numberOfIterations = 1
calls IBufferAccess.storeElement()
passedBits = 1024
returnedBits = 1
synchronous = TRUE
numberOfIterations = 1
BehavourModel_MPEG4Decoder_Component
behaviour
operation IDecode.decodeFrame()
calls IBufferAccess.getElement()
passedBits = 0
returnedBits = 1024
synchronous = TRUE
numberOfIterations = 1
calls IBufferAccess.storeElement()
passedBits = 1024
returnedBits = 1
synchronous = TRUE
numberOfIterations = 1
ResourceModel_MPEG4Decoder_Component
resource use
operation IDecode.decodeFrame()
cpu claim
max = 1E7 cycles (reference processor)
aver = 1E5 cycles (reference processor)
min = 1E4 cycles (reference processor)
mem claim = 10 KB
mem release = 3 KB
ResourceModel_MPEG4Decoder_Component
resource use
operation IDecode.decodeFrame()
cpu claim
max = 1E7 cycles (reference processor)
aver = 1E5 cycles (reference processor)
min = 1E4 cycles (reference processor)
mem claim = 10 KB
mem release = 3 KB
IDecode IBufferAccess
decodeFrame()
getElement()
storeElement()
November 23, 2005 Egor Bondarev, Michel Chaudron, Peter de With
Composition of Software Components
MMI NAV RAD
IGUIControl IParameters
IDatabase
IDatabase
ITMC
IGUIControl IParameters
IReceiver
ITMC
setVolume()
setAddress()
updateScreen()
addressLookup()
decodeTMC()
adjustVolume()
receiveTMC()
IDatabase
IGUIControl
MMI_Inst
RAD_Inst
NAV_Inst
November 23, 2005 Egor Bondarev, Michel Chaudron, Peter de With
Composition of Hardware Components
130 MIPS core-CAN bus
* *
22 MIPS core
RAM
**
ReliabilityModels
Cost ModelsPerformance
Models...
130 MIPS core-CAN bus
* *
22 MIPS core
RAM
**
ReliabilityModels
Cost ModelsPerformance
Models...
1. Performance model specifies IP processing capabilities. For processing core frequency rate and scheduling policy; For memory a memory size and addressing type; For bus bit-size, frequency and arbitration policy
130 MIPS core-CAN bus
* *
22 MIPS core
RAM
**
ReliabilityModels
Cost ModelsPerformance
Models...
November 23, 2005 Egor Bondarev, Michel Chaudron, Peter de With
SW / HW Mapping
System architecture
SW architecture
IDatabase
IGUIControl
MMI_Inst
RAD_Inst
NAV_Inst
HW architecture
130 MIPS core-CAN bus
* *
22 MIPS core
RAM
**
Mapping
November 23, 2005 Egor Bondarev, Michel Chaudron, Peter de With
Application Scenario ModellingA scenario model defines
• environmental events or system interrupts
• application level stimuli (task triggers)
for a specific hw/sw-configuration (composition structure)
IDatabaseIGUIControl MMI_Inst
RAD_Inst
NAV_Inst
VolumeStimulus
triggersIGUIControl.setVolume()
period = 31 msdeadline = 200 ms
November 23, 2005 Egor Bondarev, Michel Chaudron, Peter de With
The generated task specifies sequence of constituent method invocations period, deadline, priority, synchronization constraints
Composing the Models
Service_A Service_B
Operation_B
Operation_C
Service_C Service_D
Operation_D
Operation_F
Service_F
Operation_E
Operation_E
Operation_E
Task Trigger(period 40 ms)
Operation_A
TaskTrigger invoke InterfaceX.OperationA period 40 ms offset 0 ms deadline 40 ms
Application ScenarioModel:
Component ResourceModel:
Operation_E CPU claim = 3ms
30 ms
Component BehaviorModel:
OperationA() callsInterfaceZ.OperationB()
InterfaceY.OperationC()nmbIterations = 1
nmbIterations = 1
November 23, 2005 Egor Bondarev, Michel Chaudron, Peter de With
Scenario Simulation + Analysis
Task instancetriggering
Task instancecompletion
Task instancedeadline
CPU is idle
Simulation time
Simulation time
Me
m lo
ad
Simulation time
Bu
s lo
ad
Simulation or Schedulability analysis are performed with scheduling algorithms deployed on the target OS (RMA, EDF, CBS)
Simulation results in task latencies, number of missed deadlines, CPU, memory and bus utilization
November 23, 2005 Egor Bondarev, Michel Chaudron, Peter de With
Not mentioned Facilities and Benefits Modelling of parameter-dependent behaviour and
resource usage
Multiple-platform resource models
Task synchronization aspects can be modeled
Component mapping on multiprocessor architecture
Multidimensional design space exploration• robusteness vs cost, memory_load vs cpu_load, etc
November 23, 2005 Egor Bondarev, Michel Chaudron, Peter de With
Framework Deployment Issues We have developed a tool chain supporting the design activities
We have validated the prediction approach by MPEG4 Decoder case study:• prediction accuracy of task latencies is > 90%
RTIE Graphical ComposerR
TIE
Ta
sk G
en
era
tor
RTIE Reporter
Real-Time PredictionFramework