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Performance-Optimal Clustering with Retiming

for Sequential Circuits

Tzu-Chieh Tien and Youn-Long Lin

Department of Computer Science

National Tsing Hua University

Hsin-Chu, Taiwan, R.O.C.

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Outline

IntroductionPrevious WorkProposed ApproachExperimental ResultsConclusion and Future Research

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Retiming

critical path delay = 8

retiming

critical path delay = 7

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Performance-Driven Clustering

Minimize clock period under cluster-size constraint

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Combining Clustering and Retiming

critical path delay = 7critical path delay = 8

inter-cluster delay = 2

clusteringw/o retiming consideration

clusteringw/ retiming

consideration

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Problem Definition

Given a sequential circuit G,a target clock period c, and an area-bound number M

Find a clustered/retimed/node-replicated circuit Gr

clock period less than or equal to ceach cluster is of size M or less

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Previous Work

P. Pan, A. K. Karandikar, and C. L. Liu, “Optimal Clock Period Clustering for Sequential Circuits with Retiming,” IEEE T-CAD, June 1998.

Optimal under the unit gate delay modelNear-optimal for the general gate delay model

J. Cong, H. Li, and C. Wu, “Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization,” DAC’99.

100X more efficient but still near-optimal

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This Work

Optimal for the general gate delay model

More (2X) efficient than Pan’s approach

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Pan’s Approach

Label each node v an l-value, l(v)Find a clustered-retimed circuit such

that all PO’s l-values less than or equal to c

Retiming solutionResulting clock period less than c +

max. gate delay

1/)()( cvlvr

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Pan’s l-value of a Node

Total w1 edge weight of the longest path from PI’s to the node

w1 weight of edge e from u to v: w1(e) = - c * w(e) + d(v)

w(e): number of FF’s along e

w1(e) 2 - 1 3 0l(v) 0 2 1 4 4 < 6

target c = 6 2 5 3

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Pan’s l-value Labeling

Traveling the whole circuit for updating l-values until no more updating in any node

Time complexity VDEVO log3

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Our Approach

Modified l-value definitionOptimal for general delay modelBased on W.-J. Chen, “A Study on the

Relationship Between Retiming and Loop Folding,” Master thesis, National Tsing-Hua Univ., Taiwan, R.O.C., Aug. 1994.FIFO to aid circuit traveling during labelingImprove run timeTime complexity

VVFEVFO log21222

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Modified l-value Labeling

If an FF’s position is occupied by a gate v,

detected by

)(),(*)(max)( vdvuwculvlvu

)(*1/)()(' vdccvlvl

l(v) 0 2 1

target c = 6

cvdvlcvl /)()(/)(

5 8 8 > 6

2 5 3

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14Example (target c = 7, inter-cluster delay = 2)

5 2

l(v) 3 1 3 10 12 1

l(v) 3 1 12 7

3 5

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1

3

3

1

3 5

3

3 1 5

212

9

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15Example (Cont’) (target c = 7, inter-cluster delay = 2)

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clustering connecting & retiming merging

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16Example (target c = 6, inter-cluster delay = 2)

5 2

l(v) 3 1 3 10 11 1

l(v) 3 1 11 7

3 5

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1

3

3

1

3 5

3

3 1 5

211

9

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17Example of Pan’s Approach (target c = 6, inter-cluster delay = 2)

2

l(v) 3 1 3 10 1

l(v) 3 1 8 6

3 5

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1

3

3

1

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18Example of Pan’s (Cont’) (target c = 6, inter-cluster delay = 2)

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clustering connecting & retiming merging

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Experimental Results

26 ISCAS-89 Benchmark CircuitsPan’s approach produces suboptimal

results for 11 circuitsOur approach produces optimal result

for every circuitOur CPU time consumption is 50% of

Pan’s

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Conclusion and Future Research

First exact algorithm for performance-optimal clustering with retiming under general gate delay model

Twice as fast as Pan’s near-optimal heuristic

Future research is to improve run time efficiency

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Experimental Results

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Pan's Ours

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s35932 s38417

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Experimental Results (Cont’)

0200400600800

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s820 s832 s838 s1196 s1238 s1423 s1488 s1494 s5378 s9234

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