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T1Author: Assist. Prof. Poenar Daniel Puiu
AnalogueElectronics (E2002)
Office: S2.2-B2-06Tel.: 6790 4237E-mail: [email protected]
Assist. Prof. Poenar Daniel Puiu
-Additions to TUTORIALS-
T1Author: Assist. Prof. Poenar Daniel PuiuRecapitulation:
BASIC EQUATIONS TO SOLVE ELECTRICAL CIRCUITS =KIRCHOFF’s LAWS:
01
=∑=
n
iiI
I1I3
Ii
I2
In
∑∑∑===
+=n
iii
n
ii
n
ii IRVE
111
R3 R2
R1R4
I1
V1
E1 E2
I3
I2
I2
I4
T2
1Assist.Prof. Poenar Daniel Puiu
Tutorial 2: Op-Amps (2)2.1. An inverting amplifier with a gain of –10 is made from anon-ideal op-amp having an input offset voltage of 1 mV. Asinusoidal input voltage of 0.1 mV peak amplitude is applied.What are the resulting A.C. and D.C. components of the outputvoltage?Solution:
Let’s draw the circuit so that we can model the input offsetvoltage as follows:
vOUT
R1 R2
vIO1 mV
vIN(0.1mVp)sinusoid
2
1
10RR
=
We are given that A= –10 =>
. Assume that the
op-amp operates in the linearregion. Then using the linearsuperposition principle wehave:(Consider first only vIN and passivate vIO):
( ) ( )21
1
sin 10 0.1sin 1 sin [ ]OUT IN peakRv A v v t t t mVR
ω ω ω= ⋅ = − ⋅ = − ⋅ = − ⋅
T2
2Assist.Prof. Poenar Daniel Puiu
( ) 22
1
1 11[ ]OUT noninv IO IORv A v v mVR
⎛ ⎞= ⋅ = + ⋅ =⎜ ⎟
⎝ ⎠
(Consider first only vIO and passivate vIN => non-inverting amplifier):
Hence: ( )2
111 sin [ ]OUT OUT i
iv v t mVω
=
= = −∑
11 mVvOUT
1 mV
time t
The (qualitative) graphical representation of the output signal is:
T2
3Assist.Prof. Poenar Daniel Puiu
2.2. A difference amplifier with a gain of 2 is made from an op-amp with the following parameters: VIO= 2 mV maximum; IBIAS=100 nA; IIO=0. If both inputs are set to zero, what is themaximum expected offset value of vOUT?
First, let’s remember what is the difference amplifier:Solution:
R3
R4
v2
vOUT
R1 R2v1
Its output voltage is given by:
2
2 11 2
31
4
1
1OUT
RR Rv v vRR
R
+= − +
+
and in many practical situations R3=R1 and R4=R2.In our case the gain is 2 => R2= 2 R1.
and the condition to reject common-mode signals (i.e. to have vOUT=0 when v1=v2) is R2/R1=R4/R3 which leads to:
( )22 1
1OUT
Rv v vR
= −
T2
4Assist.Prof. Poenar Daniel Puiu
R3
R4VIO
2 mVv1=0
vOUTI+
I–
R1 R2
v2=0
Let’s re-draw the circuit such that we can calculate the effect of the op-amp’s non-idealities (input offset voltage & input currents). In order to dothis we must set to zero other input (signal) sources, as follows:
Again, using the linear superposition principle we have:
T2
5Assist.Prof. Poenar Daniel Puiu
Consider first only VIO and passivate I+ and I– , i.e. make I+=I–=0:
( ) ( ) 1 2 23 4 22
1 2 1
|| 1OUT noninvR R Rv R R I A I R I
R R R+ + +
⎛ ⎞= − ⋅ = − ⋅ + = −⎜ ⎟+ ⎝ ⎠
( ) 21
1
1OUT noninv IO IORv A V VR
⎛ ⎞= ⋅ = + ⋅⎜ ⎟
⎝ ⎠Consider only I+ and passivate VIO and I–:
because R3=R1 and R4=R2.
( ) 23OUTv R I−=Consider only I– and passivate VIO and I+:
Hence: ( ) ( )3
22
1 1
1OUT OUT IOii
Rv v V R I IR − +
=
⎛ ⎞= = + + −⎜ ⎟
⎝ ⎠∑
(the common ends of R1 & R2 are at the same virtual potential as the non-inverting input of the op-amp, which is connected to GND)
and it was given
that IIO=0; since IIO= I+ – I– =0 => I+ = I– => vOUT= 3VIO = 6 mV.
T2
6Assist.Prof. Poenar Daniel Puiu
2.3. An op-amp is connected in the non-inverting amplifierconfiguration. A voltage source of value vS is connected via aseries resistance RS to the v+ terminal.
a) Find an expression for vOUT as a function of vS ifthe op-amp is ideal.
b) If the op-amp is non-ideal and has input biascurrents I+ and I– and input offset voltage VIO, find anexpression for vOUT when vS=0.
c) Combine the answers to parts (a) and (b) to findthe total output when vS is nonzero.
d) The feedback resistors in the amplifier are set to 25kΩ and 100 kΩ, so that the amplifier has a gain of 5. If IBIAS =(I++I–)/2= 100 nA, IIO= – 40 nA, and VIO= 2 mV, what value of RSwill minimize the total D.C. offset component to vOUT?
Again, first let’s remember what is the non-inverting amplifierSolution:and let’s re-draw it for the specific case of this problem:
T2
7Assist.Prof. Poenar Daniel Puiu
vS
R1 R2 vOUT
2
1
1noninvRAR
= +a) The ideal gain is:
RS
(no voltage drop across RS since the op-amp is considered ideal, i.e. I+=I–=0)
b) If the op-amp is non-ideal, we need to
RS VIOvS=0vOUT
I+
I–
R1 R2
(input offset voltage & input currents).
In order to do thiswe must set to zerothe signal inputsource.
re-draw the circuit such that we can calculatethe effect of the op-amp’s non-idealities
T2
8Assist.Prof. Poenar Daniel Puiu
Again, using the linear superposition principle we have:Consider first only VIO and passivate I+ and I– , i.e. make I+=I–=0:
( ) 21
1
1OUT noninv IO IORv A V VR
⎛ ⎞= ⋅ = + ⋅⎜ ⎟
⎝ ⎠
( ) ( ) 22
1
1OUT S noninv SRv R I A R IR+ +
⎛ ⎞= − ⋅ = − +⎜ ⎟
⎝ ⎠
Consider only I+ and passivate VIO and I–:
( ) 23OUTv R I−=Consider only I– and passivate VIO and I+:
Hence: ( )3
2 22
1 1 1
1 1OUT OUT IO Sii
R Rv v V R I I RR R− +
=
⎛ ⎞ ⎛ ⎞= = + + − +⎜ ⎟ ⎜ ⎟
⎝ ⎠ ⎝ ⎠∑
c) When vS≠0, the total output becomes
( )22
1
1OUT S IO SRv v V I R R IR + −
⎛ ⎞= + + − +⎜ ⎟⎝ ⎠
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9Assist.Prof. Poenar Daniel Puiu
2
1
1 5noninvRAR
= + = ⇒d) Since the ideal gain is R2= 100 kΩ, R1= 25 kΩ.
We are also given that IBIAS= 100 nA, IIO= –40 nA, that is:
1002
40
BIAS
IO
I II nA
I I I nA
+ −
+ −
+ ⎫= = ⎪⇒⎬⎪= − = − ⎭
I+= 80 nA and I–= 120 nA. We are alsogiven that VIO= 2 mV. The D.C.component of the previously deducedoutput voltage is:
( ) ( ) 2. .OUT noninv IO SD Cv A V I R R I+ −= − +
We must set (vOUT)D.C.=0 and solve the equation to find the correspondingRS solution. Making the necessary calculations one obtains:
2 5 2 100 0.12 22 555 0.08 0.4
noninv IOS
noninv
A V R I mV k AR kA I A
μμ
−
+
+ ⋅ + Ω ⋅= = = = Ω
⋅
(V/A =Ω => V/mA =kΩ => mV/μA =kΩ)
T2
10Assist.Prof. Poenar Daniel Puiu
2.4. An op-amp is connected in the inverting amplifierconfiguration. The gain of the amplifier is set to –50 by using100 kΩ and 2 kΩ resistors in the feedback circuit. A 2 kΩresistor is used to connect the v+ terminal to ground. The op-amp is non-ideal and has parameters IBIAS= 10 mA; IIO=0, VIO=+10 mV, and slew rate SR= 1 V/μs. Find the D.C. offsetcomponent to the output voltage caused by the non-idealparameters.
vOUT
R2
vIN
R32 kΩ
R12 kΩ
100 kΩ
We are given that A= –50 => 2
1
50RR
=
Since IIO=0 => I+=I– , then a resistorwith a resistance value R3=R1||R2 willprecisely cancel the effect of IBIAS. In
2
1
1 51 10 510OUT IORv V mV mVR
⎛ ⎞= + ⋅ = × =⎜ ⎟⎝ ⎠
this case R1||R2 = 1.46 kΩ ≅ R3= 2 kΩ. Therefore,
SR parameter is irrelevant to this calculation that deals with D.C. outputs.
. Note that the
Solution:
T2
11Assist.Prof. Poenar Daniel Puiu
2.5. A high-gain op-amp circuit is formed by cascading twoinverting amplifiers in series. Both op-amps are connected to±15V power supplies. The first stage has a gain of –20. Thecascade is to be designed so that the peak output voltage of thesecond stage comes no closer than 1 V to either power supplyvoltage. The cascade is built from non-ideal op-amps with VIO=2 mV and IBIAS≅0, IIO=0.
a) If both stages remain in the linear region, find anexpression for the output voltage that includes the effect of VIO.Express the gain of each stage in terms of the ratio of itsresistor values. (Stage 1 gain = – R2/R1; stage 2 gain = – R4/R3.)
b) If vIN is a sinusoid of 25 mV peak magnitude, whatis the maximum gain of the second stage if vOUT is to remainwithin the specified swing limits?
The circuit including VIO in each op-amp is:Solution:
T2
12Assist.Prof. Poenar Daniel Puiu
R3 R4
vOUT
VCC(+15V)
VEE(–15V)
VIO2 mV
R1 R2
VCC(+15V)
VEE(–15V)
(vOUT)1
vS
VIO2 mV
a) Assume wehave both VIOvoltages tohave the samepolarity. Usingthe linearsuperpositionprinciple weobtain:
( ) 2 21
1 1
1OUT S IOR Rv v VR R
⎛ ⎞= − + +⎜ ⎟
⎝ ⎠
A1
A2
( ) ( )4 42 1
3 3
1OUT OUT IOR Rv v VR R
⎛ ⎞= − + +⎜ ⎟
⎝ ⎠and
( ) 4 2 2 42
3 1 1 3
2 4 4 4 2 2 4 4 4 2 4
1 3 3 3 1 1 3 3 3 1 3
1 1
1 1 1
OUT OUT S IO IO
S IO S IO
R R R Rv v v V VR R R R
R R R R R R R R R R Rv V v VR R R R R R R R R R R
⎡ ⎤ ⎛ ⎞⎛ ⎞⇒ = = − − + + + + =⎢ ⎥ ⎜ ⎟⎜ ⎟
⎝ ⎠ ⎝ ⎠⎣ ⎦⎡ ⎤⎛ ⎞ ⎛ ⎞⎛ ⎞
+ + − + = + + − − ⇔⎢ ⎥⎜ ⎟ ⎜ ⎟⎜ ⎟⎝ ⎠⎝ ⎠ ⎝ ⎠⎣ ⎦
T2
13Assist.Prof. Poenar Daniel Puiu
2 4 2 4
1 3 1 3
1OUT S IOR R R Rv v VR R R R
⎛ ⎞⇔ = + −⎜ ⎟
⎝ ⎠b) A positive VIO will result in a negative output offset IF
R2R4≥R1R3. Thus, for a positive VIO a maximum negative excursion in vOUTwill occur during the negative peak of vS. By setting the condition vOUT=–14 V (so that the peak output voltage of the second stage comes no closerthan 1 V to either power supply voltage, as requested by the problem) whenvS= –25 mV (i.e. maximal negative input), one can solve for the gain ofstage 2, |A2|=R4/R3:
( ) ( )
2 4 2 4 4 2 2
1 3 1 3 3 1 1
4 4
23 3
1
1
14000 2 25.93 2620 25 2
OUT S IO IO S IO
OUT IO
S IO
R R R R R R Rv v V V v VR R R R R R R
R v V RRR Rv VR
⎛ ⎞ ⎛ ⎞= + − = + − ⇒⎜ ⎟ ⎜ ⎟
⎝ ⎠⎝ ⎠− − −
= ⇒ = = ≈− −−
For the maximum positive input vS= 25 mV => vOUT= 12 V.
T2
14Assist.Prof. Poenar Daniel Puiu
2.6. Consider the op-amp and amplifier circuit described inProbl. 2.4:
a) If the input voltage is a 10 mV peak sinusoid, whatis the maximum frequency that can be applied before the slewrate limitation is reached?
b) Repeat part (a) for an input voltage that consists ofa 10 mV peak triangular waveform.
c) Sketch the output voltage versus time if the inputis a 10 mV peak square wave.
a) The closed-loop gain for the circuit is:Solution: 2
1
50invRAR
= − = −
For vS= 0.01 sin ωt => vOUT= –0.5 sin ωt + (D.C. offset) =>
0.5 cos max 0.5OUT OUTdv dvtdt dt
ω ω ω⎧ ⎫= − ⇒ =⎨ ⎬⎩ ⎭
By setting this equal to SR we can find he required ωMAX:60.5 2 2 10 318MAX MAX MAX
radSR SR f kHzsω ω= ⇔ = ⋅ = × ⇔ ≅
T2
15Assist.Prof. Poenar Daniel Puiu
b) For a triangular input signal, its slope can be easily deduced:
0
vIN
–VP= –10 mV
Time t
VP=10 mV
T/2
2 4
2
P PV VSlope T T= =
Since the output isamplified by Ainv= –50times, we need to set thecondition
6
24 4 10 500
4 4 10 50P P
inv invP inv
V V SRA SR T A f kHzT SR V A −≤ ⇔ ≥ ⇔ ≤ = =
⋅ ⋅c) For a 10 mV peak square wave, vOUT tends towards Ainv×vIN= 10
mV×50= 0.5V peak level, but the rise and fall of the waveforms are limitedby the slew rate of 1 V/μs, as shown in the next Figure:
T2
16Assist.Prof. Poenar Daniel Puiu
0
vOUT
–VP= –0.5 V
Time t
VP=0.5 VT/2
1 μs
0.5 μs
2.7. An op-amp is connected in the non-inverting amplifierconfiguration. A gain of 11 is achieved by using 500 kΩ and 50kΩ resistors in the feedback circuit. The signal sourceconnected to the v+ input has a 50 Ω series Thevenin resistance.
a) If the op-amp has an input bias current of 1 μAcalculate the D.C. value of vOUT when vIN=0. Assume IIO=0.
b) Choose an additional resistor to be put in serieswith the input source so that D.C. offset found in part (a) isforced to zero.
T2
17Assist.Prof. Poenar Daniel Puiu
vIN
R1 R2
RTH50 Ω
I+
I–
500 kΩ50 kΩ
Assume IIO=0 => I+=I–=IBIAS= 1 μA. Then, when vIN=0 the circuit becomes:
R1 R2 vOUT
RTH50 Ω
I+
I–
500 kΩ50 kΩ
Therefore,( ) 32
21
1 1 50 11 1 500 10OUT THRv I R I R A AR
μ μ+ −
⎛ ⎞= − + + = − ⋅ ⋅ + − ⋅ ⋅ =⎜ ⎟
⎝ ⎠= –0.55 mV + 500 mV= 499.45 mV.
b) As IIO=0 then the required total resistance connected to the v+ terminalis R1 | | R2 = 45.45 kΩ. Therefore, the additional resistor RS necessary tobe added in series to the existing RTH should be RS= R1| |R2 – RTH=45.4 kΩ
Solution:
vOUTa)
T2
18Assist.Prof. Poenar Daniel Puiu
2.8. An op-amp circuit with a D.C. gain of 400 is formed bycascading in series two inverting amplifiers with gains of –20.Both op-amps are connected to ±15V power supplies and haveslew rates of 1 V/μs.
a) If the input is a sinusoidal voltage, what peakmagnitude drives the output to its full swing range if Vsat-pos=14.3 & Vsat-neg= –14V?
b) For the input voltage found in part (a), what is themaximum frequency in [Hz] that the input voltage can havebefore the slew rate limitation becomes important ?Solution: a) The overall closed-loop gain of the two stage cascaded
op-amp circuit is:AVCL=(AVCL)1
.(AVCL)2=(–20)×(–20)= 400 => vOUT= 400 vIN , and we knowthat vOUT must be limited to ±14 V => the input must be limited to
14 35400
OUT MAXIN p
VCL
vv mVA
− ±= = = ±
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19Assist.Prof. Poenar Daniel Puiu
b) The largest signal will appear at the output of the second stage, henceonly the 2nd op-amp will suffer from slew rate limitations.
If vIN= VP sin ωt => vOUT= AVCL.VP sin ωt =>
6
3
cos max
10 11368.21 11.42 2 400 35 10
OUT OUTVCL P VCL P
VCL P
dv dvA V t A V SRdt dt
SRf kHzA V
ω ω ω
π π −
⎧ ⎫= ⇒ = ≤ ⇒⎨ ⎬⎩ ⎭
⇒ ≤ = = ≅⋅ ⋅ ×
T3
1Assist.Prof. Poenar Daniel Puiu
3.1- a) The op-amp in the Fig.3.1-A below has a unity-gainfrequency of 1.2 MHz.
i) What is the closed loop BW?ii) What is the closed-loop gain at 600 kHz ?
Tutorial 3: Op-Amps (3)
vOUT
R1 R2
vIN
5 kΩ 95 kΩFig.3.1-A:
Fig.3.1-B:
b) The op-amp shown in Fig.3.1-B has a SR of 4 V/μS anda unity-gain frequency of 2 MHz. Determine whether theamplifier will distort or not the input signal shown.
vOUT
R2
vIN
R120 kΩ
20 kΩ
Time t5 μs
5V
–2V
vIN
T3
2Assist.Prof. Poenar Daniel Puiu
Solution: a-i) We know that the unity-gain freq. is fT= 1.2 MHz. We can easily calculate the feedback factor (feedback factor) β:
1
1 2
5 0.055 95
RR R
β = = =+ +
We also know that the 3 dB bandwidth is given by 3CL dB TBW f fβ= =which applied in this case gives the value f3dB= 0.05×1.2 MHz= 0.06 MHz= 60 kHz
a-ii) At low frequencies ACL-DC= 1/β = 20.At 600 kHz. i.e. one decade beyond 60 kHz the gain will reduce
with 20 dB = 10 times. Thus,( ) ( ) 20600 600 2
10 10OUT CL DC
CLIN
v AA kHz kHzv
−= = = =
Note that ACL×f3dB= fT =1.2 MHz
b) The closed-loop gain of the circuit is: 2
1
201 1 220CL
RAR
= + = + =
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3Assist.Prof. Poenar Daniel Puiu
Therefore, when the input signal varies between –2V to 5V the outputchanges from –4V to 10V, obviously in the same period of time, Δt=5 μs.
Then, 14 3.5 (1).4
V V s tVSR sμ
μ
Δ= = < Δ Also, since 1
1 2
0.5RR R
β = =+
we have BWCL= f3dB-CL= β×fT =0.5×2 MHz = 1 MHzMoreover, we know that the eqn. for the settling time is
60.35 0.35 0.35 (2)
10settleCL
t s tBW
μ= = = << Δ
From both conditions (1) and (2) => No distortion will occur.
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4Assist.Prof. Poenar Daniel Puiu
3.2- The op-amp in Fig.3.2 has a slew rate of 0.5 V/μs. Theamplifier must be capable of amplifying the following inputsignals:v1 = 0.01 sin(106t)v2 = 0.05 sin(350×103t)v3 = 0.1 sin(200×103t)v4 = 0.2 sin(50×103t)
a) Determine whether the output will be distorted due to slew-rate limitations on any input.
b) If so, find a remedy (other than changing the input signals).
vOUT
R1 R2vIN10 kΩ 330 kΩ
Fig.3.2:
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5Assist.Prof. Poenar Daniel Puiu
a) Assuming an ideal op-amp, the closed-loop voltage gain of the stage is:2
1
330 3310CL
RAR
= − = − = −
For a sinusoidal input with peak value AP, the upper limit for the stage’smax. operating frequency is: 40.5 1.515 10(3)
33CL P MAXCL P P P
VSR sA A SR
A A A Aμω ω ×
≤ ⇔ = = =⋅
Therefore, we can now make the calculations for each case:v1 = 0.01 sin(106t) => AP= 0.01 V, ω = 106 rad.
4 461.515 10 1.515 10 1.515 10
0.01MAXPA
ω × ×= = = ×
Since ω <ωMAX, no distortion will occur.v2 = 0.05 sin(350×103t) => AP= 0.05 V, ω = 3.5×105 rad.
4 451.515 10 1.515 10 3.03 10
0.05MAXPA
ω × ×= = = ×
In this case ω >ωMAX, hence distortion will occur.
Solution:
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6Assist.Prof. Poenar Daniel Puiu
v3 = 0.1 sin(200×103t) => AP= 0.1 V, ω = 2×105 rad.4 4
51.515 10 1.515 10 1.515 100.1MAX
PAω × ×
= = = ×
In this case ω >ωMAX, hence distortion will occur.
v4 = 0.2 sin(50×103t) => AP= 0.2 V, ω = 5×104 rad.4 4
41.515 10 1.515 10 7.575 100.2MAX
PAω × ×
= = = ×
Since ω <ωMAX, no distortion will occur.Consequently, both v2 and v3 would cause the SR spec of the op-amp to
be exceeded, resulting in distortions of the output.
b) Two remedies can be applied to deal with the given signals:i- Use an op-amp with a better SR:
The SR value of the new op-amp can be also extracted from the samecondition (3) used previously: (3)CL PSR A A ω≥ . Aplying it for v2 yields
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7Assist.Prof. Poenar Daniel Puiu
SR ≥ 33 × 0.05 × 3.5×105 = 5.775×105 V/s = 0.5775 V/μswhereas for v3 we obtainSR ≥ 33 × 0.1 × 2×105 = 6.6×105 V/s = 0.66 V/μs.
If we want to cover both cases with the same circuit, an op-ampwith a SR of min. 0.66 V/μs should be used, although it would be wise toalso have some safety margin for other practical cases (or for variations inactual device characteristics). Hence, using an op-amp with a SR value of0.8…1 V/μs would be more realistic.
ii- Reduce the ACL of the amplifier stage:This solution is necessary when the whole circuit has already been
realized and solution (i) above cannot be implemented. We use againcondition (3) to find out the necessary ACL value(s):
(3)CL P CLMAX P
SRA A SR AA
ωω
≤ ⇔ ≤
Aplying it for v2 yields
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8Assist.Prof. Poenar Daniel Puiu
5
2 55 10 28.57
3.5 10 0.05CLMAX P
SRAAω
×≤ = =
× ⋅
5
3 55 10 25
2 10 0.1CLMAX P
SRAAω
×≤ = =
× ⋅
while for v3 we obtain
Again, if we want to cover both cases with the same circuit, we mustchoose the second value, as it would satisfy the conditions for both signals:ACL=25, which can be achieved if we change the R2 value from 330 kΩ to250 kΩ.
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9Assist.Prof. Poenar Daniel Puiu
3.3- a) What minimum SR is necessary for a unity-gainamplifier that must pass, without distortion, the input waveformshown in Fig.3.3.
b) Repeat (a), if the amplifier is in a non-invertingconfiguration with R1= 50 kΩ and R2= 100 kΩ.
Fig.3.3:
Time t [μs]
2V
–3V
vIN
4V
6V
10 122 16 18
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10Assist.Prof. Poenar Daniel Puiu
Solution: a) There are 5 intervals making up the piece-wise signalsignal shown in Fig.3.3, but only in 4 of them the voltage changes:
4 0 22 0
V Vst μ
Δ −= =
Δ −1) 2)
4 ( 3) 0.87510 2
V Vst μ
Δ − −= =
Δ −
3)6 ( 3) 2.2516 12
V Vst μ
Δ − −= =
Δ −4)
6 0 318 16
V Vst μ
Δ −= =
Δ −If we want to cover both cases with the same circuit, an op-amp with a SRof min. 3 V/μs should be used.
b) For a non-inverting configuration with R1=50 kΩ and R2=100kΩ (see again Probl.3.1):
2
1
1 3CLRAR
= + =
Consequently, having now an ACL≠1 will increase correspondingly each ΔVby a factor of 3 => the necessary SR value is now 3× larger than that for theprevious case: SRmin= 9 V/μs.
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11Assist.Prof. Poenar Daniel Puiu
3.4- In a certain application, a signal source having 60 kΩ ofsource resistance produces a 1 V r.m.s. signal. The signal mustbe amplified to 2.5 V r.m.s. and drive a 1 kΩ load. Assuming thatthe phase of the load voltage is of no concern, design an op-amp circuit for the application.Solution: a) Inverting configuration:The signal source can be represented by Thevenin’s equivalent circuit:
vS= RTH60 kΩ
2 sin tω => vOUT
R1 R2
vIN
vSRTH
60 kΩ
RL1 kΩ
1
1IN S
TH
Rv vR R
=+
It is clear that
At the same time 2 2
1 1
OUTCL OUT IN
IN
v R RA v vv R R
= = − ⇔ = − and combining thetwo relations gives
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12Assist.Prof. Poenar Daniel Puiu
2 1 2 1
1 1 1 1OUT S TOT
TH TH
R R R Rv v AR R R R R R
= − ⋅ ⇒ = − ⋅+ +
In our case it was specified that the signal must be amplified to 2.5 V rms=>ATOT=2.5. The values of the resistors R1,2 should also be high enough sothat the currents passing through them should be << IL.
For example, one can choose R1= 47 kΩ =>1
1
47 0.43925 0.4447 60IN S
TH
Rv vR R
= = = ≅+ +
and then
12 1
1
12.5 47 267.50.44
THTOT
R RR A R kR+
= ⋅ = ⋅ ⋅ = Ω
A very close practical resistor value is 270 kΩ.
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13Assist.Prof. Poenar Daniel Puiu
2
1
1CLRAR
= + and must be =2.5 => 2
1
1.5RR
=
If we choose R1= 100 kΩ => R2= 150 kΩ.c) Voltage follower:
b) Non-Inverting configuration:For an ideal op-amp I+=I–=0 => vS = vIN andit was given that vIN=1 Vrms and we musthave vOUT=2.5 Vrms => ACL= 2.5
vIN
R1 R2
RTH50 Ω
vOUT
RL1 kΩ
vS
I+
I–
vOUT
R1 R2
vIN
vS RTH60 kΩ
RL1 kΩ
A1
A2vO1
and we must have vOUT=2.5 Vrms=> |ACL|= 2.5
vS = vIN ; vOUT=ACLvO1
22 1
1
2.5 2.5 .R R RR
⇒ = ⇔ = We can set R1= 100 => R2= 250 kΩOR R1= 47 kΩ and R2= 117.5 kΩ; use 120 kΩ.
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14Assist.Prof. Poenar Daniel Puiu
3.5- Fig.3.5 shows anintegrator employing an op-amp whose frequencyresponse is given by
0
0
( ) .1
AA s sω
=+
Determine the transferfunction of the overallintegrator. Simplify theresult if ω0>> 1/(RC).
Solution:
vIN
R C
vOUT
A(s)
Fig.3.5:
v–
the frequency response given for the op-amp have a representation of the form:
0
ωω
(log scale)
[ ]0
( )20log A s dBA
0
–10
–20
–30
–3 dB – 6 dB/octave = –20 dB/decade
0.1 1 10
The Bode plots describing
Φ(ω)[deg]
–45
–905.7o
5.7o
– 45o/decade
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15Assist.Prof. Poenar Daniel Puiu
Therefore, it would be convenient to express the final result as a product ofelementary one-pole functions.
Being given the op-amp’s (not the entire circuit’s!) frequencyresponse A(s), we can write vOUT= –v–
.A(s)
and at the same time ( )1IN OUT
OUTv v v v sC v v
R sC
− −−
− −= − = −
We extract v– from the first relation, introduce it in the 2nd and carry out thecalculations:
[ ]
[ ]
( )( )
( ) 1 ( )
1 ( ) 1 ( )
OUTIN
OUTOUT
IN OUT OUT
OUT
IN
vvvA s sC v
R A sA s v v sRC v A sv sRC A s A sv
+⎛ ⎞
= − −⎜ ⎟⎝ ⎠
⇔ ⋅ + = − ⋅ +
⇔ − + − =
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16Assist.Prof. Poenar Daniel Puiu
[ ]
0
0
0
0
0
0
0
0
1( )( )
1 1 ( )
1 11
( )
1 1 11
As
A sH ssRC A s
AsRC s
AH s
s AsRC s
ω
ω
ωω
+⇔ = − = −
+ + ⎛ ⎞⎜ ⎟
+ +⎜ ⎟⎜ ⎟+⎜ ⎟⎝ ⎠
⇔ = −⎡ ⎤⎛ ⎞⎢ ⎥⎜ ⎟⎛ ⎞⎢ ⎥+ ⋅ + +⎜ ⎟⎜ ⎟⎢ ⎥⎜ ⎟⎝ ⎠ +⎜ ⎟⎢ ⎥⎝ ⎠⎣ ⎦
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17Assist.Prof. Poenar Daniel Puiu
( )
0
00 0
0 02
0 0 0 0
2
0 0 0 0 0 0
20
0 0
( )1 1
( )
1( )1
1( ) 1
AH ss ssRC sRCA
AH ss sRC s RC sRCA
H ss sRC s RC sRC
A A A A
H ss s RC sRC sRC
A
ω ωω
ω ω ω
ω ω
ωω
⇔ = −⎛ ⎞ ⎛ ⎞
+ + + +⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠
⇔ = −+ + + +
⇔ = −+ + + +
⇒ ≅ −+ + +
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18Assist.Prof. Poenar Daniel Puiu
3.6- Design an integrator that attenuates input frequenciesabove 100 kHz and exhibits a pole at 100 Hz. Assume thelargest available capacitor is 50 pF.
22
0 00 0 0 0 0 0
1 1 1( )1 1
H s RCRC ssRC ss RC s sRCAA A Aωω ω ω
− − −⇒ ≈ ≈ =
⎛ ⎞ ⎛ ⎞++ + +⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠
Obviously, the same schematic and starting point can be usedSolution:as in the previous problem:
vIN
R
C
vOUT
A0
Fig.3.6:
v–
( )1IN OUT
OUTv v v v sC v v
R sC
− −−
− −= − = −
However, in this case we consider the op-amp to be characterized by A0 =>vOUT= –v–×A0. Again, extracting v– from the
first relation and then substituting it into thefirst equation results in
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19Assist.Prof. Poenar Daniel Puiu
( )
( ) ( )
00 0
0
00 0
0
1
1 1 ( )1 1
OUTIN
OUTOUT IN OUT OUT
OUT
IN
vvvA sC v A v v sRC v A
R Av AsRC A A H sv sRC A
+⎛ ⎞
= − − ⇔ ⋅ + = − ⋅ +⎜ ⎟⎝ ⎠
−⇔ − + − = ⇔ =⎡ ⎤⎣ ⎦ + +
0
0
( ) .1
AA s sω
=+
Let’s compare this response with the generic representation of a one-pole
transfer characteristic from the previous problem
It quickly becomes evident that the pole is at( )0
0
1 .1RC A
ω =+
We could thus calculate R if we knew A0. To deduce A0 we use the otherpiece of data given by the problem: input frequencies above 100 kHz areattenuated. This translates into saying that (see again the Bode plots of theprevious problem) |H(ω)|=1 at f= 100 kHz.
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20Assist.Prof. Poenar Daniel Puiu
=> A0 ≅ 103. If we choose C to have the given max. value, C=50 pF, thenwe can now calculate the unknown R:
( ) 12 30 0
1 1 31.832 1 2 100 50 10 10
R kf C Aπ π −= = ≈ Ω
+ ⋅ ⋅ × ⋅
From the previous expression of A(s) one can easily deduce that themagnitude response is 0
2
0
( ) .
1
AA ω
ωω
=⎛ ⎞
+ ⎜ ⎟⎝ ⎠
and therefore for our equation |H(ω)|=1 at f= 100 kHz we can write2 25
00100 2
0
0
10| ( ) | 1 1 1100
1f kHz
A fH Aff
f
ω=
⎛ ⎞ ⎛ ⎞= = ⇒ = + = +⎜ ⎟ ⎜ ⎟
⎝ ⎠⎝ ⎠⎛ ⎞+ ⎜ ⎟
⎝ ⎠
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1Assist.Prof. Poenar Daniel Puiu
Problem 4.1- Consider a pn junction in forward bias.(a) To obtain a current of 1 mA with a voltage of 750 mV, how
should IS be chosen?(b) If the diode cross-sectional area is now doubled, what
voltage yields a current of 1 mA?Solution:
a) In forward bias, IF=ID=1 mA and VF =VD = 0.75 V. We also knowthe expression for the dependence of the current on the voltage in thisregime:
exp DD S
T
VI IV
⎛ ⎞≅ ⎜ ⎟
⎝ ⎠What is VT? VT is the so-called thermal voltage:
[ ][ ] [ ]1
19
23
647.381875.25][106.1
][3001038.1−
−
−
≅⇒≅⋅
⋅⋅== V
VmV
C
KKJ
qkTV
TT
(1)
Tutorial 4: The diode (the semiconductor pn junction)
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2Assist.Prof. Poenar Daniel Puiu
From eqn. (1), we can extract and calculate the value of the unknownparameter IS:
3 16
exp exp
75010 exp 2.58 1025.875
D DD S S D
T T
S
V VI I I IV V
I A− −
⎛ ⎞ ⎛ ⎞≅ ⇔ ≅ − ⇒⎜ ⎟ ⎜ ⎟
⎝ ⎠ ⎝ ⎠⎛ ⎞⇒ ≅ ⋅ − ≅ ×⎜ ⎟⎝ ⎠
b) Since IS is directly proportional to area, doubling the areaautomatically implies that IS has also doubled: now we have IS2= 2IS and atthe same time
2 22 2 2
2
exp lnD DD S D T
T S
V II I V VV I
⎛ ⎞≅ ⇔ ≅ ⋅⎜ ⎟
⎝ ⎠(2)
Inserting the values we obtain:3
2 161025.875 ln 732.065 732
2 2.58 10DV mV mV−
−= ⋅ = ≅× ×
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3Assist.Prof. Poenar Daniel Puiu
4.2- Consider the circuit shown in Fig.4.2, where IS = 2x10–15 A.Calculate VD and IX for VX = 0.5 V, 0.8 V, 1 V, and 1.2 V. Note thatVD changes little for VX ≥ 0.8 V.
Solution:Obviously diode D is forward biased, and therefore we can write thecorresponding well-known expression for the dependence of the current onthe voltage:
VXIX
R=2 kΩ DFig.4.2:
exp 1 expD DX F D S S
T T
V VI I I I IV V
⎡ ⎤⎛ ⎞ ⎛ ⎞= = = − ≅ ⋅ ⇔⎢ ⎥⎜ ⎟ ⎜ ⎟
⎝ ⎠ ⎝ ⎠⎣ ⎦
(3)ln lnD XD T T
S S
I IV V VI I
⎛ ⎞ ⎛ ⎞⇔ = =⎜ ⎟ ⎜ ⎟
⎝ ⎠ ⎝ ⎠
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4Assist.Prof. Poenar Daniel Puiu
ln lnD XX R D R T X T
S S
I IV V V RI V RI VI I
⎛ ⎞ ⎛ ⎞= + = + = +⎜ ⎟ ⎜ ⎟
⎝ ⎠ ⎝ ⎠
We can easily notice that the sum of voltage drops on the resistor & diodemust equal the bias from the voltage source:
(4)
At the same time, the current through the resistor can also be expressed as:
R X DX R D
V V VI I IR R
−= = = = (5)
The desired final values of VD and ID=IX can be obtained by solvingiteratively EITHER eqn.s (3) & (5), OR (4).
Let’s consider the 1st option, and start with the first given value:VX=0.5 V. We assume that D1 is ON; moreover, in order to obtain thenumerical values we assume an initial ‘guess’ value for VD1 of 0.4V.
Then applying eqn.(5) results in: 0.5 0.4 0.052XI mA−
= = which,
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5Assist.Prof. Poenar Daniel Puiu
3
1 150.05 1025.875 ln 619.52 10DV mV
−
−
⎛ ⎞×= ⋅ =⎜ ⎟×⎝ ⎠
However, it can be easily noticed that this value makes VD >VX, which isobviously impossible! Therefore, our initial assumption is incorrect.This means that for VX = 0.5 V, the diode D is OFF, i.e. NO CURRENTflows through it, hence no current flows through the whole circuit:ID=IR=IX=0 => VD= VX =0.5 V.
In fact, this should have been expected, since the first given value of(VX = 0.5 V) is obviously below the typical threshold voltage of a silicondiode (~0.6…0.8 V).
For the second value, VX= 0.8 V, we can assume safely that D is ON(because now VX is above the diode’s threshold voltage) and VD= 0.7 V. Werepeat the same sequence of calculations:
!!!
0.8 0.7 0.052XI mA−
= =and apply successively eqn.s (3) & (5):
inserted in eqn.(3) gives
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6Assist.Prof. Poenar Daniel Puiu
Eqn.(5)(Calc.ID)Eqn.(3)(Calc.VD) 0.7 0.6225 0.637 0.635 0.635
5×10–5 8.875×10–5 8.15×10–5 8.25×10–5Iteration 1 Iteration 2 Iteration 3 Iteration 4
Guessvalue No more variation from one step to another: STOP
Hence, the final values are: VD ≅ 0.635V, and ID ≅ 8.25×10–5 A = 82.5 μA
The same procedure is thus repeated for the other values. For VX = 1 V, we get:
Eqn.(5)(Calc.ID)Eqn.(3)(Calc.VD) 0.7 0.651 0.655 0.655
1.5×10–4 1.745×10–4 1.725×10–4Iteration 1 Iteration 2 Iteration 3
Guessvalue No more variation from one step to another: STOP
In this third case the final values are: VD ≅ 0.655V, and ID ≅ 172.5 μA.
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7Assist.Prof. Poenar Daniel Puiu
For the last VD value (VD= 1.2 V), let’s try a slightly different approach,based on using eqn. (4):
from which we extract IX:
ln XX X T
S
IV RI VI
⎛ ⎞= + ⎜ ⎟
⎝ ⎠(4)
and this can also be solved iteratively (fixed-point iteration method):
lnX T XX
S
V V IIR R I
⎛ ⎞= − ⎜ ⎟
⎝ ⎠(4’)
We can now insert the values, and start the calculations using an initial guess value based again on the result given by eqn.(5):
( ) ( )1
ln X nX TX n
S
IV VIR R I+
⎡ ⎤= − ⎢ ⎥
⎢ ⎥⎣ ⎦(4’’)
( ) 40
1.2 0.7 0.25 2.5 102XI mA A−−
= = = × which we
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8Assist.Prof. Poenar Daniel Puiu
insert and use for the iteration sequence based on eqn (4’’):(IX)1≅ 2.678×10–4 A(IX)2≅ 2.669×10–4 A(IX)3≅ 2.670×10–4 A(IX)4≅ 2.670×10–4 A
Then VD value is then obtained applying eqn. (3):4
15
2.67 10ln 25.875 ln 663.852 10
DD T
S
IV V mVI
−
−
⎛ ⎞ ⎛ ⎞×= = ⋅ ≅⎜ ⎟ ⎜ ⎟×⎝ ⎠⎝ ⎠
4.3- For the circuit shown in Fig.4.3 is given that at VX = 1 V →IX = 0.2 mA and at VX = 2 V → IX = 0.5 mA. Calculate R and IS.
VXIX
RDFig.4.3: VD
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9Assist.Prof. Poenar Daniel Puiu
Solution: Again, diode D is forward biased. At the same time, by KVL
ln lnX XD T X X T
S S
I IV V V I R VI I
= ⇔ − =VD= VX – IX R and also
and inserting the given values in the latter equation results in0.21 0.2 ln (6)
0.52 0.5 ln (7)
TS
TS
R VI
R VI
⎧ − =⎪⎪⎨⎪ − =⎪⎩
(with all voltages in [V] and currents in [mA] => all resistances must be in [kΩ]),and subtracting (7)–(6) gives
3
0.51 ln0.5 0.2 0.5 0.21 0.3 ln ln ln0.2 0.3
0.51 25.875 10 ln0.2 3.255
0.3
T
T T TS S
VR V V V R
I I
R R k−
−− = − = ⇔ =
− ⋅⇔ = ⇒ ≅ Ω
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10Assist.Prof. Poenar Daniel Puiu
Now we can find IS substituting the value of R in any of the eqn.s (6) or (7),e.g. in (6):
3
7 10
0.2 0.2 1 0.21 0.2 ln exp
1 0.2 1 0.2 3.2550.2exp 0.2exp25.875 10
2.76 10 2.76 10 0.276
TS S T
ST
S
RR VI I V
RIV
I mA A nA
−
− −
⎛ ⎞−− = ⇔ = ⇔⎜ ⎟
⎝ ⎠⎛ ⎞− − ⋅⎛ ⎞= = −⎜ ⎟ ⎜ ⎟⋅⎝ ⎠⎝ ⎠
≅ ⋅ = ⋅ =
4.4- Fig.4.4 depicts a parallel resistor-diode combination. IfIS= 3x10–16 A, calculate VD for IX = 1, 2, and 4 mA, respectively.
IX RD
VDID
It is clear that ID= IX –IR= IX –(VD/R) (8),
IR ln (9)DD T
S
IV VI
=
Again, these two equations can be solved iteratively for each case.
and at the same time
Fig.4.4:
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11Assist.Prof. Poenar Daniel Puiu
Eqn.(8)(Calc.ID)Eqn.(9)(Calc.VD) 0.7 0.718 0.717 0.717
3×10–4 2.82×10–4 2.832×10–4Iteration 1 Iteration 2 Iteration 3
Guessvalue No more variation from one
step to another: STOP
For IX = 1 mA:
Eqn.(8)(Calc.ID)Eqn.(9)(Calc.VD) 0.717 0.756 0.755 0.755
1.283×10–3 1.244×10–3 1.245×10–3Iteration 1 Iteration 2 Iteration 3
Guessvalue
For IX = 2 mA:
Notice that in the 2nd case the final value from the previous calculation isused as initial guess in order to minimize the number of steps to becalculated.
No more variation from one step to another: STOP
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12Assist.Prof. Poenar Daniel Puiu
For the last IX value (4 mA), let’s use again the fixed-point iteration method
which can be re-written in the more suitable form1
lnT DD X
S
V II IR I
⎛ ⎞= − ⎜ ⎟
⎝ ⎠
We can now insert the values, and start the calculations using an initial guess value based again on the result given by the final value of the previous case:
( ) ( )1
1
ln DT nD Xn
S
IVI IR I+
⎡ ⎤= − ⎢ ⎥
⎣ ⎦
further resulting in(ID)1≅ 3.223 mA => (ID)2≅ 3.223609 mA =>(ID)3≅ 3.2236078 mA => (ID)4≅ 3.2236078 mA≅ 3.224 mA
( )3
3160
1.245 104 25.875 10 ln 4 0.752 3.2483 10DI mA
−−
−
⎡ ⎤⋅= − ⋅ ≅ − =⎢ ⎥⋅⎣ ⎦
33
163.223078 1025.875 10 ln 776.39
3 10DV mV−
−−
⎡ ⎤⋅= ⋅ ≅⎢ ⎥⋅⎣ ⎦
so that
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13Assist.Prof. Poenar Daniel Puiu
4.5- Sketch VX as a function of IX for the circuit shown inFig.4.5. Assume: (a) A constant-voltage model, (b) Anexponential model.
IX RD
VD=VXIDIR
Fig.4.5:
a) Consider first the extreme casewhen D= OFF => the circuitsimplifies as
IX R VR=VX
IR
Solution:
and obviously VX is linearly proportional to IX, according to Ohm’s law.When D= ON, VX is fixed as VD-ON=VF ≅0.7 V. Therefore, the
current flowing through R is also fixed and (quasi)constant IR=VF/R (weimplicitly assumed that the current source IX can provide more than thisvalue! Otherwise, D cannot be ON and we are in the previous case!). Thismeans that any additional current (if the current source IX supplies morethan the value of IR) must flow through D.
Consequently, the plot of VX vs. IX will be:
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14Assist.Prof. Poenar Daniel Puiu
VX
IXVF /R
VF
D= Forward biased
D= Reverse biased
α
Slope=tan α=R
b) If an exponential I-V modelis used for D, we still have twocases but the quantitative valueswill be different. WhenD=OFF, the greatest part of IXflows through R, and only avery small part (yet ≠0 !) flowsthrough D. When D= ON, thecurrent IR is again fixed and anyadditional current must flowthrough D. In order to make the
calculations we can use the relations:
It is now clear that in each case one of the term dominates. For instance, in the 2nd case, if IR<<ID (when VX>>VT), then we can approximate
ln expD X X XD X T D X X S
S T
I V V VV V V and I I I II R V R
⎛ ⎞= = = − ⇒ = +⎜ ⎟
⎝ ⎠
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15Assist.Prof. Poenar Daniel Puiu
exp lnX XX S X T
T S
V II I V VV I
⎛ ⎞≅ ⇔ ≅⎜ ⎟
⎝ ⎠Consequently, the plot of VX vs IX will be:VX
IXIF
D= Forward biased
D= Reverse biased
IR<<IDVX ∝ ln(IX )IR>>ID
VX∝IX
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16Assist.Prof. Poenar Daniel Puiu
4.6- Beginning with VD-ON ≅ 800 mV for each diode, determinethe change in VOUT, if VIN changes from +2.4 V to +2.5 V for thecircuits shown in Fig.4.6.
VIN
VOUT
R1=1 kΩ
a) Solution: In this case it is clear that VOUT=VIN –VDVD
and, therefore, the output values when the input variesbetween 2.4 and 2.5 V will be VOUT =VIN –VD-ON=VOUT–0.8 => VOUT= 1.6…1.7 V.
VIN
VOUT
R1=1 kΩ
b) VD
D
D1
D2
In this case, when the input varies between 2.4 and2.5V both diodes are ON and the output values will bethe same as in the previous case: VOUT = VIN – VD1-ON=VOUT – 0.8 => VOUT = 1.6…1.7 V.
Fig.4.6:
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17Assist.Prof. Poenar Daniel Puiu
VIN
VOUTR1=1 kΩ
c)VD1
D1
D2VD2
Again, when the input varies between 2.4 and2.5V both diodes are ON and the outputclearly is: VOUT =VD2-ON = 0.8.
VIN
VOUTR1=1 kΩ
d) D VDR2=2 kΩ
As in the previous case, when the input variesbetween 2.4 and 2.5V the diode is ON and theoutput clearly is: VOUT =VD-ON = 0.8.
Fig.4.6 (continued):
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18Assist.Prof. Poenar Daniel Puiu
4.7- Determine the AC component of the output voltage, vOUTfor the circuit in Fig.4.7 when VSDC= 5 V D.C.
The data sheet for the 1N4305 diode has the followingvoltage and current values:
VD1= 0.5 V at ID1 = 250 μAVD2 = 0.7 V at ID2 = 10 mA
VSDC(5V)
RS=0.47 kΩD
1N4305
Fig.4.7:
vSAC(0.1Vpp)
Solution:
2 2 1 2 1
21
1
exp 1 exp
expln
D DF D S S
T T
D D D D DT
DD T
D
V VI I I IV V
I V V V VV II VI
η η
ηη
⎡ ⎤⎛ ⎞ ⎛ ⎞= = − ≅ ⋅⎢ ⎥⎜ ⎟ ⎜ ⎟
⎝ ⎠ ⎝ ⎠⎣ ⎦⎛ ⎞− −
⇒ = ⇔ =⎜ ⎟⎝ ⎠
We know that
Inserting the values we obtain: 2 13
26
1
0.7 0.5 54.21710 10ln ln250 10
D DT
D
D
V VV mVII
η −
−
− −= = =
⋅⋅
vOUT
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19Assist.Prof. Poenar Daniel Puiu
Now we can easily find IS:
2 822
0.7exp 10 exp 2.47 100.054217
DS D
T
VI I AVη
− −⎛ ⎞ ⎛ ⎞= ⋅ − = − = ⋅⎜ ⎟ ⎜ ⎟⎝ ⎠⎝ ⎠
(It is necessary to use the equation for ID2 because the unity in theexpression of ID can be easily neglected).
Now we can calculate the AC component of the vOUT. For this weneed first to carry out 2 consecutive analyses: D.C. and A.C.DC analysis: The circuit can be re-drawn as:VSDC(5V) RS=0.47 kΩ
D1N4305
This is identical with the cases studied earlier in Problems 1.2 and 1.3:ID
38ln 54.217 10 ln
2.47 10D D
D TS
I IV VI
η −−
⎛ ⎞ ⎛ ⎞= = ⋅⎜ ⎟ ⎜ ⎟⋅⎝ ⎠⎝ ⎠
5470
RS SDC D DD RS
S S
V V V VI IR R
− −= = = = (10) and
(11), which we solve iteratively:
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20Assist.Prof. Poenar Daniel Puiu
Eqn.(10)(Calc.ID)Eqn.(11)(Calc.VD) 0.7 0.69518 0.695238 0.695238
9.1489×10–3 9.1592×10–3 9.15907×10–3Iteration 1 Iteration 2 Iteration 3
Guessvalue
AC analysis: In this case we need to consider the small-signaldynamic resistance of the diode at its DC bias point calculated above. Thedynamic resistance is given by:
30.054217 5.92
9.159 10T
dD
VrIη
−= = = Ω⋅
RS=0.47 kΩrd
vOUT
vSAC(0.1Vpp) iD
and, evidently
5.92 0.1 1.2445.92 470 ppmV= ⋅ =
+
dOUT SAC
d S
rv vr R
= =+
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1Assist.Prof. Poenar Daniel Puiu
Tutorial 5: BJTs5.1. a) Measurements taken on a variety of transistors arefound to be incomplete (or possibly in error). Available data areas shown. Provide the missing data and calculations, and pointout inconsistencies if any.
abcdefghi
Device IC [mA] IB [mA] IE [mA] α β
10
0.6398
1010.10.99
0.02
0.0010.20.10.010.015
10.11.12
990.01110.110
0.9840.99
0.99
0.995
100
639810100
99193
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2Assist.Prof. Poenar Daniel Puiu
5.1.b) If the base voltage on an npn transistor is +5V withrespect to (w.r.t.) ground and the emitter voltage is +6V w.r.t.ground, is the base-emitter junction properly biased for linearapplications? Explain.
5.1.c) If the junction voltages in the following transistorhave the values listed, is it properly biased for linearapplications ? Si npn; VBE= –0.7V, VCB= 10V.
5.1.a) Device a: IE= IB+IC => IB= IE – IC = 0.1 mA. Solution:
ααβ
ββα
−=⇔
+=
11and, using the first relation, in this case we obtain α= 0.99.
Device b:IE=(β+1)IB =>
1.12 551 1 55 0.9820.02 1 56
E
B
II
ββ αβ
= − = − = ⇒ = = =+
Also, IC= IE–IB= 1.12–0.02= 1.1 mA. Alternatively, one can use IC=β.IB
We also know that
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3Assist.Prof. Poenar Daniel Puiu
0.63 0.0163
CB
II mAβ
= = =
Alternatively, one can do calculations using the relation IC=α.IE
Device d: (we can first check that α & β are correct: α=98/99≅0.99):
IC=β.IB => 98 198
CB
II mAβ
= = = OR IB= IE–IC = 1 mA.
Device e: IE=(β+1)IB =>0.0111 1 100.001
E
B
II
β = − = − = ⇒The value shown in Table is correct.10 0.9091
1 11βαβ
= = ≅+
IC=β.IB => IC= 10.0.001=0.01 mA and
Device f: IC=β.IB => 10 500.2
C
B
II
β = = = ⇒ Either the entry for β or that for
IB in the initial Table must be wrong. However, since we now that IE=IC+IBmust hold true, we can only assume that IB= 0.1 mA and β are correct =>
and IE=(β+1)IB => IE= =0.64 mA. IC=β.IB =>
Device c (we can first check that α & β are correct: α=63/64≅0.984):
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4Assist.Prof. Poenar Daniel Puiu
Device g: First, we should notice that in the Table IC>IE, which is animpossibility. For real devices the two values of the two currents must beswapped, i.e. the correct values are IC= 10 mA & IE= 10.1 mA. Then both IBand β values in the Table are correct and we can calculate α:
100 0.99011 101βαβ
= = ≅+
Device h: The value of either α or β in Table is incorrect. Since IC=β.IB =>β =IC/IB = 99 must be correct, and therefore the correct value of α is
99 0.991 100βαβ
= = =+
Then IE=(β+1)IB = 100.0.01=1 mA OR IE= IB+IC = 1 mA;OR IC=α.IE => IE= IC/α = 1 mA.
100 0.99011 101βαβ
= = ≅+
we can now check that the value of α is correct:
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5Assist.Prof. Poenar Daniel Puiu
5.1.b) VBE= VB–VE = 5–6= –1V. Consequently, the base-emitter (B-E)junction of the transistor is not properly biased for operation in the normalactive regime for linear & analog amplification. To enable such anoperation we must forward bias the B-E junction, i.e. VBE= 0.6…0.8 V(typically around 0.7V).
5.1.c) So we have a Si npn transistor with VBE= –0.7V, VCB= 10V. As inthe previous case, the base-emitter (B-E) junction of the transistor is notproperly biased as VBE<0.
2.895 0.9948.2.91
C
E
II
α⇒ = = =
Device i: From the values of IB & β it results that IC=β.IB => IC=193.0.015= 2.895 mA and IE= IB+IC = 2.91 mA. Then, from IC= α.IE =>
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6Assist.Prof. Poenar Daniel Puiu
5.2. For the circuits in Fig.5.2 find the labelled currents andvoltages. Let β=100 and IVBEI= 0.7 V.
VEE=+10 V
–VCC= –15 V
VBB= 0 V
RE = 5 kΩ
RC = 5 kΩ
VC
VEQ2
VCC=+10 V
–VEE= –10 V
RC = 10 kΩ
RE = 10 kΩ
VE
VCQ1
VBB= 0 V
IB
Fig.5.2:
IB
a) b)
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7Assist.Prof. Poenar Daniel Puiu
VBE= 0.7 V
VCC=+10 V
–VEE= –10 V
RC10 kΩ
RE 10 kΩ
VE
VCQ1
VBB= 0 V
IB
a)
Solution:IC
IE
By KVL around the GND-BE jct.-RE-VEE loop:
VBE+REIE= VEE => EE BEE
E
V VIR−
=
and for biasing in the active regime we must have VBE=0.7V, hence
10 0.7 0.9310
0.93 9.2 ;1 1010.9208
E
EB
C B
I mA
II A
I I mA
μβ
β
−= =
⇒ = = =+
= =VC= VCC –RCIC = 10 – 9.208= 0.792 V, and obviously VE= –VBE= –0.7 V => VCE= VC – VE= 1.492 V ≅ 1.5 V. Also VCB= VC – VB= VC = 0.792 V, i.e. C-B jct. is reverse biased, and, therefore, Q1 is indeed in the active regime.
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8Assist.Prof. Poenar Daniel Puiu
VEE=+10 V
–VCC= –15 V
VBB= 0 V
RE5 kΩ
RC5 kΩ
VC
VE
Q2
IB
b)
VEB= 0.7 V
By KVL around the GND-BE jct.-RE-VEE loop:
VBE+REIE= VEE => EE BEE
E
V VIR−
=
and for biasing in the active regime we must have VBE=0.7V, hence
10 0.7 1.865
1.86 18.42 ;1 101
1.842
E
EB
C B
I mA
II A
I I mA
μβ
β
−= =
⇒ = = =+
= =
IE
IC
VC= –VCC +RCIC = –15 + 9.208= –5.79208 V, and obviously VE= VEB= 0.7V=> VCE= VC – VE= –6.49208 V ≅ –6.5 V. Also VCB= VC = –5.8 V, i.e. theC-B jct. is reverse biased, and, therefore, Q2 is indeed in the active regime.
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9Assist.Prof. Poenar Daniel Puiu
5.3. The transistors in the circuits shown in Fig.5.3 have verylarge values of β, so we may assume the base currents to benegligibly small. If, in addition, it is determined bymeasurement that IVBEI=0.7V, find the values of the labelledvoltages.
VEE = +10 V
–VCC = –15 V
RE = 5 kΩ
RC = 5 kΩ
VC
VEQ2
VCC = +10 V
–VEE = –10 V
RC = 10 kΩ
RE = 10 kΩ
VE
VCQ1
VB
Fig.5.3:
a) b)
RB = 10 kΩ
VB
RB = 10 kΩ
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10Assist.Prof. Poenar Daniel Puiu
VBE= 0.7 V
VCC=+10 V
–VEE= –10 V
RC10 kΩ
RE 10 kΩ
VE
VCQ1VB
a)
RB 10 kΩ
IC
IE
We are given that β→∞ => IB=0 => IC ≅ IE. Additionally, IB=0 => RBIB=0 hence VB=0. Thus, since for biasing in the active regime we must have VBE=0.7V => VE= –0.7V =>
10 0.7 0.93 .10
E EEE
E
V VI mAR+ −
= = =
IC ≅ IE => VC = VCC – RCIC = 10–9.3= 0.7 V=> VCE= VC – VE= 1.4 V. Also VCB= VC – VB=VC = 0.7 V, i.e. the C-B jct. is reverse biased,and, therefore, Q1 is indeed in the activeregime.
Solution:
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11Assist.Prof. Poenar Daniel Puiu
VEE=+10 V
–VCC= –15 V
RE 5 kΩ
RC 5 kΩ
VC
VE
Q2
b)
VBRB 10 kΩ
VEB= 0.7 V
We are given that β→∞ => IB=0 => IC ≅ IE. Additionally, IB=0 => RBIB=0 hence VB=0. Thus, since for biasing in the active regime we must have VEB=0.7V => VE= +0.7V =>
10 0.7 1.86 .5
EE EE
E
V VI mAR− −
= = =
IC≅ IE => VC = –VCC + RCIC = –15+9.3= –5.7 V=> VCE= VC – VE= –6.4 V. Also VCB= VC = –5.7 V, i.e. C-B jct. is reverse biased, and,therefore, Q2 is indeed in the active regime.
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12Assist.Prof. Poenar Daniel Puiu
5.4. A single measurement indicates the emitter voltage of thetransistor in the circuit of Fig.5.4 to be 1V. Under theassumption that |VBE|=0.7V, what are VB, IB, IE, IC, β, and α?
VEE = +5 V
–VCC = –5 V
VB
RE 5 kΩ
RC5 kΩ
VC
VE
Q
Fig.5.4:
RB 20 kΩ
IB
VEB= 0.7 V
IE
IC
VB= VE –VEB = 1–0.7= 0.3 V, and obviously0.3 15 .20
BB
B
VI AR
μ= = =
Also VE+REIE= VEE => EE EE
E
V VIR−
=5 1 0.8
50.8 0.015 0.785 ;
52.333
E
C E B
C
B
I mA
I I I mAII
β
−⇒ = =
⇒ = − = − =
⇒ = =52.333 0.98125
1 53.333βαβ
⇒ = = ≅+
Solution:
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13Assist.Prof. Poenar Daniel Puiu
5.5. Identify whether the circuits in Fig.5.5 operate in theactive or saturation mode. What is the emitter voltage in eachcase? If active, what is the collector voltage? IVBEI=0.7V, β=100.
VCC=+6 V
RC3 kΩ
RE1.3 kΩ
VE
VCQ1
VBB= +2 V
Fig.5.5:
a)
VBE= 0.7 V
IB
IC
IE
Let’s start by assuming that Q1 is in the active regime => VBE= +0.7 V. It is evident that
VE= VBB – VBE= 1.3 V, and1.3 11.3 1
E EE B
E
V II mA IR β
= = = ⇒ =+
VC= VCC – RCIC = 6–3×0.99= 3.03 V⇒ VCB= VC – VBB= 3.03–2 = 1.03 V, i.e. theC-B jct. is reverse biased, and⇒VCE= VC – VE= 1.73 V.
Consequently, Q1 is indeed in the active regime.
1 9.9 0.99101B C BI A I I mAμ β⇒ = = ⇒ = =
Solution:
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14Assist.Prof. Poenar Daniel Puiu
VEE=+6 V
RE10 kΩ
RC10 kΩ
VC
VE
Q2
b)
VBB= +1 V
IB
VEB= 0.7 V
IE
IC
Assume that Q2 is in the active regime => VEB= +0.7 V. It is evident that VE= VBB+VEB= 1.7 V, and 6 1.7 0.43
10EE E
EE
V VI mAR− −
= = =
If we consider IC ≅ IE => VC= RCIE = 4.3 V⇒VCB= VC – VBB= 4.3–1= 3.3 V, i.e. C-B jct.is forward biased => Q2 is in the saturationregime NOT the active one, hence VCE==VCEsat= 0.3 V => VC= VE–VCEsat= 1.4 V=>VCB= 0.4 V (still forward biased). Noticethat these are very different values from those
previously obtained above when we started from the assumption that IC ≅IE. This shows clearly that that assumption was not correct, hence we mustrecalculate IC:
1.4 0.14 0.43 0.14 0.2910
CC B E C
C
VI mA I I I mAR
= = = ⇒ = − = − =
Fig.5.5(continued):
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15Assist.Prof. Poenar Daniel Puiu
VEE=+95 V
RE200 kΩ
RC20 kΩ
VC
VE
Q3
c)
VBB= –5 V
–VCC= –50 V
IB
VEB= 0.7 V
IE
IC
Assume that Q3 is in the active regime => VEB= +0.7 V. It is evident that VE= VBB+VEB= –4.3 V, and 95 ( 4.3) 0.4965
200EE E
EE
V VI mAR− − −
= = =
If we consider IC ≅ IE => VC= –VCC+RCIE =–50+9.93= –40.07 V => VCB= VC –VBB ≅ –35V, i.e. C-B jct. is reverse biased => Q3 is in theactive regime. Then we can make moreaccurate calculations:
0.4965 4.921 101
0.49158
EB
C B
II A
I I mA
μβ
β
= = =+
⇒ = ==> VC= –VCC+RCIC = –50+9.8316= –40.17 V=> VCB= VC – VBB≅ –35.17 V=> VCE= VC – VE= VCB – VEB ≅ –35.87 V.
Fig.5.5 (continued):
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16Assist.Prof. Poenar Daniel Puiu
VBE= 0.7 V
IB
IC
IE
–VCC= –10 V
–VEE= –30 V
RC2 kΩ
RE5 kΩ
VE
VCQ4
VBB= –20 V
d)
Assume that Q4 is in the active regime => VBE= +0.7 V. It is evident that VE= VBB–VBE= –20.7 V, and 20.7 30 1.86
5
18.4161
1.8416
E EEE
E
EB
C B
V VI mAR
II A
I I mA
μββ
+ − += = =
⇒ = =+
⇒ = =VC= –VCC + RCIC = –10 – 2×1.8416= –13.6832 V⇒ VCB= VC – VBB= –13.6832+20= 6.3168 V, i.e.the C-B jct. is reverse biased, and⇒ VCE= VC – VE= –13.6832+20.7=7.0168 ≅ 7 V.
Consequently, Q4 is indeed in the active regime.Fig.5.5 (continued):
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17Assist.Prof. Poenar Daniel Puiu
5.6. Find the voltages at all nodes and the currents throughall branches in the circuit of Fig.5. Assume that β=50 and the ICand VBE for the transistor is described by VBE=0.026.ln(IC/10–14).
VCC= +9 V
RC50 kΩ
RE30 kΩ
VE
VCQ1
Fig.5:
VBE= 0.7 V
IB
IC
IE
R11 MΩ
R2470 kΩ
Solution: We start by replacing the R1-R2 group connected to B with a
B
Thevenin equivalent source:
RC50 kΩ
RE30 kΩ
Q1
Vth
Rth=>
VCC= +9 V 2
1 2
0.479 2.8781 0.47
th CC
th
RV VR R
V V
= ⇒+
= ≅+
Rth=R1 | | R21 0.471 0.47⋅
= ≅+
0.31973 MΩ =319.73 kΩ.Vth= RthIB+VBE+REIEwith IE= (β+1)IB =>
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18Assist.Prof. Poenar Daniel Puiu
( ) ( )1 1th BE th BE
B Cth E th E
V V V VI IR R R R
ββ β− −
⇒ = ⇔ =+ + + +
However, we cannot assume automatically VBE= 0.7V, since the problem’shypothesis already indicated that
14ln10
CBE T
IV V −=
It is now obvious that these two equations will have to be solved iteratively:
Eqn.(1)(Calc.IC ; in [mA])
Eqn.(2)(Calc.VBE ; in [V]) 0.7 0.585 0.586 0.586
59×10–3 62×10–3 62×10–3Iteration 1 Iteration 2 Iteration 3 Iteration 4
Guessvalue No more variation from
one step to another: STOP
(1)
(2)
Hence, we now have IC ≅ 0.062 mA and VBE ≅ 0.585 V.
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19Assist.Prof. Poenar Daniel Puiu
1 51 0.062 0.0632450
CE E C
II I I mAβα β
+= ⇔ = = =
and IB=IC/β= 0.06324/50 = 1.2648 μA;VE= REIE = 0.06324×30= 1.8972 V => VB= VE+VBE = 2.5972 V,and VC= VCC–RCIC = 9–50×0.06324= 5.838 V => VCB= VC–VB ≅3.24V, hence the C-B jct. is reverse biased, and consequently, Q1is indeed in the active regime.VCE= VC – VE= 5.838 – 1.8972 ≅ 3.94 V.
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1Assist.Prof. Poenar Daniel Puiu
6.1- A certain NMOS fabrication process yields Kn’ = 50 μA/V2
and VTN= 1 V. Determine the width-to-length ratio needed if it isrequired that IDS= 0.5 mA when VGS= VDS= 5 V. State anyassumption made.
Tutorial 6: MOSFETs
Solution: We first need to determined the operation regime/region.Since VGS>VTN and VDS ≥ VGS–VTN= 4V => the NMOS transistor operates inthe saturation region. Consequently, we can use the corresponding equationdescribing the transistor’s operation in this region, assuming that thechannel length modulation factor λ=0:
( )2
2n
DS GS TNKI V V= ⋅ − where n n ox
WK CLμ= is the transistor gain factor
( ) 2 222 1 0.0625 62.5
16DS
nGS TN
I AmAK V VV Vμ⇒ = = = =
−62.5' 1.25
' 50n
n nn
W W KK KL L K
= ⇒ = = =Because
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2Assist.Prof. Poenar Daniel Puiu
6.2- Two points in the saturation region of an NMOS transistorare: (VGS1= 2 V and IDS1= 0.5 mA) and (VGS2= 3 V and IDS2= 2 mA).Assuming λ=0 find the values of VTN and Kn.Solution:saturation region, we can use the corresponding equation describing thetransistor’s operation in this region, again assuming that the channel lengthmodulation factor λ=0:
As we know clearly that the NMOS transistor operates in the
( )2
2n
DS GS TNKI V V= ⋅ −
and inserting in it the data for the two points we derive a system of twoequations with two unknowns:
( )( )
( )( )
2 21 1 11
222 22 2
2
2DS n GS TN GS TNDS
DS GS TNDS n GS TN
I K V V V VII V VI K V V
⎧ = ⋅ − −⎪ ⇒ =⎨−= ⋅ −⎪⎩
( ) ( )11 2 2
2
DSGS TN GS TN GS TN
DS
IV V V V a V VI
⇔ − = − ⋅ = ⋅ −
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3Assist.Prof. Poenar Daniel Puiu
( ) 2 12 1 1
1GS GS
GS GS TN TNaV VaV V a V V
a−
⇔ − = − ⋅ ⇔ =−
In our case 1
2
0.5 0.5 3 20.5 1 .2 0.5 1
DSTN
DS
Ia V VI
⋅ −= = = ⇒ = =
−
We can now introduce this value in one of the eqn.s and find Kn:
( ) ( )2
22 22
2 4 13 1
DSn
GS TN
I mAK VV V= = =
− −
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4Assist.Prof. Poenar Daniel Puiu
6.3- Two points on the characteristic curve for VGS= 3 V of anNMOS transistor are: (VDS1= 5 V and IDS1= 1 mA) and (VDS2= 10 Vand IDS2= 1.25 mA), and VTN= 1 V. Determine the value of λ.Solution: Obviously, now we must consider the equation describing thetransistor’s operation in the saturation region without neglecting thechannel length modulation factor λ:
( ) ( )2 12
nDS GS TN DS
KI V V Vλ= ⋅ − ⋅ +
and inserting in it the data for the two points we derive a system of two
( ) ( )( ) ( )
21 1
22 2
2 1
2 1DS n GS TN DS
DS n GS TN DS
I K V V V
I K V V V
λ
λ
⎧ = ⋅ − ⋅ +⎪⎨
= ⋅ − ⋅ +⎪⎩
equations withtwo unknowns,λ and Kn:
1 1 1
2 2 2 2 1
1 1 11 1
DS DS DS
DS DS DS DS DS
I V V bbI V V bV V
λ λ λλ λ
+ + −⇒ = ⇔ = ⇔ =
+ + −
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5Assist.Prof. Poenar Daniel Puiu
In our case 11
2
1 1 0.80.8 0.066671.25 0.8 10 5
DS
DS
Ib VI
λ −−= = = ⇒ = =
⋅ −We can now introduce this value in one of the eqn.s and find Kn:
( ) ( )
( ) ( )
12
1
22
212 1 0.375
3 1 1 0.06667 5
DSn
GS TN DS
n
IKV V V
mAK V
λ=
− ⋅ +
⋅⇒ = =
− ⋅ + ⋅
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6Assist.Prof. Poenar Daniel Puiu
6.4- Given VTN= 1 V, λ=0 and Kn= 0.5 mA/V2, check if the NMOStransistor in Fig.6.4 is operating in the saturation region anddetermine IDS and VDS.
VDD= +15 V
–VSS= –15 V
IDS
RD1 kΩ
RG1 MΩ
Q1
RS3 kΩ
Fig.6.4:
Solution: For any MOSFET transistor it is usually safe to consider thatIG=0 => VG=0 and by KVL in the RG-VGS-RS-VSS loop:VG=0 =VGS+RSIDS–VSS => VGS= VSS–RSIDS . We assumethat the transistor operates in the saturation region,again considering a channel length modulation factorλ=0:
VGS ( )2
2n
DS SS S DS TNKI V R I V⇒ = ⋅ − −
and introducing in it the 1st eqn. above we obtain:
( )2
2n
DS GS TNKI V V= ⋅ −
which is a 2nd
order eqn. in IDS that we need to solve. Inserting thevalues results in: IDS=0.25.(15–3IDS–1)2 <=>9IDS
2–88IDS+196=0 =>
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7Assist.Prof. Poenar Daniel Puiu
2
1,2 1 288 88 4 9 196 6.346 ; 3.4317
18DS DS DSI I mA I mA± − ⋅ ⋅= ⇒ = =
We need to choose the solution which validates our initial assumption ofworking in the saturation regime. In order to do this analysis we mustcalculate first VGS, then VDS, and compare the latter with VGS–VTN.
From the circuit it is clear that VDD+VSS=(RD+RS)IDS+VDS =>VDS= VDD+VSS – (RD+RS)IDS
For the first IDS solution:VGS= VSS–RSIDS= 15–3×6.346= –4.038 V <<VTN !! Obviously, this is anunrealistic value since it would not allow the transistor to conduct current.
For the second IDS solution:VGS= VSS–RSIDS= 15–3×3.4317= 4.705 V => VGS–VTN= 3.705 V.VDS= 30–4×3.4317= 16.27 V > VGS–VTN hence this second solutiondescribes correctly the operation of the transistor in the saturation regime.
In conclusion, the quiescent D.C. operating point is at VDS=16.27 Vand IDS= 3.43 mA.
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8Assist.Prof. Poenar Daniel Puiu
6.5. Given VTN= 4 V, λ=0 and Kn=2 mA/V2, repeat problem 4 forthe circuit shown below in Fig.6.5.
VDD= +20 V
IDS
RD1 kΩ
RG21 MΩ
Q1
RS1 kΩ
Fig.6.5:
Solution:
VGS
RG11 MΩ
Again we consider that IG=0 => VG is established solely by the resistive potential divider formed by RG1 and RG2 at avalue VG=VDD/2= +10 V. By KVL in the VG-VGS-RS-GND loop: VG= VGS+RSIDS–VSS =>VGS= VSS–RSIDS+VG<=>VGS=10–IDS. We assume that the transistoroperates in the saturation region, again taking λ=0:
VG
( )2
2n
DS GS TNKI V V= ⋅ − and introducing in it the 1st
eqn. above we obtain:( )2
2n
DS SS S DS G TNKI V R I V V⇒ = ⋅ − + − which is a 2nd
order eqn. in IDS that we need to solve. (Alternatively,we can express IDS as a function of VDS and solve forthe latter). Inserting the values results in:IDS= (10–IDS–4)2 <=> IDS
2–13IDS+36=0 =>
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9Assist.Prof. Poenar Daniel Puiu
2
1,2 1 213 13 4 36 9 ; 4
2DS DS DSI I mA I mA± − ⋅= ⇒ = =
We need to choose the solution which validates our initial assumption ofworking in the saturation regime. In order to do this analysis we mustcalculate first VGS, then VDS, and compare the latter with VGS–VTN.
From the circuit it is clear that VDD=(RD+RS)IDS+VDS =>VDS= VDD – (RD+RS)IDS
For the first IDS solution:VGS= 10–IDS= 10–9= 1 V < VTN= 4 V!! Obviously, this is an unrealisticvalue since it does not allow the transistor to conduct current (cut-off).
For the second IDS solution:VGS= 10–IDS= 6 V => VGS–VTN= 2 V.VDS= 20–2×4= 12 V > VGS–VTN hence this second solution describescorrectly the operation of the transistor in the saturation regime.
In conclusion, the quiescent D.C. operating point is at VDS=12 Vand IDS= 4 mA.
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10Assist.Prof. Poenar Daniel Puiu
VSD
6.6. Find the quiescent point of the PMOS transistor in Fig.6.6given that VTP= –2V and Kp=100 μA/V2.
VSS= +12 VIDS
RG1 MΩ Q1
RD100 kΩ
Fig.6.6:
Solution:
VGS
Again we consider that IG=0 => VG=VD=RDIDS. ByKVL, VSS=RDIDS+VSD => VSD= VSS – RDIDS (1).Because the drain and the gate have the samepotential => VGS= VDS= –VSD=> the condition|VDS|=|VGS|≥|VGS|–|VTP| is satisfied and therefore thetransistor is certainly operating in the saturation
region. Hence,
VG
VD ( )2
2p
DS GS TP
KI V V= ⋅ −
and after introducing in it eqn.(1) above rewritten
in the form we obtain:12100
SS SD GSDS
D
V V VIR− +
= =
( )2 212 100 0.05 2 5 19 8 0GS GS GS GSV V V V+ = ⋅ ⋅ − ⇔ − + =
T6
11Assist.Prof. Poenar Daniel Puiu
2
1,2 1 2
19 19 4 8 5 0.4823 ; 3.31810GS GS GSV V V V V± − ⋅ ⋅
= ⇒ = =
Evidently, only the second value has real physical meaning since the firstone is below the threshold: |VGS1|<|VTP| and would therefore place thetransistor in cut-off, not in saturation.
Finally, we can deduce VDS= VGS= –3.318 V and the correspondingcurrent is 12 12 3.318 86.82 .
100 100GS
DSVI Aμ+ −
= = =
T6
12Assist.Prof. Poenar Daniel Puiu
6.7. Determine the region of operation for the transistor inFig.6.7 given that VTP= –1 V and Kp= 250 μA/V2.
VSD
VSS= +4 VIDS
Q1
RD1.6 kΩ
Fig.6.7:
Solution:
VGSVG
Clearly VG=0 => VGS= –VSS= –4V, and we assume thatthe transistor operates in the saturation region, againconsidering a channel length modulation factor λ=0:
( ) ( )2 20.125 4 1 1.125 .2
pDS GS TP
KI V V mA= ⋅ − = − =
At the same time VSS= RDIDS+VSD =>VSD= VSS – RDIDS= 4 – 1.6×1.125 = 2.2 V =>|VDS|=2.2 < |VGS|–|VTP|=3 V => our initialassumption of operating in the saturation regimeis not correct. At the same time, we notice that|VGS|>|VTP|, hence the device can be only in thelinear (triode) region =>
( ) 22 2DS p GS TP DS DSI K V V V V⎡ ⎤= ⋅ − −⎣ ⎦ and SS SDDS
D
V VIR−
=
T6
13Assist.Prof. Poenar Daniel Puiu
and inserting the values results in:4–|VDS|=1.6×2×0.25×[2 ×(4–1)×|VDS|–|VDS|2] <=> 0.8|VDS|2–5.8|VDS|+4=0 =>
2
1,2 1 2
5.8 5.8 4 4 0.8 0.7718 ; 6.4781.6DS DS DSV V V V V± − ⋅ ⋅
= ⇒ = =
Obviously only the first value has real physical meaning since only thisvalue satisfies the condition |VDS|<|VGS|–|VTP|=3 V necessary for operatingin the linear regime. Consequently,
4 0.7718 2.018 .1.6
SS SDDS
D
V VI mAR− −
= = =
T2Author: Assist. Prof. Poenar Daniel Puiu
1
AnalogueElectronics (EE2002)
Office: S2.2-B2-06Tel.: 6790 4237E-mail: [email protected]
Assistant Professor Poenar Daniel Puiu
-Addition to TUTORIAL 7-
T2Author: Assist. Prof. Poenar Daniel Puiu
2
Recapitulation:
Bipolar transistors(continued):Input and outputcharacteristics inamplification
ICQ
VCEQ
VCE [V]
I C [A
]
ibe(t)t
VCC
tvce(t)
RC
VCC
IB=0.01 μA
VA (Early voltage → due tobase width modulation)
Saturation
Cut-off
Max. power dissipation
(1+β)RE
VB
IBQ
VBEQ VBE [V]
qVBEmkTIBE=IS
.exp( )
t
ib(t)IB [A]
vbe(t)t
VCC
T2Author: Assist. Prof. Poenar Daniel Puiu
3
Recapitulation (continued):Bipolar transistors (continued): Single-stage Amplifier Configurations
a) Common emitter:A= moderate (tens)
Zin= moderateZout= moderate
b) Common collector (Emitter follower):
A≅1Zin= highZout= low
VCC
VBB
ICRCRBA.C. in
A.C.out
VCC
VBB
ICRCRBA.C. in
A.C.out
RE
T2Author: Assist. Prof. Poenar Daniel Puiu
4
c) Common base:A≅ moderate
Zin= lowZout= highCin=low
vout
A.C.out
A.C. in
vinAmplifier
(gain=AV= )
Energy (D.C. supply)
in
out
vv
VCC
VBB
IC
RC
RB
A.C. in
A.C.out
RE
Recapitulation (continued):
T2Author: Assist. Prof. Poenar Daniel Puiu
5
• To determine Routput:– Remove the load RL and replace
it with a voltage source vx at the output terminals;
– Note with ix the current due to vx (which is provided by the new voltage source);
– At the same time, passivate the input signal source (vi or ii);
– R0 = vx/ix
Recapitulation (continued):
•To determine Rin:–Apply a voltage source vxat the (input) terminalswhere Rin is to be measured;–Note with ix the current due to vx (which is provided by the new voltage source);–Rin = vx/ix
T2Author: Assist. Prof. Poenar Daniel Puiu
6
Recapitulation (continued):Input resistance asseen from the emitter:
vxie
Rin=re
vbe
ixe
E
T
e
bein r
IV
ivr ===
What is VT? VT is the so-called thermal voltage:
[ ] [ ]119
23
647.381875.25][106.1
][300][1038.1 −−
−
≅⇒≅⋅
⋅⋅== V
VmV
CKJ
qkTV
TT
Input resistance asseen from the base:
( ) emB
T
b
bein r
gr
IV
ivr ⋅+===== 1ββ
π
vx
ix
Rin=rπ
vbe
mme gg
r 1≅=
α
=>
T2Author: Assist. Prof. Poenar Daniel Puiu
7
The simplified equivalent A.C. hybrid small signal model of a transistor:
rπ gmvbe
B
E
Cvbe [ ]( ) e
mB
T
b
be
CC
m
rgI
Vivr
VmAI
qkTIg
⋅+===≡
≈=
1
;38/
ββπ
rπ
gmvbe
B
E
C
vbero
Cπ
Cμ
C
Ao I
Vr = where VA= the Early voltage
BOTH npn & pnp transistors have the same A.C. small signal model !!!
The equivalent A.C. hybrid small signal model of a transistor:Recapitulation (continued):
T2Author: Assist. Prof. Poenar Daniel Puiu
8
C
FE
FE
C
FE
B
Cfe
dIdh
hIh
dIdIh
⋅−=≡
1
For a transistor with hFE= independentof current β≡=⇒ FEfe hh
The relevant small-signal current gain hfe is:
Another simplified equivalent A.C. hybrid small signal model:
rπ hfeib
B
E
CibHowever, in practice, this approximationdoes not always hold:
β
IC (log scale)
Recapitulation (continued):
T2Author: Assist. Prof. Poenar Daniel Puiu
9
Other simplified equivalent A.C. hybrid small signal models:
The T-models (looking fromthe emitter!)
0) Identify parts of schematics which canbe simplified (e.g. have a specific function) or discarded!
1) Very careful DC analysis => VCE, IC=> 1.A) CHECK IF TRANSISTORS ARE
IN ACTIVE REGIME !!1.B) Calculate gm, rπ, etc.
2) Simple AC analysis:2a) Passivate the DC sources;2b) Consider the relevant capacitors;2c) Redraw the schematics for a.c.2d) Replace transistors by a
simplified equivalent a.c. model;2e) Calculate A, Rin, Rout.
3) Complete A.C. analysis: full model and with all the capacitors, including feedback.
A.C. Problem Solving Procedure:
αie
iere
B
E
C
ib
re
gmvbeB
E
C
vbe
ib
T8
1Assist.Prof. Poenar Daniel Puiu
8.1- (a) A circuit is to be biased at a current of 10 mA andachieve an input resistance of at least 1 MΩ. Should a BJT orMOSFET be chosen for this circuit and why?
(b) A circuit requires the use of a transistor with atransconductance of 0.5 S. A bipolar transistor with β= 60 and aMOSFET with Kn= 25 mA/V2 are available. Which transistorwould be preferred and why?
(c) A common-emitter amplifier has a gain of 50 dB and isdeveloping a 15 V peak-to-peak A.C. signal at its output. Is thisamplifier operating within its small-signal region? If the inputsignal to this amplifier is a sine wave, do you expect the outputto be distorted? Explain your answer.
Tutorial 8: A.C. circuits with MOSFETs & BJTs (2)
Solution:current, a MOSFET should be used. If a BJT were selected, it would bevery difficult to achieve the required input resistance because its value ofrπ is low (assume we have a β= 100 for the BJT):
a) Since a relatively high RIN is required at a relatively high
T8
2Assist.Prof. Poenar Daniel Puiu
3
3
100 25.875 10 258.75 10 10
T
m C
Vrg Iπβ β −
−
⋅ ×= = = = Ω
×
b) For the BJT:
For the MOSFET:
30.5 25.875 10 12.94 13 C m TI g V mA mA−= = ⋅ × = ≈( )
( )22
3
0.55
2 2 25 10m
dn
gI A
K −= = =
×
The results clearly indicate that the BJT can achieve the requiredtransconductance at a current 400× lower than that of the MOSFET ! For agiven power supply voltage, a BJT will therefore use 400 times less power.It should be noted, however, that –as we have just seen above- that rπ issmall for BJT. In this particular case:
60 120 0.5m
rgπβ
= = = Ω versus ∞ (theoretically; practically =RG∝MΩ) for the MOSFET.
T8
3Assist.Prof. Poenar Daniel Puiu
c) We know that for the small-signal operation of a BJT the followingcondition must be obeyed: vbe<<2VT. As usual, let’s consider that afactor of 10 difference between the quantities is sufficient to replace theinequality: |vbe|≤0.2VT = 5 mV.
Since we are given both the gain and the output signal, we cancalculate the actual input signal amplitude and check if it satisfies the aboverequirement: [ ]
20
5020
[ ] 20log 10
10 316.22815| | 47.43 5
316.228
VA dB
V V V
V
OUT ppbe
V
A dB A A
AV
v mV mVA
−
= ⇒ =
⇒ = =
⇒ = = = >>
Consequently, the input signal is far too large to be considered as “smallsignal”. Therefore, significant distortion of the sine wave will occur.
T8
4Assist.Prof. Poenar Daniel Puiu
8.2- The amplifier in Fig.8.2 is the common-emitter amplifiercircuit discussed in the lecture, with the same transistorparameters (β= 65 and VA= 50 V), except that the currents havebeen reduced by a factor of approximately 10. What are thevoltage gain, input resistance and output resistance of thisamplifier?
VCC= +5 V
R11 MΩ
RC100 kΩ vout
C3=∞
RE160 kΩ C2=∞
C1=∞vin Q1
RS0.33 kΩ R3
220 kΩ
–VEE= – 5 VFig.8.2:
Solution:with Problem 7.2 of theprevious tutorial.As usual, we must start firstwith:S1) D.C. analysis: In order tosimplify our calculations wecan use a simpler equivalentcircuit:
The problem is very similar
T8
5Assist.Prof. Poenar Daniel Puiu
VBE=0.7 V
VCC = +5 VRC
100 kΩ
RE=160 kΩ
Q1
–VEE = – 5 V
R11 MΩ
IB
IC
IE
We can only continue by assuming that Q1 isworking in the ACTIVE regime => VBE=0.7 V =>VEE = IBR1 + VBE + (β +1)IBRE =>
( )
( )
1
4
4
4
5 0.71 1000 66 160
3.72 10 372
65 3.72 10 24.1782 ;
1 66 3.72 10 24.55
EE BEB
E
B
C B
E B
V VIR R
I mA nA
I I mA A
I I mA A
β
β μ
β μ
−
−
−
− −⇒ = =
+ + + ⋅
⇒ = × =
⇒ = = ⋅ × =
⇒ = + = ⋅ × =
VC= VCC –RCIC = 5 –100×24.1782×10–3 ≅ 2.582 V andVB= –R1IB = –1000×3.72×10–4= –0.372 V <<VC. Consequently, the C-Bjunction is reverse biased, hence our initial assumption of working in theactive regime is valid.VCE= VCC+VEE –RCIC –REIE= 10 –100× 24.1782×10–3 –160×24.55×10–3
⇒ VCE= 3.654 V.
Fig.8.2-A:
T8
6Assist.Prof. Poenar Daniel Puiu
Hence the quiescent operating point is:(24.1782 μA; 3.654 V).
S2) Simple small signal A.C.analysis: Passivate D.C. sources, consideronly relevant capacitors (in this case all ofthem have zero reactance), redraw theschematics for A.C.:
R11 MΩ
RC100 kΩ vout
vin Q1
RS0.33 kΩ R3
220 kΩ
Now we can replace the transistor with its equivalent small signal A.C.model:
rπ
gmvbe
B
E
Cvbe
R11 MΩ
RC100 kΩ
voutvin
RS0.33 kΩ
R3220 kΩ
which can be re-drawn in a more convenient form:
rO
RIN
ROUTFig.8.2-C:
Fig.8.2-B:
T8
7Assist.Prof. Poenar Daniel Puiu
vin vbe
RL= RC | | R3 | | rO66.684 kΩ
vout
gmvbe
Rbe=R1| |rπ65.0375 kΩ
RS= 0.33 kΩ
IC = 24.1782×10–3 mA => gm= 38.467× 24.1782×10–3 ≅ 0.9344 mA/V and rπ= 65/0.9344 = 69.56163 kΩ => Rbe= R1 | | rπ = 65.0375 kΩ.
3
3
50 +3.654 2219.1064 24.1782 10
| | | | 66.684
A CEo
C
L C O
V Vr kI
R R R r k
−
+= = = Ω ⇒
×⇒ = = Ω
vout= –gmvbeRL and be bebe in out m L in
be S be S
R Rv v v g R vR R R R
= ⇒ = − ⋅+ +
65.0375 66.6840.9344 6265.0375 0.33
out be LV m
in be S
v R RA gv R R
⋅⇒ = = − = − ⋅ ≅ −
+ +
Fig.8.2-D:
T8
8Assist.Prof. Poenar Daniel Puiu
Looking at the previous circuit in Fig.8.2-D it becomes clear thatRIN= Rbe ≅ 65.04 kΩ, and ROUT= RC | | rO = 95.68 kΩ.
8.3- Draw the small-signal equivalent circuit of the common-emitter amplifier in Fig.8.3. What are the voltage gain, inputresistance, output resistance and current gain if gm= 20 mS, β=75 and ro= 100 kΩ?
RB15 kΩ
vOUT
vin Q1
RS0.5 kΩ RC
12 kΩ
RE0.2 kΩ
Fig.8.3:
Solution:the transistor with its equivalent smallsignal A.C. model:
We begin by directly replacing
T8
9Assist.Prof. Poenar Daniel Puiu
rπ
gmvbeB
E
Cvbe
RB15 kΩ
vOUTvin
RS=0.5 kΩ
RC12 kΩ
rORIN
ROUTRE
0.2 kΩgm= 20 mA/V => rπ= 75/20 = 3.75 kΩ rO= 100 kΩ
so that we can focus our attention only on the right-hand circuit with vIN1 asinput. It is also evident that the presence of rO will significantly complicatecalculations. Therefore, it is very relevant to establish what is the influenceof rO on the final results. For this purpose we shall examine BOTH cases,
and obviously RIN= RIN1 | | RB.1IN
IN inS IN
Rv vR R
=+
RIN1
vIN1
We can simplify our study of the circuit if we consider first the influence of RS and RB:
Fig.8.3-A:
ibeiE
iC
vE
iiniB
T8
10Assist.Prof. Poenar Daniel Puiu
without and with rO, respectively. Let’s start with the simpler one, in whichwe neglect the presence of rO:
RE gmvbe
RCvOUT
rπibevIN1
vbe
iEiC
iC
vE
iC= gmvbe => vOUT= –RCiC= –RC gmvbeandiE= iC + ibe= gmvbe+vbe/rπ= ( )1 bev
rπβ +
At the same timevIN1= vbe + vE = vbe + REiE <=>
( )1 1 1 EIN be
Rv vrπ
β⎡ ⎤
= + +⎢ ⎥⎣ ⎦
( ) ( )11
1
11 1
75 12 47.53.75 76 0.2
OUT C m CV
EIN E
V
v R g RA Rv r Rr
A
π
π
βββ
− −⇒ = = =
+ ++ +
− ×⇒ = ≅ −
+ ×and
(1)Fig.8.3-B:
T8
11Assist.Prof. Poenar Daniel Puiu
11
11
1 1
IN IN IN inIN in
S IN OUT S IN OUT
IN INV V
V S IN V S IN
R v R vv vR R v R R v
R RA AA R R A R R
= ⇒ = ⋅ ⇔+ +
= ⋅ ⇔ = ⋅ ⇒+ +
11
ININ
be
vRi
= and inserting eqn.(1) and ibe= vbe/rπ in this relation =>
( )( )1
1 11
Ebe
IN Ebe
Rvr
R r Rvr
ππ
π
ββ
⎡ ⎤+ +⎢ ⎥
⎣ ⎦⇒ = = + +
=>RIN1= 3.75+76×0.2= 18.95 kΩ. Hence the overall input resistance is:RIN= RIN1 | | RB = 18.95 | | 15 ≅ 8.373 kΩ.
Now we can finally calculate the total voltage gain.
Since
T8
12Assist.Prof. Poenar Daniel Puiu
OUTI
IN
iAi
= (2)The current gain is evidently defined as:
1 18.373 0.94365 44.82
0.5 8.373V V VA A A⇒ = ⋅ ≅ ⋅ = −+
with iOUT= – gmvbe and, looking on the initial circuit in Fig.8.3-A, we can
write 1 1 11
1 1
,IN IN IN BIN IN
B IN IN B
v v R Ri vR R R R
+= + =
⋅in which we introduce (1):
( ) ( )( )
( )
11 1
1
1
E BEIN be
E B
E BIN be
B
r R RRi vr r R R
r R Ri v
r R
π
π π
π
π
ββ
β
β
+ + +⎡ ⎤= + + ⋅ ⇔⎢ ⎥ + + ⋅⎡ ⎤⎣ ⎦ ⎣ ⎦
+ + += ⋅
⋅Using this relation together with the expression of iOUT and inserting them in eqn.(2) we finally obtain AI:
T8
13Assist.Prof. Poenar Daniel Puiu
( )75 15 33.14
1 3.75 76 0.2 15OUT B
I IIN E B
i RA Ai r R Rπ
ββ
− − ×= = ⇒ = ≅ −
+ + + + × +The only parameter we still need to calculate is ROUT. Let’s remember whatis the exact detailed procedure of calculating ROUT in ANY circuit:
- Remove the load RL and replace it with a voltage source vX atthe output terminals;- Note with iX the current due to vX (i.e. the current which isprovided by the new voltage source);- At the same time, passivate the input signal source (vin or iin);- ROUT = vX/iX
If we apply the same procedure, the modified circuit from which weneed to calculate ROUT is:
vX
iX
RE gmvberπibe
vbe
iE
RS | | RB=RSB vEFig.8.3-C:
T8
14Assist.Prof. Poenar Daniel Puiu
From Fig.8.3-C we can deduce the following relations:
iX= – gmvbe and vE= –vbe –RSBibe
( ) ( )1 EbeE E E E be m be E m be be
Rvv R i R i g v R g v vr rπ π
β +⎛ ⎞= = + = + =⎜ ⎟
⎝ ⎠
1 SBbe
Rvrπ
⎛ ⎞= − +⎜ ⎟
⎝ ⎠while at the same time
From these last two relations it results that
( )1 1 0SB Ebe
R Rvr rπ π
β⎡ ⎤
+ + + =⎢ ⎥⎣ ⎦
and therefore the only possible solution is vbe=0 => iX=0 =>ROUT = ∞ !!!Indeed, theoretically this is correct since the C-B junction is reverse
biased, hence it should always provide an ideal infinite resistance.Practically, however, it is evident that this result is not realistic, and moredetailed calculations need to be performed, now taking rO into account.
T8
15Assist.Prof. Poenar Daniel Puiu
For the sake of comparison, we repeat all previous calculations. The circuit to be considered in this case is obtained from Fig.8.3-A re-drawn in a more convenient form:vIN1
rπ
RE
gmvbe
RC
vOUT
rO
iC
iC
vbeibe
iO
Fig.8.3-D:
vIN1= vbe + vE (3)vE= vO + vOUT (4) and vE= REiE (5).Also iC= gmvbe + iO => iO= iC – gmvbe (6)
vOvE
(6 ')OUTO m be
C
vi g vR
⇔ = − −
Using (6’) in a re-written form of (4) gives vE= rOiO + vOUT <=>
1 (7)
OUTE O m be OUT
C
OE OUT m O be
C
vv r g v vR
rv v g r vR
⎛ ⎞⇔ = + +⎜ ⎟
⎝ ⎠⎛ ⎞
⇔ = + +⎜ ⎟⎝ ⎠
iE
T8
16Assist.Prof. Poenar Daniel Puiu
It is also evident thatbe out
E be CC
v vi i ir Rπ
= + = − which we can insert in (5)
( ) (8).be OUTE be C E E
C
v vv i i R Rr Rπ
⎛ ⎞⇒ = + = −⎜ ⎟
⎝ ⎠Now we can eliminate vE by equating (7) with (8):
1
(9).
O be OUTOUT m O be E
C C
C O Ebe OUT
C E O
r v vv g r v RR r R
r R r Rv vR R r
π
π
β
⎛ ⎞ ⎛ ⎞⇒ + + = − ⇔⎜ ⎟ ⎜ ⎟
⎝ ⎠ ⎝ ⎠+ +
⇔ = ⋅−
By introducing the expression of vbe as given by (9) into (7) we obtain theexpression of vE as a function of vOUT:
1 O C O EE OUT m O OUT
C C E O
r r R r Rv v g r vR R R r
π
β⎛ ⎞ + +
⇒ = + + ⋅ ⋅ ⇔⎜ ⎟ −⎝ ⎠
T8
17Assist.Prof. Poenar Daniel Puiu
( )( )
1(10).E C O
E OUTC E O
R R rv v
R R rβ
β+ +⎡ ⎤⎣ ⎦⇔ =
−Having now obtained the
expressions of vbe and vE by eqn.s (9) & (10), we can replace them ineqn.(1): ( )
( )( ) ( )
( )( )
( ) ( )( )
( ) ( )
1
1
1
1
1
1
(11)1
12 7500 0.246.315
3.75 12 0.2 100 0.2 7600 12
E C OC O EIN be E OUT OUT
C E O C E O
C O E E C OIN
OUT C O E
C O EV
C O E E C O
V
R R rr R r Rv v v v vR R r R R r
r R r R R R rvv R r R
R r RA
r R r R R R r
A
π
π
π
ββ β
ββ
ββ
+ +⎡ ⎤+ + ⎣ ⎦= + = ⋅ + ⇔− −
+ + + + +⎡ ⎤⎣ ⎦⇔ = − ⇔−
−= − ⇒
+ + + + +⎡ ⎤⎣ ⎦−
⇒ = − = −+ + + +
.
T8
18Assist.Prof. Poenar Daniel Puiu
We must now determine RIN1 in order to calculate the overall AV and RIN:1 1
1IN IN
INbe be
v vR ri v π= = and using eqn.(9) to insert the expression of vbe in
this relation =>
( )( )
( )
( )
11
11
1
1
12 7500 0.21 17.32 .46.315 12 0.2 100
ININ
C O EOUT
C E O
C O EIN
V C O E
IN
v rRr R r R
vR R r
R r RR
A R r R
R k
π
π
β
β
⇒ = − ⇔+ +
⋅−
−⇔ = − ⋅ ⇒
+ +
−⇒ = ⋅ = Ω
+ +Hence the overall input resistance is:
RIN= RIN1 | | RB = 17.32 | | 15 ≅ 8.038 kΩ.Now we can finally calculate the total voltage gain:
T8
19Assist.Prof. Poenar Daniel Puiu
1 18.038 46.315 0.9414 43.6
8.038 0.5IN
V V V VS IN
RA A A AR R
= ⋅ ⇒ = ⋅ ≅ − ⋅ = −+ +
OUTI
IN
iAi
=The current gain is:
at the initial circuit in Fig.8.3-A, we can write
( )| |be be E EIN be B be B
B B
v v v vi i i v r Rr R Rππ
+= + = + = +
We use again eqn.s (9) & (10) and introduce the expressions of vbe and vE inthe relation above, resulting in:
( )( )
( ) ( ) ( )( )
1
1
E C OB C O E OUTIN OUT
B C E O B C E O
B C O E E C OIN OUT
B C E O
R R rr R r R r R vi vr R R R r R R R r
r R R r R R R ri v
R R R r
π π
π
π
ββ β
ββ
+ +⎡ ⎤+ + + ⎣ ⎦= ⋅ ⋅ + ⇔− −
+ + + + + +⎡ ⎤⎣ ⎦⇔ = ⇒−
and, lookingwith OUTOUT
C
viR
= −
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20Assist.Prof. Poenar Daniel Puiu
( )( ) ( ) ( )
( )( ) ( ) ( )
1
15 7500 0.231.024
15 3.75 12 0.2 100 0.2 12 7600
B O EI
B C O E E C O
I
R r RA
r R R r R R R r
A
π
ββ
−= − ⇒
+ + + + + +⎡ ⎤⎣ ⎦− −
⇒ = ≅ −+ + + + +
Again, the only parameter we still need to calculate is ROUT. The modifiedcircuit from which we need to calculate ROUT is:
vX
iX
RErπibe iE
RS | | RB=RSB vE
Fig.8.3-E:
vbe
gmvberO
iX
iO
vO
From this circuit we canextract/deduce thefollowing relations:
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21Assist.Prof. Poenar Daniel Puiu
with iX= gmvbe+ iO (12) => iO= iX – gmvbe (12’),while vX= –vO + vE (13), with vE= REiE (14),
(11)XOUT
X
vRi
=
and iE= iX + ibe (15). Combining (14) and (15) gives
1 (17),SBE be
Rv vrπ
⎛ ⎞= − +⎜ ⎟
⎝ ⎠At the same time, vE= –vbe –ibeRSB =>
(16).EE E X be
Rv R i vrπ
= +
so
by equating (16) with (17) to eliminate vE we will finally obtain
(18),Ebe X
SB E
R rv ir R R
π
π
= − ⋅+ +
which we can insert e.g. back in (16)to express vE as a function of iX:
( ) (19).E SBE EE E X X E X
SB E SB E
R r RR R rv R i i v ir r R R r R R
ππ
π π π
+= − ⋅ ⋅ ⇔ = ⋅
+ + + +
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22Assist.Prof. Poenar Daniel Puiu
Also vE= – iOrO = –rO(iX – gmvbe) and using again (18) =>
( )1(20).O SB E
O XSB E
r r R Rv i
r R Rπ
π
β+ + +⎡ ⎤⎣ ⎦= − ⋅+ +
Now we can use (19) and (20) and insert them back in (13), whichultimately leads to:
( ) ( )1(21)O SB E E SBX
OUTX SB E
r r R R R r RvRi r R R
π π
π
β+ + + + +⎡ ⎤⎣ ⎦= =+ +
Here we can notice that there is a large difference between the two terms ofthe numerator: since both RE<<rO and rπ+RSB<< rπ+RSB+(β+1)RE => thesecond term can be neglected, hence (21) can be expressed in a simplerform:
1 (21')EOUT O
SB E
RR rr R Rπ
β⎛ ⎞≅ +⎜ ⎟+ +⎝ ⎠
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23Assist.Prof. Poenar Daniel Puiu
75 0.2100 1 438.305 .3.75 0.484 0.2OUT OUTR R k×⎛ ⎞⇒ = + ⇒ ≈ Ω⎜ ⎟+ +⎝ ⎠
Indeed, if we used (21), the result would be 438.496 kΩ, proving thus thatthe error given by using the latter approximation is extremely small.CONCLUSION: Let’s summarize all the results obtained in both cases:
RIN [kΩ]AV1AVAIROUT [kΩ]
Parameter Without considering rO Taking into account rO8.373–47.5
0.94365AV1= –44.82–33.137∞ !?
8.038–46.3153
0.9414AV1= –43.6–31.024438.5
These results clearly show that ROUT is the ONLY parameter that isradically different when rO is considered. Therefore, we must considerrO ONLY when calculating ROUT. It is NOT necessary to take intoaccount rO when calculating all the other parameters.
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24Assist.Prof. Poenar Daniel Puiu
8.4- The gate resistor RG in Fig.8.4 below is said to be“bootstrapped” by the action of the source follower.
a. Assume that the MOSFET is operating with gm= 3.54mS and ro can be neglected. Draw the small signal modeland find the voltage gain AV, input resistance RIN and outputresistance ROUT for the amplifier.
b. What would RIN be if Av were exactly +1?
vIN
VDD= 10 V
–VSS= –10 V
IDS
RD2 kΩ
C1=∞
RG1 MΩ
Q1
C2=∞ vOUTRL
100 kΩ
Fig.8.4:
Simple small signal A.C. analysis:Passivate DC sources, consider onlyrelevant condensers, redraw theschematics for A.C. and replace thetransistor with its small signal model:
a) Since the problem alreadyprovided us the gm, we do not need tosolve the D.C. bias problem, and can startwith the remaining important part:
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25Assist.Prof. Poenar Daniel Puiu
vIN
RD2 kΩ
RG1 MΩ
vOUTRL
100 kΩ
Fig.8.4-A:
gmvgs
G
S
D
vgs
The circuit can be re-drawn in a simpler and more convenient form:
vIN
RG1 MΩ
vgs RL | | RD=RLD1.9608 kΩgmvgs
vOUT
For this latter circuit we can write:vIN = vgs + vOUT , and
gsOUT LD m gs
G
vv R g v
R⎛ ⎞
= ⋅ +⎜ ⎟⎝ ⎠
Fig.8.4-B:
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26Assist.Prof. Poenar Daniel Puiu
From the first eqn. we extract vgs and insert it into the second eqn.:
( )
( )( )
( )( )
11
1.96 1 1000 3.540.8741
1000 1.96 1 1000 3.54
IN OUTOUT LD m IN OUT
G
LD G mOUTV
IN G LD G m
V
v vv R g v vR
R R gvAv R R R g
A
⎡ ⎤−= ⋅ + − ⇔⎢ ⎥
⎣ ⎦+
= =+ +
+ ×⇒ = ≅
+ + ×
The input resistance is obviously inIN
in
vRi
= with gsIN G
G
vi i
R= = ⇒
1000 7.9431 1 0.8741
in in GIN G G IN
gs in OUT V
v v RR R R R Mv v v A
= = = ⇒ ≅ = Ω− − −
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27Assist.Prof. Poenar Daniel Puiu
The last parameter we still need to calculate is ROUT. The modified circuitfrom which we need to calculate ROUT is:
RG1 MΩ
vgs RD2 kΩgmvgs
Fig.8.4-C:
vX
iXIt is evident that
X XX m gs
D G
v vi g vR R
= + −
and that vgs= –vX , hence
1000 2 0.2475 247.51000 2 1000 2 3.54
X G DOUT
X G D G D m
OUT
v R RRi R R R R g
R k
⇒ = = ⇒+ +
×⇒ = ≅ Ω = Ω
+ + × ×
b) From the previous eqn.1
GIN IN
V
RR RA
= ⇒ = ∞−
if AV =1 !
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1Assist.Prof. Poenar Daniel Puiu
VGS
9.1- What are the voltage gain, input resistance and outputresistance for the amplifier in Fig.9.1? What is the maximuminput signal for the amplifier? Use Kp= 200 μA/V2 and VTP= −1Vfor your calculation.
Tutorial 9: A.C. circuits with MOSFETs & BJTs (3)
VSS= +15 V
VDD= –15 V
ISD
RD43 kΩ
RS68 kΩ
Q1
C1=∞
C2=∞ R3200 kΩ
RI0.25 kΩ
vIN
Fig.9.1:
Solution: As usual, we must start first with:S1) D.C. analysis: We need first to
calculate the D.C. quiescent point and besure we are in saturation.It is immediately visible thatVSS= RSIDS+VSG <=> VSG= VSS –RSIDS<=> VGS= RSIDS –VSS ,, and, if we assumeQ1 is operating in saturationVSD
( )
( )
2
2
2
2
pDS GS TP
pGS S GS TP SS
KI V V
KV R V V V
= ⋅ − ⇒
= ⋅ − − ⇒
T9
2Assist.Prof. Poenar Daniel Puiu
( )2 2
1 2
68 0.1 1 15 6.8 12.6 8.2 02.3632 ; 0.51
GS GS GS GS
GS GS
V V V VV V V V
⇒ = × ⋅ + − ⇔ + − =
⇒ = − =Since we have a PMOS, the first solution is obviously the only one withphysical meaning (and for which clearly |VGS|>|VTP|). Then
( ) ( )2 20.1 2.3632 12
0.185835 185.835
pDS GS TP DS
DS
KI V V I
I mA Aμ
= ⋅ − ⇒ = ⋅ − +
⇒ = =It results that VSD= VSS+VDD – (RD+RS)IDS => VSD= 30 – (68+43)×0.185 =>VSD ≅ 9.37 V which means that |VDS|> |VGS|–|VTP|=1.632 V, hence Q1 isindeed operating in the saturation region.
Now we can start S2) Simple small signal A.C. analysis:2 2 0.185 0.273
1.3632DS
m mGS TP
I mAg g VV V×
= ⇒ ≅ =−
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3Assist.Prof. Poenar Daniel Puiu
vIN
Now we can replace the transistor with its equivalent small signal A.C. model:
Passivate D.C. sources, consider only relevant capacitors (in this case all of them have zero reactance), redraw the schematics for A.C.:
R3| |RD= R3D35.39 kΩ
RS68 kΩ
Q1
RI0.25 kΩ
vIN
Fig.9.1-A:
gmvgs
G
S
D
RS68 kΩ
RI0.25 kΩ
vgs R3D35.39 kΩvOUT
Fig.9.1-B:
which can be re-drawn more conveniently:
T9
4Assist.Prof. Poenar Daniel Puiu
vINRS
68 kΩ
RI= 0.25 kΩgmvgs
R3200 kΩ
vOUT
vgs
Fig.9.1-C:
(No λ was given, and besides, IDS is very small => rO ∝ 1/IDS will be verylarge and thus can be neglected in the transistor’s equivalent small signalA.C. model). vOUT = –gmvgsR3D and vgs= –isRS. Also we can write that
vIN= RIiI – vgs, and iI= iS – gmvgs =>
iS
iI
3
3 0.273 35.39 68 9.0130.25 68 0.273 0.25 68
m gs D SOUTV
IN I gs m gs I S gs S
m D SV V
I S m I S
g v R RvAv R v g v R R v R
g R RA AR R g R R
−= =
− − −
× ×= ⇒ = =
+ + + + × ×
RIN1 ROUTRD
43 kΩ
gsIN I m gs gs
S
vv R g v v
R⎛ ⎞
= − − − ⇒⎜ ⎟⎝ ⎠
RIN
with R3D= R3 | | RD <=>
T9
5Assist.Prof. Poenar Daniel Puiu
The input resistance can be calculated as follows:
1I gs m gs I S gs SIN
INgsI
S m gsS
R v g v R R v RvRvi
R g vR
− − −= = ⇔
⎛ ⎞⋅ − −⎜ ⎟⎝ ⎠
1 10.25 68 0.273 0.25 68 3.726
1 1 0.273 68I S m I S
IN INm S
R R g R RR R kg R
+ + + + × ×= ⇒ = = Ω
+ + ×From previous Fig.9.1-C we notice that RIN1= RI+RIN => RIN= 3.476 kΩ.The circuit necessary to calculate ROUT is:
RS68 kΩ
RI0.25 kΩ
gmvgs
RD43 kΩ
vXvgs
Fig.9.1-D:
iS
iX
ROUT
XX m gs
D
vi g vR
= + and
gmvgs= –vgs/(RI | | RS) <=>vgs[gm + 1/(RI | | RS)]= 0 =>vgs=0 and henceROUT = RD= 43 kΩ
T9
6Assist.Prof. Poenar Daniel Puiu
To calculate the maximum input voltage we remember from Tutorial 7 thatthe small-signal limit is:
( )0.2 0.2 2.3632 1 0.27265gs GS TP gsv V V v V= − ⇔ = × − + =
However, as we noticed in previous Fig.9.1-C, RIN1= RI+RIN =>
3.476 0.250.27265 0.29233.476
in in Igs IN IN gs
in I in
IN
R R Rv v v vR R R
v V
+= ⋅ ⇔ =
++
⇒ ≤ ⋅ =
T9
7Assist.Prof. Poenar Daniel Puiu
9.2- What are the midband voltage gain, input resistance andoutput resistance of the amplifier in Fig.9.2? Use β= 100 andVA= 70V. VCC +15 V
R320 kΩ
R2180 kΩ
Q1
vOUT
R518 kΩ
R1300 kΩ
C2= ∞
R6180 kΩvIN
R42 kΩ
RS2 kΩ
C1= ∞
C4= ∞
C3= ∞
R5300 kΩ
Q2
R820 kΩ
R720 kΩ
R9100 kΩ
C5= ∞
Fig.9.2:
T9
8Assist.Prof. Poenar Daniel Puiu
VBE=0.7 V
S1) D.C. analysis: We need first to calculate the D.C. quiescent point andbe sure we are in saturation. For each transistor the D.C. bias circuit is:
Solution:
VCC +15 V
Q
RE20 kΩ
RB2180 kΩ
RB1300 kΩ
RC18 kΩIB
IC
IE
VE
VC
VBE= 0.7 V
IB
IC
IE
We replace the RB1-RB2 group with a Theveninequivalent source (see again probl.6 in Tutorial 5):
RC20 kΩ
RE20 kΩ
Q1Vth
Rth=>
VCC= +15 V 2
1 2
18015 5.625180 300
Bth CC
B B
th
RV VR R
V V
= ⇒+
= =+
Vth= RthIB+VBE+REIEwith IE= (β+1)IB =>
Rth=R1 | | R2 => 180 300 112.5180 300thR k⋅
= = Ω+
( ) ( )1 1th BE th BE
B Cth E th E
V V V VI IR R R R
ββ β− −
⇒ = ⇔ = ⇒+ + + +
Fig.9.2-A: Fig.9.2-B:
T9
9Assist.Prof. Poenar Daniel Puiu
5.625 0.7100 0.231112.5 101 20C CI I mA−
⇒ = ⇒ ≅+ ×
1 101 0.231 0.23326100
CE E C
II I I mAβα β
+= ⇔ = = =
and IB=IC/β= 2.31 μA;VE= REIE = 0.231×20= 4.62 V => VB= VE+VBE ≅ 5.32 V andVC= VCC – RCIC = 15–20×0.231= 10.38 V => VCB= VC–VB ≅5.06V, hence the C-B jct. is reverse biased, and consequently,each transistor is indeed in the active regime.
Their Q-point is, therefore: IC ≅ 0.231 mA, and VCE ≅ 5.76 V.
T9
10Assist.Prof. Poenar Daniel Puiu
S2) Simple small signal A.C. analysis:Passivate D.C. sources, consider only relevant capacitors (in this case all ofthem have zero reactance), redraw the schematics for A.C.:
R320 kΩ
R12=R1| |R2112.5 kΩ
Q1
vOUT
vINR4
2 kΩ
RS1 kΩ
Q2
R720 kΩ
R9100 kΩ
R56=R12112.5 kΩ
ROUT
RIN
Now we can replace each transistor with its equivalent small signal A.C. model:
Fig.9.2-C:
T9
11Assist.Prof. Poenar Daniel Puiu
R12=R1| |R2112.5 kΩ
vOUTvIN
RS2 kΩ
R720 kΩ
R9100 kΩ
R56=R12112.5 kΩ
ROUT
RIN
rπgmvbe1
B1
E1
C1vbe1
R320 kΩ
which can be re-drawn more conveniently as:
rO
R42 kΩ
rπgmvbe2E2
C2vbe2
rO
B2
R12112.5 kΩ
vIN
RS2 kΩ
RINvbe1
R4= 2 kΩ
rπ
gmvbe1
rO
R356p=R56| |R3| |rπ6.7691 kΩ
vbe2 vOUTR9
100 kΩ
ROUT
gmvbe2
R7O=rO| | R7
vin’iin iO1
ibe2
i4
Fig.9.2-D:
Fig.9.2-E:
ibe1
T9
12Assist.Prof. Poenar Daniel Puiu
Instead of directly solving the circuit in Fig.9.2-E, we can further simplifyit. In Problem 3 of the Tutorial #8, it was demonstrated that ro can beneglected when calculating any parameter except ROUT. Therefore, wecan simplify our calculations here as well by adopting the same procedureand neglect rO of Q1. In such a case, the circuit can be re-drawn as:
R12112.5 kΩ
vIN
RS2 kΩ
RIN vbe1
R42 kΩ
rπ
gmvbe1
R356pR56| |R3| |rπ6.7691 kΩ
vbe2vOUT
R9100 kΩ
ROUT
gmvbe2
R7O=rO| |R7vin’
iinibe2
i4
Fig.9.2-F:RIN1
10038.467 8.884 11.256/ 8.884
Cm C
m
I mAg I r kVkT q gπβ
= ≈ ⋅ = ⇒ = ≈ = Ω
7 970 +5.76 328 | | | | 15.86
0.231 A CE
o L OC
V Vr k R R R r kI+
= = ≅ Ω⇒ = ≅ Ω(≅16.67 kΩ if we neglect rO of Q2 as well)
T9
13Assist.Prof. Poenar Daniel Puiu
' (1) ' (1')IN INin IN V V
IN S IN S
R Rv v A AR R R R
= ⇒ =+ +
Also, as in previous problems
As noticed earlier, the whole amplifier consists of two identical stages,hence we can consider AV’=AV1’×AV2’.
For the first stage vout1 = vin2 = vbe2= –gmvbe1R356p (2), while forthe second one it is evident that vout2 = vOUT= –gmvbe2RL (3), and thatROUT= ro | | R7 = 18.85 kΩ. The expression of vbe2 can be deduced startingfrom the relation vin’= vbe1 + R4i4 (4), with i4 given by
14 2 (5).be
m bevi g vrπ
= +
By inserting (4) into (3), we obtain:
( )4
1 1 1 4 14
' ' (6),1in be be m be be in
R rv v v g v R v vr r R
π
π π β= + + ⇔ =
+ +which we can substitute back in eqn.(2) to calculate AV1’:
T9
14Assist.Prof. Poenar Daniel Puiu
( )356
1 14
8.884 6.7691 11.256' (8) ' 3.1741 11.256 101 2
m pV V
g R rA A
r Rπ
π β× ×
= − ⇒ = − ≅ −+ + + ×
Since (3) can be re-written as vout2 = –gmRLvbe2 = –gmRLvin2 (3’) =>AV2’= –gmRL = –8.884×15.86= –140.907. Consequently, AV’=AV1’×AV2’=3.174 × 140.907 => AV’= 447.238.
11 1
' ' 'in in inIN
bebe be
v v vR rvi ir
π
π
= = = ⋅For the input resistance and using again
eqn.(6) it results that( )1 4 11 (9) 11.256 101 2 213.256IN INR r R R kπ β= + + ⇒ = + × = Ω
The circuit also shows that RIN= RIN1| |R12 => RIN ≅ 73.648 kΩ. Finally, the complete total voltage gain is calculated using (1’):
73.648' 447.238 435.4175.648
INV V
IN S
RA AR R
= = × =+
T9
15Assist.Prof. Poenar Daniel Puiu
IF so desired, we can repeat the calculations for greater accuracy byconsidering ro in the calculations. In this case, looking back again atFig.9.2-E it can be seen that:
22 1 1
356
(10),bebe m be O
p
vi g v iR
= = − − and vbe2= rOiO1+R4i4 =>
2 41 4 (11).be
OO O
v Ri ir r
= − At the same time, ibe1= i4 + ibe2 <=>
356 1 21 24 4
356 356
(12).p be bebe be
p p
R v r vv vi ir R R r
π
π π
−= + ⇔ =
356 4 41 2 1
356
(13),pO be be
p O O
R R Ri v vR r r rπ
+= −
Inserting eqn.(12) in (11) one obtains
which we now insert back in eqn.(10), leading to
T9
16Assist.Prof. Poenar Daniel Puiu
( )( )
356 42 41 2 1
356 356
356 42 1
4 356
(14).
pbem be be be
p p O O
p Obe be
O p
R Rv Rg v v vR R r r r
R r Rv v
r r R R
π
π
β
+= − − + ⇔
−= −
+ +
From Fig.9.2-E it can also be seen that vin’= vbe1+R4i4 (4), and insertinghere the relation for i4 given by previous eqn. (12), provides
356 1 21 4
356
4 41 2
356
'
' (15),
p be bein be
p
in be bep
R v r vv v R
R r
r R Rv v vr R
π
π
π
π
−= + ⋅ ⇔
+= −
in which we can insert eqn.(14) obtained above =>
T9
17Assist.Prof. Poenar Daniel Puiu
( )( )
( )( ) ( ) ( )
356 44 41 1
356 4 356
4 3561
4 4 356 4 4
'
' (16).
p Oin be be
p O p
O pbe in
O p O
R r Rr R Rv v vr R r r R R
r r R Rv v
r R r R R R r R
π
π π
π
π
β
β
⎡ ⎤−+= + ⋅ ⇔⎢ ⎥
+ +⎢ ⎥⎣ ⎦
+ +=
+ + + + −Having obtained this relation between vin’ and vbe1, we can insert it back ineqn.(14) to obtain the relation between vin’ and vbe2:
( )( ) ( ) ( )
356 42
4 4 356 4 4
' (17),p Obe in
O p O
R r Rv v
r R r R R R r Rπ
ββ
−= −
+ + + + −which can be substituted in eqn.(3) to finally calculate the voltage gain:
( )( ) ( ) ( )
356 4
4 4 356 4 4
' (18)'
m L p OOUTV
in O p O
g R R r r RvAv r R r R R R r R
π
π
ββ
−= =
+ + + + −
T9
18Assist.Prof. Poenar Daniel Puiu
( )( ) ( ) ( )
8.884 15.86 6.7691 11.256 32800 2'
11.256 2 328 2 6.7691 2 32800 2' 446.497.
V
V
A
A
× × × × −⇒ =
+ + + + × −
⇒ ≅In order to find out the total final voltage gain AV, we must first determinethe input resistance RIN.
For this, we can write 11 1
' 'in inIN
be be
v vR ri v π= = (19), and using (16)
it results that ( )4 41 4
4 356
1
(19)
208.0363
OIN
O p
IN
R r RR r R
r R R
R k
π
β −= + +
+ +
⇒ = Ω
73.0154' 446.497 434.5975.0154
INV V
IN S
RA AR R
= = × =+
Since RIN= RIN1| |R12 = 208.0363 | | 112.5 => RIN ≅ 73.0154 kΩ. Finally, the complete total voltage gain is calculated using (1’):
T9
19Assist.Prof. Poenar Daniel Puiu
Fig.9.3:
VCC= +15 V
RC118 kΩ
R2100 kΩ
Q1
vOUT
RE12 kΩ
R1820 kΩ
C2= ∞
R443 kΩvIN
RS10 kΩ
C1= ∞
C4= ∞
C3= ∞
R3160 kΩ
Q2
RE21.6 kΩ
RC24.7 kΩ
RL250 Ω
C5= ∞C6= ∞
Q3R5
910 kΩ
R61.2 MΩ RE3
3 kΩ
β= 100, VA= 70V;Kn= 1 mA/V2, VTN =1 Vand λ= 0.02 V–1
9.3- Fig.9.3 shows a three-stage amplifier. Find the midbandvoltage gain, input resistance RIN and output resistance ROUT ofthis amplifier. What is the input signal range for this amplifier?Use β= 100, VA= 70 V, Kn= 1 mA/V2, VTN =1 V and λ= 0.02 V–1 forall BJT and n-MOS transistors.
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20Assist.Prof. Poenar Daniel Puiu
S1) D.C. analysis: We need first to calculate the D.C. quiescent point and be surewe are in the active regime and saturation, respectively. For each transistor theD.C. bias circuit is:
Solution:
VCC= +15 V
Q
RE
RB2
RB1RC
VBE=0.7 V
IB
IC
IE
VE
VC
VBE= 0.7 V
IB
IC
IE
Just as in previous Problem 9.2 we replace the RB1-RB2group with a Thevenin equivalent source:
RC
RE
QVth
Rth=>
VCC= +15 V 2
1 2
110015 1.63
100 820
Bth CC
B B
th
RV VR R
V V
= ⇒+
= =+
Vth1= Rth1IB1+VBE1+RE1IE1with IE1= (β+1)IB1 =>
Rth1= RB1 | | RB2 =>
1100 820 89.13100 820thR k⋅
= = Ω+
( ) ( )1 1
1 11 1 1 11 1
th BE th BEB C
th E th E
V V V VI IR R R R
ββ β− −
⇒ = ⇔ = ⇒+ + + +
Fig.9.3-A:Fig.9.3-B:
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21Assist.Prof. Poenar Daniel Puiu
1 11.63 0.7100 0.3196
89.13 101 2C CI I mA−⇒ = ⇒ ≅
+ ×
1 11 101 0.3196 0.32279
100C
E E CII I I mAβα β
+= ⇔ = = =
and IB1=IC1/β= 3.196 μA;VE1= RE1IE1 = 0.32279×2= 0.64558 V => VB1= VE1+VBE ≅ 1.35 VandVC1= VCC – RC1IC1 = 15–18×0.3196= 9.25 V => VCB1= VC1–VB1 ≅7.9 V, hence the C-B jct. is reverse biased, and consequently, theQ1 transistor is indeed in the active regime.
The Q-point of Q1, therefore, is: IC1 ≅ 0.3196 mA, and VCE1 ≅7.25V.
All the calculations can then be repeated for Q2:
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22Assist.Prof. Poenar Daniel Puiu
24315 3.18
160 43thV V= ≅+
Rth2= R3 | | R4 => 2160 43 33.89160 43thR k⋅
= = Ω+
and
2 2 23.177 0.7 101100 1.267 1.267 1.28
33.8916 101 1.6 100C C EI I mA I mA−= ⇒ ≅ ⇒ = =
+ ×and IB2=IC2/β= 12.672 μA;VE2= RE2IE2 = 1.28×1.6= 2.048 V => VB2= VE2+VBE ≅ 2.75 V andVC2= VCC – RC2IC2 = 15–4.7×1.267≅ 9 V => VCB2= VC2–VB2 ≅ 6.3V, hence the C-B jct. is reverse biased, and consequently, the Q2transistor is indeed in the active regime.
The Q-point of Q2, therefore, is: IC2 ≅ 1.267 mA, and VCE2 ≅ 6.3 V.
We need now to analyze the NMOS transistor:
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23Assist.Prof. Poenar Daniel Puiu
VCC= +15 VQ3R5
910 kΩ
R61.2 MΩ RE3
3 kΩ
VGS
VG
IDS
VDS
VG= VGS + RE3IDS (20), with
Fig.9.3-C:( )2
2n
DS GS TNKI V V= ⋅ −
( ) ( )2 23
21 2
18.53 3 12 2
3 4 14.062 0 2.932 ; 1.6 .
nG GS E GS TN GS GS
GS GS GS GS
KV V R V V V V
V V V V V V
= + ⋅ − ⇒ = + × × − ⇔
− − = ⇒ = = −
and combining it with (20) results in
6
5 6G CC
RV VR R
= ⇒+
and VCC= VDS + RE3IDS (21).We assume that Q3 is in saturation =>
120015 8.531200 910GV V= =
+
Obviously, only the first solution is realistic and in accordance with thecircuit’s details. Inserting the VGS1 value back in eqn. (20) provides IDS:
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24Assist.Prof. Poenar Daniel Puiu
3
8.53 2.932 1.8663
G GSDS CC DS
E
V VI V I mAR− −
= ⇒ = =
and VDS= VCC – RE3IDS = 15–3×1.866 ≅ 9.4 V ≥ VGS –VTN = 1.932 V, henceQ3 is indeed in saturation.
Thus the Q-point of Q3 is: IDS= 1.866 mA and VDS= 9.4 V.We can now move ahead with the A.C. analysis of the initial circuit
shown in Fig.9.3. Clearly, it is composed of 3 cascaded one-transistorstages. However, the analysis of the overall circuit has to be done‘backwards’, i.e. from the output towards the input, because the inputresistance of each stage has to be considered when calculating the load atthe output of the preceding stage.
Consequently, we shall start our A.C. analysis with stage #3.Passivate D.C. sources, consider only relevant capacitors (in this case all ofthem have zero reactance), redraw the A.C. schematics of stage #3 fromwhich we shall calculate ROUT and the gain & input resistance RIN3 of thisstage:
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25Assist.Prof. Poenar Daniel Puiu
Q3
RG=R5| |R6 RE3
3 kΩ
vin3
Fig.9.3-D:
vOUTRL250 Ω
=>
Fig.9.3-E:
RG=R5| |R6
vin3 gm3vgs
G
S
D
vgs ro331.83 kΩ
RE3| |RL vout3= vOUT
( ) ( )3 2 1 2 1 1.866 1 0.02 9.4 2.10565m n DS DSmAg K I V Vλ= + = × × × + × =
RLS=RE3| | RL | | ro3
Fig.9.3-F:
RG=R5| |R6
vin3
gm3vgs
vgs
which can be redrawn as:
3
3
1
50 9.4 31.8331.866
DS
oDS
o
Vr
I
r k
λ+
= ⇒
+= = Ω
vout3
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26Assist.Prof. Poenar Daniel Puiu
3 33
3 3
2.10565 0.2291 0.325421 1 2.10565 0.2291
out m LSV
in m LS
v g RAv g R
×= = = =
+ + ×
RLS= RE3| |RL | | ro3= 0.2291 kΩ; RG= R5| |R6 = 910 | | 1200 = 517.536 kΩ.We can also write the following relations:vout3= gm3×vgs×RLS (22) vin3= vgs+vout3=> vgs= vin3 – vout3 (23)From both (22) and (23) => vout3= gm3×RLS ×(vin3 –vout3) <=>
vout3 = gm3×RLS×vin3 – gm3×RLS×vout3 =>
The circuit from which ROUT can be calculated is the following one:
vXgm3vgs3rO3| |RE3
vgs3
iXFig.9.3-G: vgs3= – vX and
3 33 3
33 3
| |
1| |
XX m gs
E O
X X mE O
vi g vR r
i v gR r
= − ⇔
⎛ ⎞= + ⇒⎜ ⎟
⎝ ⎠
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27Assist.Prof. Poenar Daniel Puiu
RE3 | | rO3= 3 | | 31.833 = 2.7416 kΩ => ROUT = 1/(2.10565+0.3647)==404.793 Ω.Obviously, Rin3= RG= 417.536 kΩ, and it will be necessary to consider it byadding it to the load of the preceding stage 2.
We can now analyze in a similar manner the 2nd stage. Let’s draw firstthe A.C. circuit:
Q2 RIN3417.536 kΩ
RC24.7 kΩ
R34=R3| |R4
vin2
Now we can replace the transistor with its equivalent small signal A.C. model:
Fig.9.3-H:
vout2
33 3
33 3
1 1 11| || |
Xm OUT
OUT X E Om
E O
i g RR v R r g
R r
= = + ⇔ =+
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28Assist.Prof. Poenar Daniel Puiu
rπ2gm2vbe2E2
C2
RL2=rO2| |RC2| |RIN3
B2vbe2vin2
R34=R3| |R4
Fig.9.3-I:
vout2
22 2 2
2
10038.467 48.9662 2.0422/ 48.9662
Cm C
m
I mAg I r kVkT q gπβ
= ≈ ⋅ = ⇒ = ≈ = Ω
22 2 2 3 2
2
70 +7 60.77 | | | | 4.326 1.267
A CEo L C IN O
C
V Vr k R R R r kI+
= = ≅ Ω⇒ = ≅ Ω
vout2= gm2×vbe2×RL2 and vin2 = vbe2 => AV2 = – gm2×RL2 = –48.9662×4.326 =>AV2 = –211.83 andRin2= R34||rπ2= (160| |43)| |2.0422= 1.926 kΩ
Finally, the 1st stage can be analyzed as well. Its A.C. schematic andthe subsequent circuit resulting after replacing the transistor with itsequivalent small signal A.C. model are as follows:
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29Assist.Prof. Poenar Daniel Puiu
Q1 RIN21.926 kΩ
RC118 kΩR12=
R1| |R2Fig.9.3-J:
vout1
vIN
RS10 kΩ
RIN
iin vin1
R12=R1| |R2
vIN
RS10 kΩ
RIN
iin vin1 rπ1vbe1
gm2vbe2 RL1=rO1| |RC1| |RIN2
vout1
Fig.9.3-K:
11 1 1
1
10038.467 12.3517 8.096/ 12.3517
Cm C
m
I mAg I r kVkT q gπβ
= ≈ ⋅ = ⇒ = ≈ = Ω
11 1 1 2 1
1
70 +8.6 245.93 | | | | 1.728 0.3196
A CEo L C IN O
C
V Vr k R R R r kI+
= = ≅ Ω⇒ = ≅ Ω
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30Assist.Prof. Poenar Daniel Puiu
1 1 1 1 11 1 1
1 1 1 1
IN out out IN INin IN V V
IN S IN in IN S IN S
R v v R Rv v A AR R v v R R R R
′= ⇒ = ⋅ ⇔ = ⋅+ + +
while vout1= gm1×vbe1×RL1 and since vin1 = vbe1 => AV1`= –gm1×RL1 =>AV1’ = –12.3517×1.728 => AV1’ = –21.34 andRIN= Rin1= R12||rπ1= (100| |820)| |8.096= 7.422 kΩ.
Therefore, the overall gain is:AV’= AV1’×AV2×AV3= 21.34×211.835×0.32542 = 1471.079 =>
1
1
7.421851471.079 626.69217.42185
INV V
IN S
RA AR R
′⇒ = ⋅ = × =+
The input signal range is limited by the small signal limit of the last stage. As this 3rd stage is MOS-based, the small signal condition is expressed as: vgs≤0.2(VGS – VTN) <=> vgs≤0.2(2.932 – 1)= 0.3864 V.
We also saw that vin3= vgs+vout3= AV3×vin3 + vgs => vgs=(1–AV3) vin3,
and vin3 = vout2 = AV2×AV1×vin11
2 11
IN INV V
IN S
v RA AR R
′= ⋅ ⋅ ⇒+
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31Assist.Prof. Poenar Daniel Puiu
( ) ( )
( )( )( )
( )( )
13 2 1
1
1
3 2 1 1
1 0.2
0.21
0.2 2.932 1 17.42185297.436
1 0.32542 211.835 21.34 7.422
INV V V in GS TN
IN S
GS TN IN SIN MAX
V V V IN
IN MAX
RA A A v V VR R
V V R Rv
A A A R
v Vμ
−
−
⇒ − ⋅ ⋅ ⋅ ≤ − ⇒+
− += ⇒
− ⋅ ⋅ ⋅
× − ×= ≅
− × × ×
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32Assist.Prof. Poenar Daniel Puiu
9.4. Fig.9.4-A shows the C-E/C-B cascode circuit. It is used inhigh gain amplifiers and high output resistance currentsources. Derive the expressions of rπ’, gm’, β’ and ro’ of thesingle transistor equivalent hybrid-π model of the cascodecircuit (shown in Fig.9.4-B) in terms of the small signalparameters of transistors Q1 and Q2.
Q1 Q2 <=> rπ’gm'vbe’E’
C’
rO’
B’
vbe'
Fig.9.4-A:
vOUTvin
Solution:
Q1
Q2
E’
C’B’IB’ =IB1
IC’ =IC2IC1=IE2
IB2IE1IE’
In order to deduce the β and gmparameters of the equivalent transistor weneed to analyze the D.C. behaviour of thecascode circuit, as shown in Fig.9.4-C:
Fig.9.4-C:
Fig.9.4-B:
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33Assist.Prof. Poenar Daniel Puiu
At the same time, IC’ =IC2 , IE2=IC1 and
For the circuit in Fig.9.4-A we can easily see that IC1 =β1IB1 = IE2 (24), and
( )22 2
2
251
EC C
II I ββ
′ = = ⋅+
, and combining (24) & (25) =>
( )2 11
2
26 ,1
C
B
II
β ββ ββ
′′ = = ≈
+′( )27 ,
1C E EI I Iβαβ
′′ ′ ′= =′ +
while
we can also write similarly that ( )2 22 2 1
2 2
28 .1 1C C E CI I I Iβ β
β β′ = = =
+ +As we know that, by definition, C
mT
IgV
=
12 21 1
2 21 1C C
m m mT T
I Ig g gV V
β ββ β
′′ = = ⋅ = ⋅ ≈
+ +
, hence, using in this relation
eqn. (28) it results that
We can now proceed to find the small signal parameters of theequivalent transistor’s hybrid-π circuit. For this we need to draw the A.C.
IF β2 >> 1.
T9
34Assist.Prof. Poenar Daniel Puiu
rπ1vin= vbe1
B’cascode circuit after replacing the equivalent small signal circuits of eachtransistor:
vOUT
rO1
gm1vbe1 rπ2vbe2
gm2vbe2
rO2
which can be redrawn as:
<=>Fig.9.4-D:
E’
C’
rπ1gm1vbe1
vbe’=vbe1
rO1| |rπ2
B’rO2
gm2vbe2
vbe2
E’
C’
Fig.9.4-E:
After comparing Fig.s 9.4-Band 9.4-E it is evident thatrπ’= rπ1.
The only parameter we still need to find out is rO’. How can we findit out? We know how to calculate the output resistance ROUT of a circuit.Can we use the same method to extract rO in this case? (In other words, isrO indeed the output resistance exhibited by a transistor’s small signalequivalent circuit?). Let’s verify it by applying it for a simple transistor!
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35Assist.Prof. Poenar Daniel Puiu
rπgmvbe
E
C
rO’
B
vbe vX
iX
Fig.9.4-F:
Clearly vbe=0 => gmvbe=0 => ROUT = ro.Consequently, we can apply the sameprocedure to deduce ro’ from theprevious circuit shown in Fig.9.4-E,which will be transformed as shown inFig. 9.4-G below:
rπ1gm1vbe1
vbe1
rO1| |rπ2
B’rO2
gm2vbe2
vbe2
E’
C’
Fig.9.4-G:
vX
iX
Here also vbe1=0 => gm1vbe1= 0 => the circuitsimplifies as shown in Fig. 9.4-H:
RPO12=rO1| |rπ2
rO2
gm2vbe2
vbe2C’ vX
iX
Fig.9.4-H: v2
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36Assist.Prof. Poenar Daniel Puiu
As in the previous Tutorials, we can use 2 methods to calculate rO’: withand without considering the (first) transistor’s output resistance ro1.
i) ro1 is neglectedIn this case RPO12 = rπ2 hence vbe2 appears across rπ2 alone and we can writevX = v2 – vbe2 (29), while
22 2
2 22 2
2 2 2
2
22 2 2
2
(30 ),1
(30 )
1 (31)
X m beo
be mbe o
X
be o
vi g v a andr vv g
v r ri br
v v rr
π
π
π
β
⎫= + ⎪ ⎛ ⎞⎪⇒ + = −⎬ ⎜ ⎟⎝ ⎠⎪=
⎪⎭+
⇔ − = ⋅ which we introduce back in (29), resulting in
( )( )2 2
222 2
222
2
11
11
obe
o XX be OUT o
beX
rv
rr vv v R r vr ir
π
π
π
ββ
+⎡ ⎤− +⎢ ⎥+⎡ ⎤ ⎣ ⎦′= − + ⇒ = = = ⇒⎢ ⎥ −⎣ ⎦
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37Assist.Prof. Poenar Daniel Puiu
⇒ rO’= rπ2 + rO2(β2+1) (32).
ii) ro1 is taken into considerationIn this case vbe2 appears across RPO12= rπ2| |rO1, which means that eqn.(30b)must be modified accordingly (replace rπ2 with RPO12). However, eqn.s (29)and (30a) remain unchanged. Carrying out a similar reasoning aspreviously, from combining (30a) and the modified eqn.(30b) one obtains
( )1 2 22 2 2
1 2
1(31')o
be oo
r rv v r
r rπ
π
β + += − ⋅ and 1 2
21 2
(32 ')oX be
o
r ri vr r
π
π
+= −
which can be obtained either directly applying Ohm’s law for RPO12, or byintroducing eqn.(31’) back in (30a). At the same time, introducing (31’) in(29) results in
( )1 2 22 2
1 2
11 (33')o
X be oo
r rv v r
r rπ
π
β + +⎡ ⎤= − +⎢ ⎥
⎣ ⎦. Combining eqn.s (32’) & (33’) gives
T9
38Assist.Prof. Poenar Daniel Puiu
( )1 2 2 1 2 2 2
1 2
1o o o oo
o
r r r r r rr
r rπ π
π
β+ + +′⇒ =+
( )1 2 22 2
1 2
1 22
1 2
11 o
be ooX
OUT ooX
beo
r rv r
r rvR r r ri vr r
π
π
π
π
β + +⎡ ⎤− +⎢ ⎥
⎣ ⎦′= = =+
−
AddT10Author: Assoc. Prof. Poenar Daniel PuiuRecapitulation: Differential Amplifiers
IC2
VCC
IC1
– VEE
I
RC RC
vB1(vin-diff /2)
vC2vC1
Loads: Passive (resistors)or active (current mirrors);
Emitter current source:Passive (resistor) or active (current source/sink);
Modes of operation:Input:A) Common mode: vB1= vB2;B) Differential mode: vB1≠ vB2;
b.1- Small signal;b.2- Large signal.
Output:1) Differential mode: vC1 – vC2;2) Single-end: vC1 or vC2
Q2Q1 vB2(–vin-diff /2)
AddT10Author: Assoc. Prof. Poenar Daniel Puiu
Linear region(small input signal)I
iC
0
T
BB
Vvv 21 −
Q1 Q2
Small input signal <=> vbe<< VT<=> vin-diff << 2VT
Large input signal => Q1,2 = ON/OFF
Recapitulation (continued):
IC2
VCC
IC1
– VEE
RC RC
vin-diff = vB1 – vB2
vC1 vC2
REvE = + = ?
=>
E=Virtual ground
E
=>
Two identical halves => simplifyanalysis by considering only one =>
Differential
Q2Q10V
AddT10Author: Assoc. Prof. Poenar Daniel PuiuRecapitulation (continued):
IC2
VCC
IC1
RC RC
vCM
RE+ = ?
=>
E=…
E
=>
Two identical halves => simplifyanalysis by considering only one =>
Q2Q1
RC RCvC1
vC2
E
VCC
=>
Common mode
Differentialmode
Q2Q1
vin-diff = vB1 – vB2
– VEE
vC1 vC2
vE =
DIFFERENTIALHALF-CIRCUIT
Q1
RC
VCC
vin-diff /2vout
AddT10Author: Assoc. Prof. Poenar Daniel Puiu
Common modeRecapitulation (continued):
VCC
– VEE
RC RC
vCM
vC1 vC2
2RE
EvCM
–VEE
2RE
Q2Q1
RC voutCM
–VEE
2RE
vCM
VCC
=> Q1
Common-modeHalf-circuit
AddT10Author: Assoc. Prof. Poenar Daniel PuiuBe careful and notice if the circuit has differential or single-ended output.The previous analysis and circuits considered a differential output. In such a case, the half circuit and its corresponding output voltage will be:
vin
vout1
voutTotVCCRC RC
Q1
RCvinput= vB1= vin-diff /2
voutput= vout1
Clearly, vinput=vbe=vin-diff/2 and voutput= −gmvbeRC=> AVD= voutput/vinput= vout-diff/(vin-diff /2)= −gmRC,or AVD= −αRC/re.It can be noticed that the gain in differential mode calculated using the half-circuit is identical with the total differential gain of the complete circuit !!
This is because voutput= voutTot=vC1− vC2=vout1 − vout2, but we know that in differential mode vC2 = − vC1 => Total differential gain is:
Recapitulation (continued):
Q1 Q2
AddT10Author: Assoc. Prof. Poenar Daniel Puiu
whereas solving the half-circuit will obviously provide
circuitHalfVDin
out
in
out
in
C
in
CC
in
TotoutTotVD Av
vvv
vv
vvv
vvA −−
−− ====
−==
2
22 11121
It can be easily realized thus that, for differential output,solving only the half-circuit will provide us exactly the samevoltage gain as for the entire circuit, hence the practicalimportance of using the half-circuit.
However, if the output of the entire circuit is single-ended, thenobviously the output voltage will be only voutput= vC1 = vout1=> for the complete initial
circuit we will now have:in
outendedSingleTotVD v
vA 1=−−−
endedSingleTotalVDin
out
in
out
circuitHalfinput
circuitHalfoutputendedSinglecircuitHalfVD A
vv
vv
vv
A −−−−−
−−−−−− ==== 22
2
11
Recapitulation (continued):
AddT10Author: Assoc. Prof. Poenar Daniel Puiu
Analysis of Op-Amp Problems:A) Input signals for differential &
common-mode half-circuits: vin-diff = vD = vB1 − vB2;vin-CM = vCM = (vB1+ vB2)/2;
B) Calculate gains for differential output: AD, ACM and CMRR:
Recapitulation (continued):
C) Differential output signal by superposition:vout = AD
.vD+ ACM.vCM
, ,out diff out diff DD CM
in diff in CM CM
v v AA A CMRRv v A
− −
− −
= = =
AddT10Author: Assoc. Prof. Poenar Daniel PuiuA more detailed representation is presented below. The following notesgo beyond the simplified picture previously shown, and complete it.
For a differential amplifier with two inputs and two outputs, the two-portrepresentation used for single-transistor amplifiers is not applicable. Instead,a three port representation is needed, as shown below:
DifferentialAmplifier
vout1vin1 = vB1
vin2 = vB2 vout2As mentioned earlier, the two inputs vin1 and vin2 can be always decomposedinto differential and common-mode components, vin-diff and vin-CM, respectively, defined as: vin-diff = vD = vB1 − vB2;
vin-CM = vCM = (vB1+ vB2)/2;meaning that
vin1 = vin-CM + vin-diff /2; vin2 = vin-CM − vin-diff /2;
AddT10Author: Assoc. Prof. Poenar Daniel Puiu
vin-CM
vin-diff /2
vin2
vin1–vin-diff /2vin-CM
The same relations applyto the input currents:
1 2
1 2
;2
2
in inin diff
in inin CM
i ii
i ii
−
−
−=
+=
The input voltages and currents are related by the input impedances:
0
0
;in CM
in dif
in diffin diff
in diff v
in CMin CM
in CM v
vR
i
vRi
−
−
−−
− =
−−
− =
=
=
As usually Rin-CM>> Rin-diff , the three-port input of the operational amplifiercan be represented by the π equivalent circuit shown in the next figure.
0V
AddT10Author: Assoc. Prof. Poenar Daniel Puiu
vin-diff iin-CM
vin-diff
vin-CM
Rin
-CM 2R
in-d
iff
Rin
-CM iin-CM
iin-dif
iin1
iin2
vout-diff
vout-diff
vout-CM
RL
-CM
2RL
-diffR
L-C
M
2iout-CM
iout1
iout2
vin2
vin1
vout2
vout1
Rout-CM
Rout-diff
Rout-diff
In the same manner it can be shown that the output voltages and currents can be decomposed into differential and common components and that twooutput impedances can be defined, one for each component. The outputs ofthe differential amplifier can be loaded either symmetrically or asymmetrically. Consequently, the differential and common output voltagescan be related to the input voltages with the following more exact relations:
AddT10Author: Assoc. Prof. Poenar Daniel Puiu
vout-diff = ADD.vin-diff + ADC
.vin-CMvout-CM = ACD
.vin-diff + ACC.vin-CM
0
0
0
0
in CM
in dif
in dif
in CM
out diffDD
in diff v
out CMCC
in CM v
out diffDC
in CM v
out CMCD
in diff v
vA
v
vAv
vA
v
vAv
−
−
−
−
−
− =
−
− =
−
− =
−
− =
=
=
=
=
where
is the differential mode gain
is the common mode gain
is the common-to-differential modetransfer gain
is the differential-to-common modetransfer gain
Under conditions of ideal symmetry, both transfer gains should be =0.
AddT10Author: Assoc. Prof. Poenar Daniel PuiuDifferential amplifiers are commonly used when a desired differential
mode signal is superimposed on a large fluctuating common-mode signal.The next figure shows a possible application where the differentialamplifier is used with a bridge circuit & an oscilloscope to measure a slightunbalance caused by a small change in resistance ΔR. The oscilloscope andthe power supply must have a common terminal. Thus, it is important thatthe oscilloscope responds only to the difference mode component input(vin1 − vin2)/2, which can be in the range of mV or lower, and not to the CMcomponent which can be in the range of V.
vout1= vout-diff +vout-CM=vin-diff (ADD+ACD)+vin-CM(ACC+ADC)
Y GND X
DifferentialAmplifier
ER R
RR±ΔR (e.g.: temperature or pressure sensor, etc.)
vin1
vin2
vout1
AddT10Author: Assoc. Prof. Poenar Daniel PuiuSince the desired signal is usually the differential signal, the response to
the CM signal produces an error at the output that is indistinguishable fromthe signal. Therefore, the minimization of both ACC and ADC are extremelyimportant objectives in differential amplifiers design.
The effect of finite transfer gains on the amplifier response can bedescribed by the common-mode rejection ratio CMRR and the differential-mode rejection ratio DMRR:
CMRR=ADD
ADCDMRR=
ACC
ACD
IF the differential amplifier is loaded symmetrically, only thedifferential output voltage appears across the load, because
( )1 2 2 2 in CMout diff out out in diff DD in CM DC DD in diff
vv v v v A v A A vCMRR
−− − − −
⎛ ⎞= − = ⋅ + ⋅ = +⎜ ⎟⎝ ⎠
It can be clearly seen that higher the CMRR, the more independent vout-diffbecomes from the effect of the CM input voltage.
AddT10Author: Assoc. Prof. Poenar Daniel PuiuHowever, for a single-ended load (load applied between one of the two
outputs and GND), the output will be a function of both CM anddifferential input components, and vout = vout-diff +vout-CM , as it is also shownin the figure of the previous example with the oscilloscope.
Consequently, in such cases it is necessary to have the CM input rejectedas much as possible, i.e. one must have ADD>>ACC. The degree towhich this requirement is met by a given differentialamplifier is specified using the discrimination factor,defined as:
F=ADD
ACC
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1Assist.Prof. Poenar Daniel Puiu
Tutorial 11: Current Mirrors & Active Loads 11.1- Fig.11.1.1 shows an input differential BJT amplifier with asingle-ended output.
(a) Derive the amplifier’s voltage gain AV without theuse of the small signal model in terms of gm and ro , given thatthe npn transistors Q1 and Q2 are identical and pnp transistorsQ3 and Q4 are also identical. State your assumptions, if any.
(b) Prove that the voltage gain is independent of thetail current “2I”, given that the Early voltage of the pnptransistor is VAP and that of the npn is VAN. State yourassumptions, if any.
(c) If VT = 25 mV at room temperature, 2I = 100 μA andVAP = VAN = 100 V, find the gain of the amplifier. If 2I = 200 μA,what is the gain? State your assumptions, if any.
(d) Fig.11.1.2 shows an input differential amplifierusing MOS transistors. Compare the characteristic differencewith the BJT-based implementation.
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2Assist.Prof. Poenar Daniel Puiu
Given that Kn= Kp= 40 mA/V2, λN = λP = 0.01 V–1, with 2I = 100 μA,find the voltage gain of the amplifier. If 2I = 200 μA, what is thegain? State your assumptions, if any.
Q4Q3
Q1 Q2
2I
VCC
vin/2
Fig.11.1.1:
–vin/2
I+gm1vin/2vout
I+gm1vin/2
I–gm1vin/2 io=gm1vin
a) Assume that the β of both thenpn & pnp transistors are bothvery high such that the basecurrent can be neglected. Then,IC1=IC2=IC3=IC4=I, while
Solution:
4 3 1 1
2 2 1
4 2 1
2
2 2
inc c c m
in inc m m
o c c m in
vi i i g
v vi g g
i i i g v
= = =
= − = −
= − = so that
1 2 4where | |out m in o o o ov g v R R r r= = ( )1 2 4| |outv m o o
in
vA g r r
v= =, hence
T11
3Assist.Prof. Poenar Daniel Puiu
2 41
2 4
o ov m
o o
r rA g
r r⇔ =
+
( )
2 4 1 2 41 1 2 3 4
2 4
2 4
and because
1 2 if .2
AN AP
o o C C Cv m C C C C
AN APo o T
C C
AN AP Av A AN AP
T AN AP T
V Vr r I I I
A g I I I I IV Vr r VI I
V V VA V V V
V V V V
×= = ⋅ = = = = ⇒
+ +
= ⋅ = = =+
b) If we approximate A CE Ao
C C
V V VrI I+
= ≅ then (1) becomes
(1).
Thus, it can be concluded that, considering the same assumptions asat point (a), the voltage gain AV remains the same irrespective of thecurrent I.
c) Applying eqn. (2) leads to: 3
100 2000, . . 66 .2 50 10
Av
T
VA i e dB
V −= = =×
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4Assist.Prof. Poenar Daniel Puiu
Obviously, as was just stated previously, the voltage gain is independenton the magnitude of the current I, hence AV will not change its value if 2Ichanges from 100 to 200 μA.
d) A similar reasoning can be applied for the MOS-based circuit:
M4M3
M1 M2
2I
VDD
vin/2
Fig.11.1.2:
–vin/2
I+gm1vin/2vout
I+gm1vin/2
I–gm1vin/2 io=gm1vin
( )2 2 41
2 4
2 | |
1 12
v m o n o o
v no o
A g R K I r r
A K Ir r
−
= =
⎛ ⎞⇔ = +⎜ ⎟
⎝ ⎠
11DS
ODS DS
Vr
I Iλ
λ
+= ≈
(3)
If we approximate
then (3) becomes
2 42 4
212 with and .2 2
n nv n N P
N P
K I KA K I I I I
I I I Iλ λ λ
λ λ λ λ
⎛ ⎞= = = = = = =⎜ ⎟
+⎝ ⎠
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5Assist.Prof. Poenar Daniel Puiu
It can be seen that, in contrast with the BJT-based differential amplifierwhich has a gain independent from the bias current I, the MOSFETdifferential amplifier exhibits a gain inversely proportional to the squareroot of the bias current in the transistor. With the given specific parameters,the value of AV for the MOS input differential amplifier results as:
40100 20000.1
vA = = ( = 66 dB) for a current 2I = 100 μA, and
AV= 1414.214 ( = 63 dB) for a current 2I = 200 μA, respectively.
MOS implementations is representedgraphically in Fig.11.1.3. It can be seenthat the performance for the BJT issuperior for most of the cases. However,MOSFET differential amplifiers offermuch higher input impedance and verylow input currents.
AV
2I
BJT
MOS
The variation of the ideal gain AV with the bias current I for both the BJT- &
Fig.11.1.3:
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6Assist.Prof. Poenar Daniel Puiu
11.2- What are the output currents and output resistances forthe current sources in Fig. 11.2, if Kn’ = 25 μA/V2, VTN= 0.75 Vand λ = 0.015 V–1 ?
IREF30 μA
VDD
+10V +8V +12V
M14:1
M210:1
M320:1
M440:1
Solution:Clearly, for M1
11 1
1
2 600.75 1.5246 ,25 4
DSDS GS TN
n
IV V V VWKL
= = + = + =×⎛ ⎞′ ⎜ ⎟
⎝ ⎠and VGS1=VGS2=VGS3=VGS4=VGS.
Fig.11.2:
I1I2 I3 I4
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7Assist.Prof. Poenar Daniel Puiu
For all the transistors which share the same VGS we can write the followingrelations
( ) ( )
( ) ( )
( )
( )
2
1 211
11
1 12
112
nGS TN DSk DSk
k k k
n DSGS TN DS
K W WV V V VL LI
WI K W VV V V LL
λ λ
λλ
′ ⎛ ⎞ ⎛ ⎞− + +⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠= =′ ⎛ ⎞⎛ ⎞ +⎜ ⎟− +⎜ ⎟ ⎝ ⎠⎝ ⎠
with k= 2, 3, 4; VDS1=VGS (because of the diode-connected transistorconfiguration), I1 = IREF , and the VDSk values are the bias voltages appliedon the drains of the transistors Mk. Introducing the numerical values oneobtains: ( )
( )
( )( )
22
2
1
110 1 0.015 10
30 84.3224 1 0.015 1.52461
DS
REF
GS
W VL
I I A AW VL
λμ μ
λ
⎛ ⎞ +⎜ ⎟ × + ×⎝ ⎠= = × =× + ×⎛ ⎞ +⎜ ⎟
⎝ ⎠
2
2 62
1 1 100.015 909.217
84.322 10
DS
o
Vr k
Iλ
−
⎛ ⎞ ⎛ ⎞+ +⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠= = = Ω
×and . Similarly, for M3
For M2:
T11
8Assist.Prof. Poenar Daniel Puiu
( )
( )
( )( )
33
3
1
120 1 0.015 8
30 164.2444 1 0.015 1.52461
DS
REF
GS
W VL
I I A AW VL
λμ μ
λ
⎛ ⎞ +⎜ ⎟ × + ×⎝ ⎠= = × =× + ×⎛ ⎞ +⎜ ⎟
⎝ ⎠
3
3 62
1 1 80.015 454.608
164.244 10
DS
o
Vr k
Iλ
−
⎛ ⎞ ⎛ ⎞+ +⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠= = = Ω
×and
For M3:
( )
( )
( )( )
44
4
1
140 1 0.015 12
30 346.0854 1 0.015 1.52461
DS
REF
GS
W VL
I I A AW VL
λμ μ
λ
⎛ ⎞ +⎜ ⎟ × + ×⎝ ⎠= = × =× + ×⎛ ⎞ +⎜ ⎟
⎝ ⎠
4
4 62
1 1 120.015 227.304
346.085 10
DS
o
Vr k
Iλ
−
⎛ ⎞ ⎛ ⎞+ +⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠= = = Ω
×and
For M4:
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9Assist.Prof. Poenar Daniel Puiu
11.3- What are the output currents and output resistances forthe current sources in Fig.11.3, if β= 50 and VA= 50 V?
IREF100 μA
VDD
+10V +8V +12V
Q1A1=ASolution:
Fig.11.3:
IC1IC2 IC3 IC4
Q2A2=2.5A
Q3A3=5A
Q4A4=10A
Clearly, for Q1 VBE1=VCE1 and VBE1=VBE2 = VBE3=VBE4 = VBE. Because of current mirroring, for all the transistors which share the same VBE we can write the following relation:
( )11 1 1 1
1 1 1
1 1 1 4
1 1 1
VBEVT
VBEVT
CEk CEk CEkk S k k
A A ACkCk C
C CE CE CES
A A A
V V VA I e A AV V VI
I II V V VA I e A A
V V V
⎛ ⎞ ⎛ ⎞ ⎛ ⎞+ + +⎜ ⎟ ⎜ ⎟ ⎜ ⎟
⎝ ⎠ ⎝ ⎠ ⎝ ⎠= = ⇒ =⎛ ⎞ ⎛ ⎞ ⎛ ⎞+ + +⎜ ⎟ ⎜ ⎟ ⎜ ⎟
⎝ ⎠ ⎝ ⎠ ⎝ ⎠
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10Assist.Prof. Poenar Daniel Puiu
with k= 2, 3, 4. However, IREF≠ IC1 because of the base currents that appeardue to finite β, so that
C1 C2 C3 C4REF C1 B1 B2 B3 B4 C1
2 3 42 3 4
C1 C1 C1 C1C1
1 1 11 1 1
C11
1
I I I II I I I I I I
A 1 A 1 A 1I I I II
A 1 A 1 A 1
1 1I 1A 1
CE CE CE
A A A
CE CE CE
A A A
CE
A
V V VV V V
V V VV V V
VV
β β β β
β β β β
ββ
= + + + + = + + + + =
⎛ ⎞ ⎛ ⎞ ⎛ ⎞+ + +⎜ ⎟ ⎜ ⎟ ⎜ ⎟
⎝ ⎠ ⎝ ⎠ ⎝ ⎠= + + ⋅ + ⋅ + ⋅⎛ ⎞ ⎛ ⎞ ⎛ ⎞+ + +⎜ ⎟ ⎜ ⎟ ⎜ ⎟
⎝ ⎠ ⎝ ⎠ ⎝ ⎠
= ⋅ + +⎛ ⎞+⎜ ⎟
⎝ ⎠
2 3 42 3 4A 1 A 1 A 1CE CE CE
A A A
V V VV V V
⎧ ⎫⎪ ⎪⎡ ⎤⎛ ⎞ ⎛ ⎞ ⎛ ⎞⎪ ⎪+ + + + +⎨ ⎬⎢ ⎥⎜ ⎟ ⎜ ⎟ ⎜ ⎟
⎝ ⎠ ⎝ ⎠ ⎝ ⎠⎣ ⎦⎪ ⎪⎪ ⎪⎩ ⎭
Introducing the numerical values one obtains:
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11Assist.Prof. Poenar Daniel Puiu
( )
REF C1
C1 C1
C1 REF
1 1 10 8 12I =I 1 2.5 1 5 1 10 10.750 50 50 5050 150
I 1 0.02 0.019724 3 5.8 12.4 1.438146 I
I 0.69534 I 0.69534 100 69.534A Aμ μ
⎧ ⎫⎪ ⎪⎡ ⎤⎪ ⎪⎛ ⎞ ⎛ ⎞ ⎛ ⎞+ + × + + × + + × + =⎨ ⎬⎜ ⎟ ⎜ ⎟ ⎜ ⎟⎢ ⎥⎛ ⎞ ⎝ ⎠ ⎝ ⎠ ⎝ ⎠⎣ ⎦⎪ ⎪× +⎜ ⎟⎪ ⎪⎝ ⎠⎩ ⎭
= + + × + + = ⋅ ⇔⎡ ⎤⎣ ⎦= ⋅ = × =
Using now eqn.(4) for each transistor Qk results in:2
2
2 11
1
101 2.5 150 69.534 205.722
0.711 50
CE
AC C
CE
A
VAV
I I AVAV
μ
⎛ ⎞ ⎛ ⎞+ +⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠= = × =⎛ ⎞ ++⎜ ⎟⎝ ⎠
A CE2o2 3
C2
V V 60r 291.656 kΩ;I 205.722 10−
+= = =
×
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12Assist.Prof. Poenar Daniel Puiu
33
3 11
1
81 5 150 69.534 397.73
0.711 50
CE
AC C
CE
A
VAV
I I AVAV
μ
⎛ ⎞ ⎛ ⎞+ +⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠= = × =⎛ ⎞ ++⎜ ⎟⎝ ⎠
A CE3o3 3
C2
V V 58r 145.828 kΩ, andI 397.73 10−
+= = =
×
44
4 11
1
121 10 150 69.534 850.317
0.711 50
CE
AC C
CE
A
VAV
I I AVAV
μ
⎛ ⎞ ⎛ ⎞+ +⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠= = × =⎛ ⎞ ++⎜ ⎟⎝ ⎠
A CE4o4 3
C2
V V 62r 72.914 kΩ.I 850.317 10−
+= = =
×In conclusion, the accuracy of the current mirror depends on β, VA, and thenumber of transistors connected to the same diode-connected transistor.
T11
13Assist.Prof. Poenar Daniel Puiu
11.4- (a) Derive the output resistance ROUT of the cascodecurrent mirror in Fig.11.4. State your assumptions necessary inorder to ensure that the circuit exhibits a large ROUT value.
(b) What is the lowest voltage limit of VD3-min at the
IREFVDD
M4 M3
Fig.11.4:
I0
M1 M2
ROUT
drain of M3 if all the transistors shouldbe in the saturation region?
(c) If IREF = 17.5 μA , VDD = 5 V,Kn = 75 μA/V2, VTN= 0.75 V, and λ=0.0125 V–1, find:
- the numerical value of VD3-minas in part (b), and- ROUT if the drain voltage of M3is connected to VDD .
Solution: a) In the modified circuit thatis necessary to calculate ROUT, we assume that the IREF source offers an ideal infinite
VG3
VG2
VD3
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14Assist.Prof. Poenar Daniel Puiu
A.C. resistance and we also need to replace M1 and M4 with theirequivalent circuits. Therefore, it is necessary to determine first the outputresistance offered between G & S by the diode-connected transistors M1and M4 using Fig.11.4-A, from which it can be easily deduced that vgs= vX
vX gmvgs
G
S
D
vgs rO
iX Fig.11.4-A: and 1 1
11
X XX m X m X
O O X O
OO
O m m
v ii g v g vr R v r
rRr g g
= + ⇒ = = +
⇒ = ≈+
Consequently, the initial circuit can besimplified as shown in Fig.11.4-B.However, since ig3=0 => vgs2=0 =>gm2vgs2=0 and G3≡GND => after replacingM3 as well with its equivalent smallsignal circuit, the output resistance can bededuced from the further simplifiedcircuit shown in Fig.11.4-C:
M3
ROUT
RO4
RO1rO2
gm2vgs2G2
vgs2
Fig.11.4-B:ig3
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15Assist.Prof. Poenar Daniel Puiu
vX
iX
rO3
rO2vgs3
gm2vgs2
Fig.11.4-C: From this circuit we can see that vgs3= −iXrO2 and3
3 33
x gsX m gs
O
v vi g v
r+
= +
and after combining these two relations oneultimately obtains
ROUT= rO2+rO3+gm3rO2rO3 ≅ rO3(1+gm3rO2) ≈ gm3rO2rO3.b) Assuming all the MOSFET transistors have identical W/L ratios
and they operate in the saturation region, since they all have the same draincurrents they will also exhibit identical VGS values:
REFGSi GS T T 0
n
2IV V V V VK
= = + = + if we denote REF0
n
2I V .K
=
with i = 1…4.Hence the gate voltage of M3 and M4 is
( )REFG3 G4 GS1 GS4 GS T T 0
n
2IV V V V 2V 2V 2 2 V VK
= = + = = + = +
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16Assist.Prof. Poenar Daniel Puiu
and the drain-to-source voltage of M2 isVDS2 = VG3 − VGS3 = 2VGS − VGS = VT + V0 .
For M3 to remain in the saturation region the condition VDS3≥ VGS3– VT must be obeyed. Consequently, the lowest acceptable value of VDS3 is
VDS3-min = VGS3 – VT = V0and, therefore, the minimum external bias voltage VD3 necessary to beapplied at the drain of M3 which does NOT set M3 into the triode/linearoperating region is VD3-min= VDS2 + VDS3-min = VT +V0 + V0 = VT +2V0 .
c) Inserting the values in the relations previously deduced weobtain:
0
0
2 2 17.5 0.6831375
0.75 0.683313 1.43313
REF
n
GS T
IV V
KV V V V
×= = =
= + = + =and therefore, the minimum external bias voltage VD3 necessary in this case is VD3-min= VDS2 + VDS3-min = VT +2V0 = 0.75 + 2×0.68313= 2.1163 V.
If VD3=VDD, for the output resistance we need to calculate rO2,3 and gm3:
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17Assist.Prof. Poenar Daniel Puiu
3 3 2 2
3
3 63
1 1 5 1.433130.0125 4.77525
17.5 10
DS D DS DD DS
DS
oD
V V V V V
Vr M
Iλ
−
= − = − ⇒
+ + −= = = Ω
×( ) ( )6 6
3 3 3
5 23
2 1 2 75 10 17.5 10 1 0.0125 5 1.43313
5.23645 10 5.23645 10
m n D DS
m
g K I V
mAg V
λ − −
− −
⎡ ⎤= + = × × × × × + × −⎣ ⎦
⇒ = × = ×
( ) ( ) ( )5 6 63 2 3 5.23645 10 4.6533 10 4.77525 10 1.1636o m o oR g r r G−≅ = × ⋅ × ⋅ × = Ω
2
2 62
1 1 1.433130.0125 4.6533
17.5 10
DS
oD
Vr M
Iλ
−
+ += = = Ω
×