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Research Article NULL Convention Floating Point Multiplier Anitha Juliette Albert 1 and Seshasayanan Ramachandran 2 Centre for Research, Anna University, Chennai, Tamilnadu , India Faculty of Information and Communication Engineering, College of Engineering, Anna University, Chennai, Tamilnadu , India Correspondence should be addressed to Anitha Juliette Albert; anideni@gmail.com Received October ; Revised December ; Accepted January Academic Editor: Shih-Hsu Huang Copyright © A. J. Albert and S. Ramachandran. Tis is an open access article distributed under the Creative Commons Attribut ion License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. Tis paper presents the design o an IEEE single precision oating poin t mult iplie r using async hron ous NULL con vent ion logic para digm. Roun ding has not been impl emen ted to suit high prec isio n applications. Te novelty o the research is that it is the rst ever NULL convention logic multiplier, designed to perorm oating point multiplication. Te proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Perormance attributes o the NULL convention logic oating point multiplier, obtained rom Xilinx simulation and Cadence, are compare d with its equivalent synchronous implementatio n. 1. Introduction Clock ed circu its hav e domin ated semico nduc tor indu stry or the past two decades. Excessive clock skew, clock noise, and larger power dissipation o clocked circuits have led the way to the asynchronous world o very large scale integration (VLS I). NULL convention logic (NCL) is an async hron ous paradigm that requires less power, generates less noise, radi- ate s less EMI, and allows reus abili ty o compo nent s compa red to the synchronous counterparts [ ]. Te International echnology Roadmap or Semi- cond uctor s (IRS ) has pred icted that async hrono us clockl ess ci rcui ts wil l occ up y % o the chip area in and has ide nti ed power con sumpt ion as one o the maj or desi gn challe nges . Delay insensiti ve NCL circu its design ed using CMOS exhibit an inherent idle behaviour since they switch only when useul work is being perormed. Hence, the dynamic power consumption contrib uted due to the swi tc hing activit y is gre atl y red uce d whe n compar ed wit h the synchronous counterpart. Hence, NCL based asynchronous designs provide a signicant contribution in the research o low power VLSI. In order to integrate NCL into semiconductor design ind ust ry , reu sab le des ign lib rar ies ha ve to be des igne d. We perormed a background analysis o the circuits that were designed using NCL methodology. Consequently, we observed that, due to the complexity involved in processing oa ting poi nt da ta, res ear che rs con trib uti ng to NCL oc uss ed only on NCL based design s that processed n onractional and xed point data. However, high precision is a prime require- ment or high dynamic range and computationally intensive applications such as ast Fourier transorm, which requires an efficient hardware to support oating point data. Hence, we propose the design and characterization o a NCL based oating point multiplier (FPM) that is compliant with single precision IEEE . Te proposed NCL FPM is targeted to perorm multiplication o oating point numbers and to dis- sipate lower power when compared to its synchronous coun- terpart. Eventually, the primary contribution o our research was to deve lop a lo w powe r and hi gh pr ecision, re us ab le NCL oating point multiplier library component, which in uture can be used as an inte gral component in the design o NCL based DSP processor cores. Te perormance attributes o NCL FPM are analysed in terms o power , average delay , and area and compared with its equivalent synchronous FPM. Te outline o the paper is as ollows. In Section , liter- ature o NCL based designs is presented. Section presents Hindawi Publishing Corporation e Scientific World Journal Volume 2015, Article ID 749569, 10 pages http://dx.doi.org/10.1155/2015/749569
