FRONT-END AND READ-OUT ELECTRONICS FOR THE NUMEN FPD

D. LO PRESTI

D. BONANNO, F. LONGHITANO, D. BONGIOVANNI, S. REITO

INFN- SEZIONE DI CATANIA

D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015 1

OVERVIEW• NUMEN -> Upgrade of Cyclotron and Detector -> Higher Event rate

• Needed upgrade of the front-end and read-out electronics for the Focal Plane Detector (FPD):

• Tracker;

• DE-E Telescopes;

• Definition of the front-end and read-out architecture:• Choice of the technologies;

• Design and test of the building blocks:• Front-end based on the VMM2 chip by BNL;

• Read-out based on the SOM by National Instruments.

• Design and construction of the FPD detector:• Detector interface to front-end;

• Interconnections, cabling…

• Power distribution;

• Slow control;

• …D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015 2

FOCAL PLANE DETECTOR (FPD)specifications

• Tracker: • 16 layers, 1 m width, segmented in 0,5 mm steps =32000 channels

• DE-E Telescopes :• 40*100 DE-E SiC Telescopes (1x1 cm2)= 4000 channels

Event Rate foreseen after the upgrade of the cyclotron: 100 KHz/cm

• Modularity

• Ease of maintenance

• Re-configurability

• Radiation Tolerance

• Low Power

• Low Cost

D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015 3

* ASIC for ATLAS Muon Spectrometer Upgrade

New Small Wheels

• sTGCSmall Strip Thin Gap Chamber

• MMMicroMegas(MICROMEsh GAseous Structure)

Front-end Electronics (ASIC)• more than 2.3 million channels total• operate with both charge polarities• sensing element capacitance 10-200 pF• charge meas. up to 2 pC @ < 1 fC rms• time meas. ~ 100 ns @ < 1 ns rms• trigger primitives, neighbor logic• low power, programmable

D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015

4

VMM2 CHIP BROOKHAVEN NATIONAL LABORATORIES

D. Lo Presti, NUMEN2015 LNS, 1-2 December 20155

• Selected after a deep survey between available front-end ASICs;

• Designed for MicroMegas detectors in ATLAS;

• Collaboration established with the designer: Prof. G. De Geronimo;

• Radiation Tolerant;

• New version VMM3 could take in account the NUMEN specifications;

• Available in the future in big volume;

• All digital read-out compliant with the foreseen event rate;

• Suitable for all the detector types foreseen in the final FPD:

• Tracker (GEM, MicroMegas);

• Calorimeter- particle identification (SiC DE-E);• APD.

• 64 linear front‐end channels:• low‐noise charge amplifier (CA) with adaptive feedback;• test capacitor and pulse generator for calibration;

• adjustable polarity;

• optimized for a capacitance of 200pF and a peaking time of 25 ns.

• third‐order shaper (DDF) - adjustable peaking time in four values (25, 50, 100, and 200 ns);• Stabilized band‐gap referenced baseline;• Gain adjustable in eight values (0.5, 1, 3, 4.5, 6, 9, 12, 16 mV/fC).

• Many mode of operation, selected “continuous digital”:

• 38 bit generated for each event read-out @ about 200 MHz;

• Id channel-peak amplitude (10b) - time stamp (10b);

• 4-event deep de-randomizing FIFO per channel, read-out token ring;

• 8 LVDS digital channel required for the read-out and control of the chip;

• Power dissipation 4 mW per channel.

130nm 1.2V 8‐metal CMOS technology from IBM

VMM2 CHIP BROOKHAVEN NATIONAL LABORATORIES

D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015 6

Resolution Measurements (VMM2)

• timing resolution < 1 ns

(at peak-detect)

• charge resolution ENC < 5,000 e- at 25 ns, 200 pF

• analog dynamic range Qmax / ENC > 12,000 → DDF

charge resolution timing resolution

σt ≈ENC τP

Q ρP

λP≈ 0.3-0.8

G. De Geronimo, in “Medical Imaging” by Iniewski

1p 10p 100p 200p 1n100

1k

5k

10k

25ns, 9mV/fC

50ns, 9mV/fC

100ns, 9mV/fC

200ns, 9mV/fC

Me

asu

red

EN

C [e

lectr

on

s]

Input capacitance [F]

0.0 0.2 0.4 0.6 0.8 1.0100p

1n

10n

200pF, 200ns

200pF, 100ns

200pF, 50ns

200pF, 25ns

2pF, 25ns

Me

asu

red

tim

ing

re

so

lutio

n [s]

Output pulse amplitude [V]

D. Lo Presti, NUMEN2015 LNS, 1-2 December 20157

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.70.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Gain

0.5,1,3,4.5,6,9,12,16 mV/fC

Peaking time

200ns

100ns

50ns

25ns

Am

plitu

de [V

]

Time [µs]

Input charge: ~ 36 fC

Charge polarity: negative

Input capacitance: ~ 5 pF

Measured Pulse Response

Peak-time ~26 ns

@ Cin = 240 pF

0 25 50 75 100 125 150 175 200

0.2

0.4

0.6

0.8

Input capacitance

~ 5pF

~ 40pF

~ 243 pF

Am

plitu

de [V

]

Time [ns]

Input charge: ~ 36 fC

Charge polarity: negative

Peaking time: 25 ns

Gain: 16 mV/fC

D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015

8

• Suitable for different

detector capacitances

• Wide range of

measurement parameters

• Test pulse pattern

embedded

ENC ~4,7k e- (0.75 fC) at 25 ns, 226 pF (~5.6k at 0.5 mV/fC)

10 100 1000

102

103

104

MOSFETpara

llelshaper

Gain 16 mV/fC

Qin = 30 fC

Cin

= 6 pF

Cin

= 226 pF

PD + ADC

peak rms (PD)

Eq

uiv

ale

nt

No

ise C

harg

e [

e- ]

Peaking Time [ns]

baseline rms

theoretical

Measured ENC

D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015

9

1 10 1000.01

0.1

1

10

TAC + ADC

TAC rmsC

in= 6 pF

Tim

ing

Re

so

luti

on

t [

ns

]

Input Charge [fC]

Cin

= 226 pF

Peaking Time 25ns

Gain 16 mV/fC

TAC rms

theoretical*

PtQ

ENC8.0

σt within few ns @ 25 ns, 226 pF

Measured Timing Resolution

D. Lo Presti, NUMEN2015 LNS, 1-2 December 201510

VMM2 Test board Thanks to the collaboration with G. De

Geronimo a complete FE-RO chain for one

VMM2 chip is available from sept 2015.

Control and read-out software included.

Continuous digital mode:

38 bit/event

D. Lo Presti, NUMEN2015 LNS, 1-2 December 201511

• first ck of CKBC after peak-found stops ramp

• first ck of CKBC after latcheswrites FIFO

• 8-bit ADC starts at stop oframp, latches after conversion,resets at next rising edge ofCKBC (after latch)

• 10-bit ADC starts at peak,latches after conversion, resetsat next rising edge of CKBC(after latch)

• timing ramp starts at peak-found; the next rising edge ofCKBC arms the stop circuit; thenext falling edge stops the rampand starts the 8-bit ADCconversion

peak-found

CKBC

stop armedramp stop

timing ramp

conversion

data latch

data latch

reset 10-bit

reset 8-bit

FIFO writeFIFO ready & advance

conversion

8-bit ADC (timing)

10-bit ADC (peak)

Timing Ramp Optimization

charge eventanalog pulse

D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015 12

D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015 13

Read-out of VMMx chips will be

performed by a SOM based

board, custom designed for the

experimental demands:

• Low Power;

• Radiation Tolerance;

• Low Cost;

• Re-configurability;

Re-programmable Intelligence on

board will allow for:

• composite trigger strategies;

• Slow control;

• Calibration;

• Overall synchronization;

• Gigabit Ethernet to maximize

data throughput.

Adapter SOM

Schematic View

D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015 14

Design and Test SOM-VMM2 board by

D. Bonanno and D. Bongiovanni.

Full custom board hosting SOM and

interfacing VMM2 Board through Molex

twin-ax cable.

Measured Performance: Sampling of 128 digital input SE @230MHz

Sampling of 64 digital input SE @350MHz

Applications: Real – Time characterization of a proton

beam (position, size, fluence, energy);

Imaging and radiography;

Interfacing with:

DAC

ASICs (VMM2, MAROC)

SD – Cards, USB – HDD

Data transfer through Gigabit LAN

SD-CARD

LAN

USB

SOM

POWER

CONNECTORS

Adapter SOM

To VMM2

To VMM2

D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015 15

Test SOM-VMM2D. Bonanno, D. Bongiovanni

• SOM-VMM2 board fully

functional:

• Firmware SOM ready for:

• Configuration:

• Calibration;

• Synchronization:

• Read-out;

• LabView GUI:

• Slow control;

• DAQ

D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015 16

• 8 VMMx chip read-out by 1 SOM is one FE-RO Module;

• Possible increase to 10 VMMx, to be confirmed!

D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015 17

FE-RO Module

SOMXilinx-Zynq7020

667 MHz Dual Core Arm

Cortex A9

Artix7 FPGA Fabric

VMMx_1

VMMx_2

VMMx_3

VMMx_4

VMMx_5

VMMx_6

VMMx_7

VMMx_8

Conne

ctor

64 Sig IN

64 Sig IN

64 Sig IN

64 Sig IN

64 Sig IN

64 Sig IN

64 Sig IN

64 Sig IN

GbE

SPI Config10

BC ck/ En2

6

6

6

6

6

6

6

6

D0,

D1

From Synchro Som

FE-RO ARCHITECTURE

D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015 18

SOM

VMMx VMMx VMMxVMMx

DATA MANAGER

(storage)

SYNCHRO

SOM

BC ckEnableGb Ethernet

1 event (Tracker 1 strip per event):

• FE-RO Board id;

• Chip id;

• Channel id;

• BC ck count;

• Fine Timestamp;

• Charge measurement;

BC counter resetGb Ethernet

switch

twisted cables

FE-RO Module

x8

FE-RO ARCHITECTURE• FE-RO Module:

• 8 VMM2 chip -> 1 SOM

• 512 input -> 1 Gb/s Ethernet

• If 0,5 mm pad -> 320 kHz average event rate per Module;

• 38 bit/event *number of strips involved = 38 bit/event

(extra id chip and id Module);

• Data Throughput = 20 Mb/s per Module;

• Timing strategy

• Synchro SOM:• BC clock to all Modules = 10 MHz;

• Enable all Modules;

• Each Module (SOM): • counts BC clock edges up to 4096 = 409.6 m s;

• Each VMMx chip measures time from peak to next BC edge @ 488 psresolution.

D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015 19

CONCLUSIONS

• Design of a complete VMM2-SOM system, now under test;

• For the FE-RO Module final design we need:• the VMM3 details:

• Definition of the overall architecture;

• The FPD tracker final design:• Pitch, capacitance and interconnections;

• (Vacuum sealing,…)

D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015 20

(ALMOST) EVERY NEW IDEA IS WELCOME…

D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015 21

THANK YOU

D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015 22

THANK YOU

CONTACTS

DOMENICO.LOPRESTI@CT.INFN.ITSKYPE: DOMENICO.LO.PRESTI

D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015 23

mailto:Domenico.lopresti@ct.infn.it