Numerical signal processing for LVDT reading based on rad tol components

Salvatore DanzecaPh.D. STUDENT

(CERN EN/STI/ECE )

Students’ coffee meeting1/3/2012

1

Radiation field in the tunnel of LHCThe radiation field in the LHC is mainly due to:•Beam collision in the experiment points (ATLAS, LHCb, CMS, ALICE)•Beam collision with residual gas in the pipe•Beam collision with collimator, beam dump, etc..

Not Shielded Areas

2

Shielded Areas

Effect of radiation on the electronic devices

Cumulative effects

Single Event Effects (SEE)

Total Ionizing Dose (TID)Potentially all components

Displacement damageBipolar technologiesOptocouplersOptical sourcesOptical detectors (photodiodes)

Permanent SEEsSEL

CMOS technologiesSEB

Power MOSFETs, BJT and diodesSEGR

Power MOSFETs

Static SEEsSEU

Digital ICs

Transient SEEsCombinational logicOperational amplifiers

3

Conditioning and acquisition system architecture

ADC 16bitMAX11046

FPGA Actel ProAsic3

/

Profibus Module

/

UART to USB

External MemoryFlash or EEPROM

Instr. Amplifier

LVDT Sensors

Secondaries

DAC 20 bitPCM1702

LVDT SensorsPrimaries

/

Jumper wire

USB

4

Objectives / Targets

• Acquisition and processing in REAL TIME with a sampling rate of 250 kSps

• Uncertainty on position 1.0 μm • Position survey frequency 100 Hz• Possibility of multiple sensor readings in parallel• Numeric Resolution of 0.5 μm• Being radiation tolerant up to 100 Gy of Total Ionizing

Dose; low number of SEU for a given fluence of 1011pp/cm2

5

LVDT and position reading)2cos()( 0tfAtp

)2cos(101

tfA )2cos(202

tfA

21

21

AAAAr

rkP

1iy 2iy

11

1ir

s

c yDAA

2

2

2ir

s

c yDAA

21

211 sc AAA 2

2222 sc AAA

Sine Fit

)2()2cos(

)2()2cos(

00

1010

NN tfsentf

tfsentf

0D

T0

10

T0 DDDD

r

Ratiometric

6

Acquisition and processing: CPU vs FPGA

ADC

LVDT

Buffer CPU POSITION SURVEY

Acquisition of 2000 samples with a sampling rate of 250 KSps takes 8ms

Time to compute the position = 2ms

LVDT

LVDT

ADC FPGA POSITION SURVEY

Acquisition of 2000 samples with a sampling rate of 250 KSps takes 8ms

Time to compute the position < 2ms

LVDT

LVDT

LVDT 7

noise

signal

noise

signaldB A

APP

SNR log20log10

Is it possible to go faster?

8

-5 -4 -3 -2 -1 0 1 2 3 4 5x 10

4

0.5

1

1.5

2

2.5

3

3.5

4

Position [um]

Sta

ndar

d de

viat

ion

[um

]

N=2000N= 1500N= 1000N= 500N= 300N= 100

SNR = 60 dB

1.0 μm TARGET

9

Numerical algorithm

• FPGA implies the fixed point algorithm• Why?• Floating point would not assure the required

performance in terms of calculation time and area occupancy

• Fixed point is simpler; thus less prone to SEU effects

10

∑ x x

+

∑ x x

-

+

2121AAAA

∑ x x

+

∑ x x

Yi1

Yi2

Dr(:,2)

Dr(:,1)

Dr(:,2)

Dr(:,1) Q-9,24

Q-9,24

Q-9,24

Q0,15

Q0,15

Q-8,39

Q1,39

Q1,39

Q1,39

Q1,39

Q3,78

Q3,78

Q4,78

Q4,78

Q2,39

Q2,39

Q3,39Q0,42

Fixed Point Algorithm

16 bit 41 bit 82 bit 42 bit 43 bit

Low and Medium resolution algorithm

∑ x x

+

∑ x x

∑ x x

+

∑ x x

Yi1

Yi2

Dr(:,2)

Dr(:,1)

Dr(:,2)

Dr(:,1) Q-9,24

Q-9,24

Q-9,24

Q0,15

Q0,15

Q-8,39

Q1,39

Q1,39

Q1,39

Q1,3941bit->16bit

41bit->16bit

41bit->18bit

41bit->18bit

Implementation Area Occupancy Clock Frequency

Low resolution Core Cells:35197 of 24576 (143%) 2.3 MHz - 434.570 ns

Medium resolution

Core Cells:41780 of 24576 (170%) 1.7 MHz -588.235 ns

Low res

Medium res

16 bit 41 bit 18 bit

16 bit 32 bit

36 bit

11

CORDIC

Ac

As

A1-A2

A1+A2

Vectoring Mode

Circular Rotation

“Linear” Rotation

Vectoring Mode

22scnn AAAx

21

21

AAAAzn

12

A

r

Cordic = High resolution algorithm

∑ x

∑ x

Yi1

Dr(:,2)

Dr(:,1)

CORDIC

∑ x

∑ x

Yi1

Dr(:,2)

Dr(:,1)

CORDIC+

-CORDIC

2121AAAA

221 scn AAAA

222 scn AAAA

41 bit 41 bit 42 bit

Implementation Area Allocation Clock Frequency

High resolution (A3PE1000) Core Cells: 11881 of 24576 (48%) 25.6 MHz-39.031 ns

High resolution with TMR Core Cells: 14572 of 24576 (59%) 24.7 MHz-40.427 ns

High resolution on A3PE3000 Core Cells: 11465 of 75264 (15%) 23.9 MHz- 41.796

1

CLRCLK

D

Q

Triple Modular Redudancy

13

14

How to evaluate the algorithm

• Simulation– Emulation of the secondary voltages in Matlab– Emulation of a 0.5 μm movement– Comparison of the Low- Medium- High- resolution

algorithms(all fixed point) VS floating point algorithm • Experimental data from LHC collimator

– Analysis on a 5 μm movement at different absolute positions

– Comparison of the Low- Medium- High- resolution algorithms(all fixed point) VS floating point algorithm

Simulation results 0,5 μm with Low resolution algorithm

15

16

Simulation results 0,5 μm with Medium resolution algorithm

17

Simulation results 0,5 μm with High resolution algorithm

0 5 10 15 20 25 300.45

0.5

0.55

0.6

0.65

Number of repetition

Pos

ition

[um

]

Position Floating PointPosition High ResolutionPosition High Resolution on 32bit

0 5 10 15 20 25 300

0.5

1 x 10-4

Number of repetition

Err

or [u

m]

Difference Floating point - High resolution 32bit

Experimental ResultsLow resolution Medium resolution

Low ResMax error

[µm]

Medium ResMax error

[µm]

High Resolution with 32 bitMax error

[µm]

Position 9730µm 7,7499 0,7878 9,57E-05Position 9715µm 8,4810 0,5588 1,20E-04Position 9710µm 4,1310 1,0275 1,99E-04Position 9715µm 7,2870 0,8173 6,94E-05

Total max error 8,4810 1,0275 1,99E-04 18

Radiation Test Results

MAX TID[Gy]

Fluencepp/cm2

FPGA Actel ProAsic3 [1] [2]

390 1e13

Paul Scherrer Institut230 MeV Proton Beam

MAX TID[Gy]

Fluencepp/cm2

ADC MAX11046 [3] 210 3.9e11

Cross SectionSEU estimated per channel (fluence 1e11) 0.95SEU estimated per device (fluence 1e11) 7.6

Cross Section [3] 2.30e-10 cm2

Cross Section [1] 1e-13 cm2

Proton Beam

DUT

[1] NanoFIP Large Scale Radiation Tests, 2012, E. Gousiou 19[2] nanoFIP Preliminary Radiation Tests - Test Report, 2011, E. Gousiou

[3] ADC MAX11046 test 03.06.2011 at PSI Institute –Test Report , 2011, G. Spiezia, P. Perronard, S. Danzeca

][ 2cmN

ConclusionsHigh resolution algorithm – CORDIC based – complies to the specifications of 0,5 μm ofnumeric resolution

Possibility of using a single FPGA (A3PE1000) for readings of 2 LVDTs in parallel

Application of a redundancy scheme formitigate the effects of radiation

ADC and FPGA can be considered radiationtolerant in an environment characterized by a TID of 100 Gy and a fluence of 1e11cm-2

20

21

BACKUP SLIDES

• DAC PCM RADIATION TEST SETUP AND RESULTS

• SEU SIMULATION ON LVDT VOLTAGE ACQUISITION.

• WHAT HAPPENS TO THE POSITION?

22

DAC PCM1702 Radiation test setup

DUT DAC 1

Anti-latchup board

Ch1

Ch3

Ch2

Ch4

TESTER

GPIB

HP34970

Agilent E3648A

GPIB

DUT DAC 2

DUT DAC 3

Current Monitor +I -I

Power Supply +5V -5V

FPGAACTEL

USB-SERIAL

4

Ref DAC

DUT IN-BEAM

Temperature

23

PSI Beam conditionsRun DUT Flux

pp/cm2/sFluencepp/cm2

Cumulative Fluence

Dose rate (rad/s)

Cumulative TID [Gy]

45 DAC_Board 1 1,44E+08 1,98E+11 1,98E+11 4,58 105

46 DAC_Board 1 1,44E+08 1,60E+11 3,58E+11 4,64 191

47 DAC_Board 1 1,44E+08 9,80E+10 4,56E+11 4,58 243

48 DAC_Board 1 1,44E+08 2,20E+11 6,76E+11 4,63 361

49 DAC_Board 2 1,44E+08 2,00E+11 2,00E+11 4,20 100

50 DAC_Board 2 1,44E+08 4,10E+11 6,10E+11 4,51 320

Taken in consideration only for the current drift because of some problem at the anti-latch up circuit

Taken in consideration for the SEU after removing the anti-latch up board

OUTPUT ANALYSIS ON RUN 50

24NO SEU

25

Current supply (+5V) analysis in the runs 45-48

NO DRIFT

26

Current supply (-5V) analysis in the runs 45-48

DRIFT START AT 100 Gy

OUT OF SPEC ~ 200 Gy

27

SEU SIMULATION ON LVDT OUTPUTIf we want to simulate an SEU two parameter have to be considered:

1. SEU POSITION IN THE 16 BIT ADC REGISTER2. SEU POSITION IN THE ACQUIRED SINE WAVE

Wait until SEU on bit = 8 to see the SEU effects on the most significant BIT

Play ANIMATION

28

Maximum Error due to SEU on position evaluation