192 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 13, NO. 2, MARCH 2014
Design of Efficient Binary Comparatorsin Quantum-Dot Cellular Automata
Stefania Perri, Senior Member, IEEE, Pasquale Corsonello, Member, IEEE, and Giuseppe Cocorullo, Member, IEEE
Abstract—Quantum-dot cellular automata (QCA) are an attrac-tive emerging technology suitable for the development of ultra-dense low-power high-performance digital circuits. Efficient solu-tions have recently been proposed for several arithmetic circuits,such as adders, multipliers, and comparators. Nevertheless, sincethe design of digital circuits in QCA still poses several challenges,novel implementation strategies and methodologies are highly de-sirable. This paper proposes a new design approach oriented tothe implementation of binary comparators in QCA. New formula-tions of basic logic equations required to perform the comparisonfunction are proposed. The new strategy has been exploited in thedesign of two different comparator architectures and for severaloperands word lengths. With respect to existing counterparts, thecomparators proposed here exhibit significantly higher speed andreduced overall area.
Index Terms—Binary comparators, majority gates, quantum-dot cellular automata (QCA).
I. INTRODUCTION
QUANTUM-DOT cellular automata (QCA) technologyprovides a promising opportunity to overcome the ap-
proaching limits of conventional CMOS technology [1]–[6].For this reason, in recent years the design of logic circuits basedon QCA has received a great deal of attention, and special effortshave been directed towards arithmetic circuits, such as adders[7]–[14], multipliers [15]–[21], and comparators [22]–[28].
EVEN though comparators are key elements for a wide rangeof applications [29], [30], QCA implementations existing inthe literature are mainly provided for comparing two singlebits. Only few examples of comparators able to process n-bitoperands, with n > 2, are available [24], [26], [27]. The com-parator described in [22] simply computes the XNOR functionto establish whether two input bits a and b match each other.The structures proposed in [23]–[28] provide higher computa-tional capabilities, and circuits able to separately recognize allthe three possible conditions in which a = b, a > b, and a< b (here named full comparators) are described in [23], [24],and [27]. The 1-bit implementation proposed in [23] and then
Manuscript received June 11, 2013; revised September 26, 2013; acceptedDecember 11, 2013. Date of publication December 20, 2013; date of currentversion March 6, 2014. The review of this paper was arranged by AssociateEditor C. A. Moritz.
Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TNANO.2013.2295711
improved in [25], has been exploited in [27] to design a paralleln-bit full comparator. An example of serial structures is pro-vided in [24], whereas the n-bit comparator described in [26]can recognize only the case in which, A and B being the n-bit inputs, A ≥ B. Alternative QCA implementations of 1-bitfull comparators were recently proposed in [28]. With respectto other QCA designs, the latter exhibit reduced delays, areaoccupancy and number of used cells.
This paper focuses on the design of efficient parallel QCA-based n-bit full comparators. The main contribution of this paperis the introduction of a novel design methodology that allows lowcomputational time and very compact layouts to be achieved.In particular, original theorems and corollaries are stated anddemonstrated that directly impact on the QCA realizations ofsome basic Boolean functions used within the comparator ar-chitectures.
The novel theorems were applied to achieve innovative QCA-based structures of n-bit full comparators that were laid out andsimulated using the QCADesigner tool [31] for n ranging be-tween 2 and 32. As an example, one of the 32-bit comparatorsdesigned exploiting the proposed theory is implemented usingless than 2800 cells within an overall area of about 2.66 μm2 ;moreover, it requires only 15 clock cycles to complete the op-eration.
The rest of the paper is organized as follows: a brief back-ground of the QCA design approach and existing QCA imple-mentations of binary comparators is given in Section II; the newtheorems and corollaries are then enunciated and demonstratedin Section III; comparators designed exploiting the novel theo-rems are proposed in Section IV that also presents comparisonresults with existing designs; finally, in Section V, conclusionsare drawn.
II. BACKGROUND AND RELATED WORKS
The basic element of a nanostructure based on QCA is asquare cell with four quantum dots and two free electrons. Thelatter can tunnel through the dots within the cell, but, owingto Coulombic repulsion, they will always reside in oppositecorners [1], thus leading to only two possible stable states, alsonamed polarizations. Locations of the electrons in the cell areassociated with the binary states 1 and 0.
Adjacent cells interact through electrostatic forces and tendto align their polarizations. However, QCA cells do not haveintrinsic data flow directionality. Therefore, to achieve control-lable data directions, the cells within a QCA design are parti-tioned into the so-called clock zones that are progressively as-sociated with four clock signals, each phase shifted by 90◦. Thisclock scheme, named the zone clocking scheme, makes the QCA
PERRI et al.: DESIGN OF EFFICIENT BINARY COMPARATORS IN QUANTUM-DOT CELLULAR AUTOMATA 193
designs intrinsically pipelined, since each clock zone behaveslike a D-latch [20].
QCA cells are used for both logic structures and intercon-nections that can exploit either the coplanar cross or the bridgetechnique [1], [2], [6], [31], [32]. The fundamental logic gatesinherently available within the QCA technology are the inverterand the majority gate (MG). Given three inputs a, b and c, theMG performs the logic function reported in (1) provided that allinput cells are associated with the same clock signal clkx (withx ranging from 0 to 3), whereas the remaining cells of the MGare associated with the clock signal clkx+1
M (a, b, c) = a · b + a · c + b · c (1)
There are several QCA designs of comparators in the literature[22]–[28]. A 1-bit binary comparator receives two bits a and bas inputs and establishes whether they are equal, less than orgreater than each other. These possible states are representedthrough three output signals, here named AeqB, AbigB,BbigA,that are asserted, respectively, when a = b, a > b, and a < b. Fullcomparators are those that can separately identify all the abovecases, whereas non-full comparators recognize just one or twoof them. As an example, the comparator designed in [22] anddepicted in Fig. 1(a) can verify only whether a = b. Conversely,the circuits shown in Fig. 1(b) and (c), proposed in [23] and [24],are full comparators. The latter also exploits two 1-bit registersD to process n-bit operands serially from the least significantbit to the most significant one.
With the main objective of reducing the number of wirecrossings, which is still a big challenge of QCA designs[33]–[35], in [25] the universal logic gate (ULG) f(y1 , y2 , y3) =M(M(y1 , y2 , 0),M(y1 , y3 , 1), 1) was proposed and then usedto implement the comparator illustrated in Fig. 1(d). It isworth noting that, two n-bit numbers A(n−1:0) = an−1 . . . a0and B(n−1:0) = bn−1 . . . b0 can be processed by cascading n in-stances of the 1-bit comparator. Each instance receives as inputsthe ith bits ai and bi (with i = n − 1, . . . , 0) of the operandsand the signals AbigB(i−1:0) and BbigA(i−1:0) . The former isasserted when the subword A(i−1:0) = ai−1 . . . a0 represents abinary number greater than B(i−1:0) = bi−1 . . . b0 . In a similarway, BbigA(i−1:0) is set to 1 when A(i−1:0) < B(i−1:0) . Theoutputs AbigB(i:0) and BbigA(i:0) directly feed the next stage.It can be seen that this circuit does not identify the case in whichA = B, therefore it cannot be classified as a full-comparator.
The design described in [26] exploits a tree-based (TB) ar-chitecture and exhibits a delay that in theory logarithmicallyincreases with n. The 2-bit version of such designed compara-tor is illustrated in Fig. 1(e).
Also the full comparator proposed in [27] exploits a TB ar-chitecture to achieve high speed. As shown in Fig. 1(f), where4-bit operands are assumed, one instance of the 1-bit comparatorpresented in [23] is used for each bit position. The intermediateresults obtained in this way are then further processed through aproper number of cascaded 2-input OR and AND gates imple-mented by means of MGs having one input permanently set to1 and 0, respectively.
Analyzing existing QCA implementations of binary compara-tors it can be observed that they were designed directly mapping
the basic Boolean functions consolidated for the CMOS logicdesigns to MGs and inverters, or ULGs. Unfortunately, in thisway the computational capability offered by each MG couldbe underutilized [13], [36], [37]. As a consequence, both thecomplexity and the overall delay of the resulting QCA designscould be increased in vain.
III. NEW FORMULATIONS FOR QCA IMPLEMENTATIONS
OF n-BIT FULL COMPARATORS
In this section, four original theorems and two corollariesare enunciated that can significantly increase the speed per-formances of QCA-based designs of full comparators and cansignificantly reduce the number of used MGs and inverters with
194 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 13, NO. 2, MARCH 2014
respect to existing comparators, thus reducing also the numberof used cells and the overall active area. The Appendix at theend of the paper provides the proofs of the novel theorems andcorollaries.
The novel formulations can be exploited in the design of n-bitfull comparators splitting the operands A(n−1:0) = an−1 . . . a0and B(n−1:0) = bn−1 . . . b0 into a proper number of 2-bit and3-bit subwords that can be compared applying Theorems 1 and2. The intermediate results obtained in this way can be thenfurther processed by applying Theorems 3 and 4 together withCorollaries 1 and 2.
Theorem 1: If A(k−1:k−2) = ak−1ak−2 and B(k−1:k−2) =bk−1bk−2 , with k = 2, 4, . . ., n – 2, n, are two 2-bit sub-words of the n-bit numbers A(n−1:0) and B(n−1:0) , respectively,then AbigB(k−1:k−2) as defined in (2) is equal to 1 if and onlyif A(k−1:k−2) > B(k−1:k−2) ;BbigA(k−1:k−2) as defined in (3) isequal to 0 if and only if A(k−1:k−2) < B(k−1:k−2)
AbigB(k−1:k−2) = M(ak−1 , bk−1 , ak−2
)
· M(ak−1 , bk−1 , bk−2
)(2)
BbigA(k−1:k−2) = M(ak−1 , bk−1 , ak−2
)
+ M(ak−1 , bk−1 , bk−2
)(3)
Theorem 2: If A(k−1:k−3) =ak−1ak−2ak−3 and B(k−1:k−3) =bk−1bk−2bk−3 , with k = 3, 6, . . . , n − 3, n, are 3-bit subwordsof the n-bit numbers A(n−1:0) and B(n−1:0) , respectively, thenAbigB(k−1:k−3) as defined in (4) is equal to 1 if and only ifA(k−1:k−3) > B(k−1:k−3) ; BbigA(k−1:k−3) as given in (5) isequal to 0 if and only if A(k−1:k−3) < B(k−1:k−3)
AbigB(k−1:k−3) = M(M(ak−1 , bk−1 , ak−2
),
M(ak−1 , bk−1 , bk−2
), ak−3 · bk−3) (4)
BbigAk−1:k−3 = M(M(ak−1 , bk−1 , ak−2
),
M(ak−1 , bk−1 , bk−2
), ak−3 + bk−3). (5)
Theorem 3: Given two n-bit numbers A(n−1:0) and B(n−1:0) ,(6) gives AbigB(n−1:0) = 1 if and only if A(n−1:0) > B(n−1:0) ,whereas (7) gives BbigA(n−1:0) = 0 if and only if A(n−1:0) <B(n−1:0) .
AbigB(n−1:0) = M(M(an−1 , bn−1 , an−2
),
M(an−1 , bn−1 , bn−2
), AbigB(n−3:0)) (6)
BbigA(n−1:0) = M(M(an−1 , bn−1 , an−2
),
M(an−1 , bn−1 , bn−2
), BbigA(n−3:0)) (7)
Theorem 4: If A(n−1:0) and B(n−1:0) are two n-bit numbers,AbigB(n−1:n−3) and BbigA(n−1:n−3) being computed by (4) and(5), respectively, then AbigB(n−1:0) as defined in (8) is equal to1 if and only if A(n−1:0) > B(n−1:0) , whereas BbigA(n−1:0) asdefined in (9) is equal to 0 if and only if A(n−1:0) < B(n−1:0)
AbigB(n−1:0) = M(AbigB(n−1:n−3) ,
BbigA(n−1:n−3) , AbigB(n−4:0)) (8)
BbigA(n−1:0) = M(AbigB(n−1:n−3) ,
BbigA(n−1:n−3) , BbigA(n−4:0)). (9)
Corollary 1: Let’s consider two n-bit numbers A(n−1:0)and B(n−1:0) , and let’s suppose that they are split intothe subwords A(n−1:h) , A(h−1:0) , B(n−1:h) and B(h−1:0) . IfAbigB(n−1:h) , AbigB(h−1:0) , BbigA(n−1:h) and BbigA(h−1:0)are computed by applying Theorems 3 and 4, then AbigB(n−1:0)as defined in (10) is equal to 1 if and only if A(n−1:0) > B(n−1:0) ,whereas BbigA(n−1:0) as defined in (11) is equal to 0 if and onlyif A(n−1:0) < B(n−1:0) .
Corollary 2: Given two n-bit numbers A(n−1:0) and B(n−1:0) ,if AbigB(n−1:0) and BbigA(n−1:0) are computed by applyingTheorems 1, 2, 3, and 4 and/or Corollary 1, then AeqB(n−1:0)defined in (12) is equal to 1 if and only if A(n−1:0) = B(n−1:0)
AeqB(n−1:0) = M(AbigB(n−1:0) , BbigA(n−1:0) , 0
). (12)
In the following, it is demonstrated that several strategies canbe adopted at the circuit level to apply the above demonstratedformulations and, consequently, that different architectures andQCA implementations can be achieved for an n-bit full com-parator. In order to exploit the novel approach, the operandsA(n−1:0) and B(n−1:0) are split into a proper number of 2- and3-bit subwords that are compared applying Theorems 1 and 2.The results obtained comparing 2- and 3-bit subwords are thencombined by applying Theorems 3 and 4 together with Corol-laries 1 and 2.
IV. DESIGNING BINARY COMPARATORS EXPLOITING
THE NEW THEOREMS
The circuits illustrated in Fig. 2 were designed to implementin QCA the novel equations demonstrated in the previous Sec-tion. The generic module Ti, with i ranging between 1 and 4,implements the equations enunciated in the ith theorem, whereasC1 and C2 compute the signals AbigB(k−1:0) , BbigA(k−1:0) , andAeqB(k−1:0) as shown above in Corollaries 1 and 2, respectively.
As examples of application, the above QCA modules havebeen used to design two different structures of full compara-tors here named cascade-based and TB architectures. However,many other structures can be designed by combining the basicmodules in different manners.
A. Novel QCA Comparators
The first proposed comparator exploits a cascade-based (CB)architecture. To explain better how the overall computation isperformed, the schematic diagram illustrated in Fig. 3 is pro-vided. It shows a possible implementation of a 32-bit comparatorbased on the proposed theory. Following the criterion illustrated
PERRI et al.: DESIGN OF EFFICIENT BINARY COMPARATORS IN QUANTUM-DOT CELLULAR AUTOMATA 195
in Fig. 3, an n-bit CB full comparator designed as proposed hereuses: n/3 instances of T1 and/or T2; n/3 cascaded instances ofT4 through which the signals AbigB(n−1:0) and BbigA(n−1:0)are computed; and one instance of C2, needed to compute alsoAeqB(n−1:0) . Circles visible in Fig. 3 indicate the additionalclock phases that have to be inserted on wires to guarantee thecorrect synchronization of the overall design.
The CB full comparator was designed for operands wordlengths ranging from 2 to 32 and using, for n > 2, the splitcriterion summarized in Table I. Obviously, alternative splitscould be used.
TABLE ISPLITTING CRITERION ADOPTED IN THE CB COMPARATORS
As it is well known, the number of cascaded MGs within theworst computational path of a QCA design directly affects thedelay achieved. In fact, each MG introduces one clock phase inthe overall delay. From Fig. 2, it can be seen that the modules T1and T2 contribute to the computational path with one inverterand two MGs. Each instance of T4 introduces one more MG,whereas C2 is responsible for one MG and one inverter. As aconsequence, the critical computational path of the novel n-bitCB full comparator consists of n/3+ 3 MGs and 2 inverters. Asan example, the 32-bit implementation depicted in Fig. 3 hasthe worst-case path made up of 13 MGs and 2 inverters.
As always happens in CB computational architectures, thenumber of MGs within the computational path of the above-described comparator linearly increases with n. An alternativesolution presented here adopts a TB architecture to achieveshorter computational paths. When this approach is exploited,several implementations of an n-bit full comparator can be de-signed differently combining the novel theorems and corollar-ies, as well as their QCA implementations depicted in Fig. 2.The TB comparators implement the comparison function recur-sively. The operands A and B are preliminarily partitioned asA = AMSBALSB and B = BMSBBLSB . The portions AMSB andBMSB are compared independently of the portions ALSB andBLSB . The depth of the recursion directly impacts the wholearchitecture. Examples of TB structures designed for 16- and32-bit comparators are illustrated in Fig. 4. In Fig. 4(b) and (d),the recursion with its minimum depth is adopted. The portionsAMSB and BMSB , as well as the portions ALSB and BLSB , areseparately compared trough two independent CB architectures.The overall result is finally built with the modules C1 and C2.Fig. 4(a) and (c) shows comparators designed adopting deeperrecursions.
In the following of the paper, the 16- and 32-bit TB imple-mentations illustrated in Fig. 4(b) and (d) are deeply analyzed.Referring to the QCA modules depicted in Fig. 2, it can be easilyverified that the former uses 35 MGs and 17 inverters and itscritical computational path consists of 7MGs and 2 inverters,whereas the latter utilizes 83 MGs and 33 inverters and it has aworst-case path composed by 9 MGs and 2 inverters.
B. Results
Preliminary results obtained for the novel comparators at sev-eral operands word lengths are reported in Table II and com-pared to the pre-implementation characteristics furnished in theoriginal papers for the parallel comparators described in [26]and [27] for operands wider than 1 bit. The design complexity
196 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 13, NO. 2, MARCH 2014
Fig. 4. Examples of novel TB comparators with: (a) and (b) 16-bit operands; (c) and (d) 32-bit inputs.
TABLE IIPREIMPLEMENTATION RESULTS
TABLE IIISIMULATION PARAMETERS
Fig. 5. Novel 16-bit comparators: (a) the CB; (b) the TB.
of the comparators examined is reported in terms of number ofMGs and inverters required in the overall designs, and number ofMGs within the worst computational paths. The computationalcapability of each architecture is also specified.
PERRI et al.: DESIGN OF EFFICIENT BINARY COMPARATORS IN QUANTUM-DOT CELLULAR AUTOMATA 197
Fig. 6. QCA implementation of the novel 32-bit comparators: (a) the CB; (b) the TB.
Fig. 7. Simulation results obtained for the novel 16-bit comparators: (a) the CB; (b) the TB.
It can be seen that, exploiting the formulations introduced inthis paper, the novel comparators can achieve lower complex-ity than their competitors, especially when wider operands areprocessed. Among the compared architectures, that describedin [26] theoretically has a shorter critical path for all the con-sidered n. However, it should be noted that it is not a full com-parator. Moreover, the QCA implementations of the TB archi-tectures adopted in [26] and [27] require overlong wires. Asdeeply discussed in [1], [2], [6], in order to achieve robust QCAdesigns, a maximum of 15 or 16 cascaded cells per clock zoneshould be used. As a consequence, overlong wires introduceadditional clock phases that, depending on the operands wordlength, can significantly exceed the number of cascaded MGs
reported in Table II, thus compromising the actually achievablespeed performances. As shown in the following, the novel com-parators have been implemented in QCA taking this aspect intoaccount. Proper layout strategies have been adopted that allowthe number of additional clock phases due to overlong wires tobe limited to 1 independently of the operands word length andin both cascade-based and TB architectures proposed here.
The novel comparators were implemented using the QCADe-signer tool [31] adopting the following rules: the QCA cells are18 nm wide and 18 nm high; the cells are placed on a grid witha cell center-to-center distance of 20 nm; there is at least onecell spacing between adjacent wires; the quantum dot diameteris 5 nm; the multilayer wire crossing structure is exploited; a
198 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 13, NO. 2, MARCH 2014
Fig. 8. Simulation results obtained for the novel 32-bit comparators: (a) the CB; (b) the TB.
TABLE IVPOSTIMPLEMENTATION COMPARISON RESULTS
maximum of 16 cascaded cells and a minimum of 2 cascadedcells per clock zone are assumed.
The coherence vector engine was used for simulations withthe options summarized in Table III.
Layouts implemented for the 16- and 32-bit versions of thenovel comparators are illustrated in Figs. 5 and 6, respectively.It is worth pointing out that the layouts of the CB comparatorsexploit only forwards paths: that is the intermediate results ob-tained for the least significant bits of the operands are routedtowards the most significant ones (i.e., from right to left). Onthe contrary, in order to limit the number of overlong wires,the layouts of the TB comparators also use backward paths.From Figs. 5(b) and 6(b), it can be seen that forward paths arerouted for the least significant bits, whereas backward paths areexploited for the most significant bits.
Some simulation results obtained for the 16- and the 32-bitcomparators are depicted in Figs. 7 and 8 that also show the timeat which the first valid results are outputted. It is worth notingthat the CB circuits require 10 and 15 latency clock phases toobtain the first 16- and 32-bit valid outputs, respectively. As anexample, the 15 clock phases of the 32-bit comparator are as fol-lows: 1 clock phase is needed for inputs acquisition; the signalsAbigB(1:0) and BbigA(1:0) related to the least significant bit po-sitions are then computed within the 2 subsequent clock phases;one additional phase is due to the overlong wire highlightedin Fig. 6(a); ten phases are required for computing the signalsAbigB(j :0) and BbigA(j :0) , with j = 4, 7,. . ., 28, 31; finally, onemore phase is needed to compute the output AeqB(31:0) .
The 16- and 32-bit TB comparators have a latency of 8 and 11clock phases, respectively, and also in this case at most there isonly one overlong wire [highlighted in Fig. 6(b)] in the layout.
Post layout characteristics, such as, cell count, overall size,delay and number of clock phases, are reported in Table IV for allthe examined comparators. Results obtained demonstrate that,at a parity of the operands word length, when compared to [27],which is the only parallel comparator existing in the literature forwhich QCA implementations have been characterized also for n> 2, the novel CB implementation is over 60% faster, occupiesup to 81% smaller area and uses over 56% less cells. Resultsreported in Table IV demonstrate that speed performances canbe further increased by using the novel TB structure, which alsoexhibits limited area and cells requirements.
As expected, for the TB comparators presented in [26] and[27], several additional clock phases exceeding the number ofcascaded MGs within the computational path are introducedin the layout due to overlong wires. For example, in the caseof n = 8, the comparator [27] has 9 cascaded MGs within itscritical path, but the operation is actually performed within 18clock phases. On the contrary, as a further merit, for the newcomparators the number of clock phases exceeding the numberof MGs within the worst computational path is at most two,independently of n. Only one of these additional clock phases
PERRI et al.: DESIGN OF EFFICIENT BINARY COMPARATORS IN QUANTUM-DOT CELLULAR AUTOMATA 199
Fig. 9. Possible cases occurring when two 2-bit subwords are compared.
is due to overlong wires, whereas the other one is needed for theinputs acquisition.
V. CONCLUSION
A new methodology useful to design binary comparators inQCA has been presented. It is based on innovative formulationsthat allow increased speed performances and reduced overallsizes to be achieved with respect to the existing competitors.
The novel comparators split the received n-bit inputs into aproper number of 2- and 3-bit subwords that are processed inparallel through 2- and 3-bit comparators designed by applyingtheorems demonstrated here.
Thanks to the basic logic and layout strategies adopted, a32-bit CB full comparator designed as described in this paperexhibits a delay of only 3 + (3/4) clock cycles, occupies anactive area of 2.66 μm2 , and achieves an area-delay product lessthan 10.
When the alternative TB architecture presented here is ex-ploited, the delay is further reduced to 2 + (3/4) clock cycles;the active area is ∼2.9 μm2 , whereas the area-delay product isless than 8.
APPENDIX
This Appendix provides proofs of the theorems and corollar-ies enunciated in Section III.
Proof of Theorem 1: Equations (2) and (3) can be easilyproven referring to the truth table reported in Fig. 9, which showsthat the terms M(ak−1 , bk−1 , ak−2) and M(ak−1 , bk−1 , bk−2)are both equal to 1 only when A(k−1:k−2) > B(k−1:k−2) ,whereas they are both equal to 0 only when A(k−1:k−2) <B(k−1:k−2) .
Proof of Theorem 2: Fig. 9 shows that, if A(k−1:k−2)
> B(k−1:k−2) ,M(ak−1 , bk−1 , ak−2) = M(ak−1 , bk−1 , bk−2)= 1 and then the majority functions used in(4) and (5) provide AbigB(k−1:k−3) = 1 andBbigA(k−1:k−3) = 1, independently of ak−3 · bk−3 andak−3 + bk−3 , respectively. Analogously, when A(k−1:k−2) <
B(k−1:k−2) , both M(ak−1 , bk−1 , ak−2) and M(ak−1 ,
bk−1 , bk−2) are equal to 0, therefore AbigB(k−1:k−3) = 0
and BbigA(k−1:k−3) = 0, independently of ak−3 · bk−3
and ak−3 + bk−3 . On the contrary, with A(k−1:k−2) =B(k−1:k−2) ,M(ak−1 , bk−1 , ak−2) and M(ak−1 , bk−1 , bk−2)assume opposite values, therefore the results provided by(4) and (5) depend on ak−3 · bk−3 and ak−3 + bk−3 . In thiscase, the only condition for which A(k−1:k−3) > B(k−1:k−3)
occurs if ak−3 = 1 and bk−3 = 0 (i.e., bk−3 = 1). When ittakes place, AbigB(k−1:k−3) = 1; otherwise, it is equal to0. It can be also observed that, A(k−1:k−2) being equal toB(k−1:k−2) , the condition A(k−1:k−3) < B(k−1:k−3) is satisfiedonly if ak−3 = 0 and bk−3 = 1 (i.e., bk−3 = 0). When it occurs,BbigA(k−1:k−3) = 0; otherwise, it is equal to 1.
Proof of Theorem 3: Recursively applying (6) to the termAbigB(n−3:0) , we obtain
AbigB(n−3:0) = M(M
(an−3 , bn−3 , an−4
),
M(an−3 , bn−3 , bn−4
), AbigB(n−5:0)
)
and in turn
AbigB(n−5:0) = M(M
(an−5 , bn−5 , an−6
),
M(an−5 , bn−5 , bn−6
), AbigB(n−7:0)
)
and so on till (6) is rewrittenas follows, with h being equal to 1or 2
AbigB(n−1:0) = M(M
(an−1 , bn−1 , an−2
),
M(an−1 , bn−1 , bn−2
), AbigB(n−3:0)
)
= M(M(an−1 , bn−1 , an−2
),M
(an−1 , bn−1 , bn−2
),
M(M(an−3 , bn−3 , an−4
),M
(an−3 , bn−3 , bn−4
),
AbigB(n−5:0)))
= M(M(an−1 , bn−1 , an−2
),M
(an−1 , bn−1 , bn−2
),
M(M(an−3 , bn−3 , an−4
),M
(an−3 , bn−3 , bn−4
), . . . ,
M(M(ah+2 , bh+2 , ah+1
),M
(ah+2 , bh+2 , bh+1
),
AbigB(h :0)))).
200 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 13, NO. 2, MARCH 2014
Analogously, (7) can be rewritten as shown in the expressionbelow.
By applying Theorem 1 to the 2-bit subwords A(h+2:h+1) =ah+2ah+1 and B(h+2:h+1) = bh+2bh+1 , and Theorems 2 and 3to the subwords A(h :0) and B(h :0) , we obtain that
AbigB(h+2:0) = M(M
(ah+2 , bh+2 , ah+1
),
M(ah+2 , bh+2 , bh+1
), AbigB(h :0)
)
is equal to 1 if and only if A(h+2:0) > B(h+2:0) , and in turn that
AbigB(h+4:0) = M(M
(ah+4 , bh+4 , ah+3
),
M(ah+4 , bh+4 , bh+3
), AbigB(h+2:0)
)
provides 1 only when A(h+4:0) > B(h+4:0) , and so on till
AbigB(n−1:0) = M(M
(an−1 , bn−1 , an−2
),
M(an−1 , bn−1 , bn−2
), AbigB(n−3:0)
)
is obtained, which is equal to 1 if and only if A(n−1:0) >B(n−1:0) .
Similarly, we have that
BbigA(h+2:0) = M(M
(ah+2 , bh+2 , ah+1
),
M(ah+2 , bh+2 , bh+1
), BbigA(h :0)
)
is equal to 0 if and only if A(h+2:0) < B(h+2:0) , and in turn that
BbigA(h+4:0) = M(M
(ah+4 , bh+4 , ah+3
),
M(ah+4 , bh+4 , bh+3
), BbigA(h+2:0)
)
provides 0 only when A(h+4:0) < B(h+4:0) , and so on till
BbigA(n−1:0) = M(M
(an−1 , bn−1 , an−2
),
M(an−1 , bn−1 , bn−2
), BbigA(n−3:0)
)
is obtained, which is equal to 0 if and only if A(n−1:0) <B(n−1:0) .
Proof of Theorem 4: Recursively applying (8) to the termAbigB(n−4:0) , we obtain
AbigB(n−4:0) = M(AbigB(n−4:n−6) ,
BbigA(n−4:n−6) , AbigB(n−7:0))
and in turn
AbigB(n−7:0) =(AbigB(n−7:n−9) ,
BbigA(n−7:n−9) , AbigB(n−10:0))
and so on till (8) is rewritten as follows, with h being equal to 1or 2.
In a similar way, (9) can be rewritten as shown in the expres-sion below
BbigA(n−1:0) = M(AbigB(n−1:n−3) ,
BbigA(n−1:n−3) , BbigA(n−4:0))
= M(AbigB(n−1:n−3) , BbigA(n−1:n−3) ,
M(AbigB(n−4:n−6) , BbigA(n−4:n−6) ,
BbigA(n−7:0)))
= M(AbigB(n−1:n−3) , BbigA(n−1:n−3) ,
M(AbigB(n−4:n−6) , BbigA(n−4:n−6) , . . . ,
M(AbigB(h+3:h+1) , BbigA(h+3:h+1) ,
BbigA(h :0)))).
By applying Theorem 2 to the 3-bit subwords A(h+3:h+1) andB(h+3:h+1) , and Theorems 2 and 3 to the subwords A(h :0) andB(h :0) , we can derive that
AbigB(h+3:0) = M(AbigB(h+3:h+1) ,
BbigA(h+3:h+1) , AbigB(h :0))
is equal to 1 if and only if A(h+3:0) > B(h+3:0) and that
BbigA(h+3:0) = M(AbigB(h+3:h+1) ,
BbigA(h+3:h+1) , BbigA(h :0))
is equal to 0 if and only if A(h+3:0) < B(h+3:0) . In turn, it alsoarises that
AbigB(h+6:0) = M(AbigB(h+6:h+4) ,
BbigA(h+6:h+4) , AbigB(h+3:0))
is equal to 1 if and only if A(h+6:0) > B(h+6:0) and that
BbigA(h+6:0) = M(AbigB(h+6:h+4) ,
BbigA(h+6:h+4) , BbigA(h+3:0))
PERRI et al.: DESIGN OF EFFICIENT BINARY COMPARATORS IN QUANTUM-DOT CELLULAR AUTOMATA 201
is equal to 0 if and only if A(h+6:0) < B(h+6:0) , and so on till
AbigB(n−1:0) = M(AbigB(n−1:n−3) ,
BbigA(n−1:n−3) , AbigB(n−4:0))
and
BbigA(n−1:0) = M(AbigB(n−1:n−3) ,
BbigA(n−1:n−3) , BbigA(n−4:0))
are obtained. The former is equal to 1 if and only if A(n−1:0) >B(n−1:0) , whereas the latter is equal to 0 if and only if A(n−1:0) <B(n−1:0) .
Proof of Corollary 1:From Theorems 3 and 4, we know that,AbigB(n−1:h) = BbigA(n−1:h) = 1 if and only if A(n−1:h) >
B(n−1:h) . In this case, AbigB(n−1:0) = BbigA(n−1:0) = 1 in-dependently of AbigB(h−1:0) and BbigA(h−1:0) . Analogously,AbigB(n−1:h) = BbigA(n−1:h) = 0 if and only if A(n−1:h) <
B(n−1:h) . This case leads to AbigB(n−1:0) = BbigA(n−1:0) = 0independently of AbigB(h−1:0) and BbigA(h−1:0) .
Theorems 3 and 4 also demonstrate that, A(n−1:h) beingequal to B(n−1:h) , AbigB(n−1:h) = 0 and BbigA(n−1:h) = 1.In this case, the results provided by (10) and (11) depend onAbigB(h−1:0) and BbigA(h−1:0) . The former is equal to 1 onlywhen A(h−1:0) > B(h−1:0) , this implies A(n−1:0) > B(n−1:0) ,whereas the latter is equal to 0 only if A(h−1:0) < B(h−1:0) , thatis, if A(n−1:0) < B(n−1:0) . Consequently, when the first caseoccurs, (10) and (11) provide AbigB(n−1:0) = BbigA(n−1:0) =1. On the contrary, if the second case takes place, bothAbigB(n−1:0) and BbigA(n−1:0) are equal to 0.
Proof of Corollary 2: From Theorems 1, 2, 3, and 4 and Corol-lary 1, we know that AbigB(n−1:0) = 1 if and only if A(n−1:0) >
B(n−1:0) and that BbigA(n−1:0) = 0 if and only if A(n−1:0) <B(n−1:0) . This implies that, when the case A(n−1:0) = B(n−1:0)occurs, only one condition is possible: AbigB(n−1:0) = 0 andBbigA(n−1:0) = 1. Consequently, the majority function used in(12) provides AeqB(n−1:0) = 1, otherwise it outputs 0.
REFERENCES
[1] C. S. Lent, P. D. Tougaw, W. Porod, and G. H. Bernestein, “Quantumcellular automata,” Nanotechnology, vol. 4, no. 1, pp. 49–57, 1993.
[2] M. T. Niemer and P. M. Kogge, “Problems in designing with QCAs: Lay-out = timing,” Int. J. Circuit Theory Appl., vol. 29, pp. 49–62, 2001.
[3] G. H. Bernstein, A. Imre, V. Metlushko, A. Orlov, L. Zhou, L. Ji, G. Csaba,and W. Porod, “Magnetic QCA systems,” Microelectron. J., vol. 36,pp. 619–624, 2005.
[4] J. Huang and F. Lombardi, Design and Test of Digital Circuits by Quantum-Dot Cellular Automata. Norwood, MA, USA: Artech House, 2007.
[5] W. Liu, L. Lu, M. O’Neill, and E. E. Swartzlander Jr., “Design rules forquantum-dot cellular automata,” in Proc. IEEE Int. Symp. Circuits Syst.(ISCAS), Rio De Janeiro, Brazil, May 2011, pp. 2361–2364.
[6] K. Kim, K. Wu, and R. Karri, “Towards designing robust QCA archi-tectures in the presence of sneak noise paths,” in Proc. IEEE Design,Automation Test Eur. Conf. Exhib. (DATE), Munich, Germany, Mar. 2005,pp. 1214–1219.
[7] K. Navi, M. H. Moaiyeri, R. F. Mirzaee, O. Hashemipour, andB. M. Nezhad, “Two new low-power full adders based on majority-notgates,” Microelectron. J., vol. 40, pp. 126–130, 2009.
[8] H. Cho and E. E. Swartzlander Jr., “Adder design and analyses forquantum-dot cellular automata,” IEEE Trans. Nanotechnol., vol. 6, no. 3,pp. 374–383, May 2007.
[9] H. Cho and E. E. Swartzlander Jr., “Adder and multiplier design inquantum-dot cellular automata,” IEEE Trans. Comput., vol. 58, no. 6,pp. 721–727, Apr. 2009.
[10] V. Pudi and K. Sridharan, “Efficient design of a hybrid adder in quantum-dot cellular automata,” IEEE Trans. VLSI Syst., vol. 19, no. 9, pp. 1535–1548, Jul. 2011.
[11] M. Gladshtein, “Quantum-dot cellular automata serial decimal adder,”IEEE Trans. Nanotechnol., vol. 10, no. 6, pp. 1377–1382, Nov. 2011.
[12] V. Pudi and K. Sridharan, “Low complexity design of ripple carry andBrent-Kung adders in QCA,” IEEE Trans. Nanotechnol., vol. 11, no. 1,pp. 105–119, Jan. 2012.
[13] S. Perri and P. Corsonello, “New methodology for the design of efficientbinary circuits addition in QCA,” IEEE Trans. Nanotechnol., vol. 11, no. 6,pp. 1192–1200, Nov. 2012.
[14] V. Pudi and K. Sridharan, “New decomposition theorems on majoritylogic for low-delay adder designs in quantum dot cellular automata,”IEEE Trans. Circuits Syst. II: Exp. Brief, vol. 59, no. 10, pp. 678–682,Oct. 2012.
[15] H. Cho and E. E. Swartzlander Jr., “Serial parallel multiplier design inquantum-dot cellular automata,” in Proc. IEEE Symp. Comput. Arithmetic,2007, pp. 7–15.
[16] S. W. Kim and E. E. Swartzlander Jr., “Parallel multipliers for quantum-dot cellular automata,” in Proc. IEEE Nanotechnol. Mater. Devices Conf.,2009, pp. 68–72.
[17] S. W. Kim and E. E. Swartzlander Jr., “Multipliers with coplanar crossingsfor quantum-dot cellular automata,” in Proc. IEEE Int. Conf. Nanotech-nol., 2010, pp. 953–957.
[18] W. Liu, L. Lu, M. O’Neill, and E. E. Swartzlander Jr., “Montgomerymodular multiplier design in quantum-dot cellular automata using cut-setretiming,” in Proc. IEEE Int. Conf. Nanotechnol., 2010, pp. 205–210.
[19] L. Lu, W. Liu, M. O’Neill, and E. E. Swartzlander Jr., “QCA systolicmatrix multiplier,” in Proc. IEEE Annu. Symp. VLSI, 2010, pp. 149–154.
[20] J. D. Wood and D. Tougaw, “Matrix multiplication using quantum-dot cel-lular automata to implement conventional microelectronics,” IEEE Trans.Nanotechnol., vol. 10, no. 5, pp. 1036–1042, Sep. 2011.
[21] L. Lu, W. Liu, M. O’Neill, and E. E. Swartzlander Jr., “QCA sys-tolic array design,” IEEE Trans. Comput., vol. 62, no. 3, pp. 548–560,Mar. 2013.
[22] J. R. Janulis, P. D. Tougaw, S. C. Henderson, and E. W. Johnson, “Serialbit-stream analysis using quantum-dot cellular automata,” IEEE Trans.Nanotechnol., vol. 3, no. 1, pp. 158–164, Mar. 2004.
[23] K. Qiu and Y. Xia, “Quantum-dots cellular automata comparator,” in Proc.Int. Conf. ASIC, 2007, pp. 1297–1300.
[24] B. Lampreht, L. Stepancic, I. Vizec, and B. Zankar, “Quantum-dot cellularautomata serial comparator,” in Proc. EUROMICRO Conf. Digital Syst.Design Architectures, Methods Tools, 2008, pp. 447–452.
[25] Y. Xia and K. Qiu, “Design and application of universal logic gate basedon quantum-dot cellular automata,” in Proc. IEEE Int. Conf. Commun.Technol., 2008, pp. 335–338.
[26] M. D. Wagh, Y. Sun, and V. Annampedu, “Implementation of comparisonfunction using quantum-dot cellular automata,” in Proc. Nanotechnol.Conf. Trade Show, 2008, pp. 76–79.
[27] Y. Xia and K. Qiu, “Comparator design based on quantum-dot cellu-lar automata,” J. Electron. Inf. Technol., vol. 31, no. 6, pp. 1517–1520,2009.
[28] S. Ying, T. Pei, and L. Xiao, “Efficient design of QCA optimal universallogic gate ULG.2 and its application,” in Proc. Int. Conf. Comput. Appl.Syst. Modeling (ICCASM), 2010, pp. 392–396.
[29] S. Perri and P. Corsonello, “Fast low-cost implementation of single-clock-cycle binary comparator,” IEEE Trans. Circuits Syst. II: Exp. Briefs,vol. 55, no. 12, pp. 1239–1243, Dec. 2008.
[30] P. Chuang, D. Li, and M. Sachdev, “A low-power high-performance single-cycle tree-based 64-bit binary comparator,” IEEE Trans. Circuits Syst.-II:Exp. Briefs, vol. 59, no. 2, pp. 108–112, Feb. 2012.
[31] K. Walus and G. A. Jullien, “Design tools for an emerging soc technology:Quantum-dot cellular automata,” Proc. IEEE, vol. 94, no. 6, pp. 1225–1244, Jun. 2006.
[32] S. Bhanja, M. Ottavi, S. Pontarelli, and F. Lombardi, “QCA circuits forrobust coplanar crossing,” J. Electron. Testing: Theory Appl., vol. 23,no. 2, pp. 193–210, 2007.
[33] A. Gin, P. D. Tougaw, and S. Williams, “An alternative geometry forquantum dot cellular automata,” J. Appl. Phys., vol. 85, no. 12, pp. 8281–8286, Jun. 1999.
[34] A. Chaudhary, D. Z. Chen, X. S. Hu, and M. T. Niemer, “Fabricatableinterconnect and molecular QCA circuits,” IEEE Trans. Comput. AidedDesign Integr. Circuits Syst., vol. 26, no. 11, pp. 1977–1991, Nov. 2007.
202 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 13, NO. 2, MARCH 2014
[35] M. Janez, P. Pecar, and M. Mraz, “Layout design of manufacturablequantum-dot cellular automata,” Microelectron. J., vol. 43, pp. 501–513,2012.
[36] R. Zhang, K. Walus, W. Wang, and G. A. Jullien, “A method of majoritylogic reduction for quantum cellular automata,” IEEE Trans. Nanotech-nol., vol. 3, no. 4, pp. 443–450, Dec. 2004.
[37] K. Kong, Y. Shang, and R. Lu, “An optimized majority logic synthesismethodology for quantum-dot cellular automata,” IEEE Trans. Nanotech-nol., vol. 9, no. 2, pp. 170–183, Mar. 2010.
Stefania Perri (M’00–SM’09) received the M.S. de-gree in computer science engineering from the Uni-versity of Calabria, Rende, Italy, in 1996, and thePh.D. degree in electronics engineering from the Uni-versity Mediterranea of Reggio Calabria, Reggio Cal-abria, Italy, in 2000.
In 1996, she joined as a Researcher Associate inthe Department of Electronics, Computer Sciencesand Systems, University of Calabria, where she iscurrently an Associate Professor of Electronics. In2002, she was appointed as an Assistant Professor of
Electronics with the Department of Electronics, Computer Science and Systems,University of Calabria. In the summer 2004, she was a Visiting Researcher in theDepartment of Electrical and Computer Engineering, University of Rochester,NY, Rochester, USA, where from 2005 she was appointed as Adjunct AssistantProfessor for four years. Her current research interests include QCA-based cir-cuits, high-performance arithmetic circuits, low-power design, VLSI circuits forimage processing and multimedia, reconfigurable computing, and VLSI design.She is coauthor of more than 100 technical papers and holds two patents in thesefields.
Pasquale Corsonello (M’97) was born in Cosenza,Italy, on May 4, 1964. He received the M.S. degree inelectronics engineering from the University of Naples“Federico II,” Naples, Italy, in 1988.
He joined the Institute of Research on ParallelComputers, National Council of Research of Italy,Naples, Italy, where he was involved on the designand modeling of electronic transducers for high pre-cision measurement, receiving a post-graduate two-year grant. In 1992, he joined the Department of Elec-tronics, Computer Science and Systems, University
of Calabria, Rende, Italy, as a Research Associate. In 1997, he was appointedas an Assistant Professor of Electronics with the Department of ElectronicsEngineering and Applied Mathematics, University of Reggio Calabria, ReggioCalabria, Italy, where he was also the Director of the Microelectronics Lab-oratory. In 2001, he was appointed as an Associate Professor of Electronicsand as the Chair of the Ph.D. Program in Electronics Engineering at the Uni-versity of Reggio Calabria. In the summer 2004, he was a Visiting Researcherwith the Department of Electrical and Computer Engineering of the Universityof Rochester, Rochester, NY, USA. In 2005, he was appointed as an AdjunctAssociate Professor with the same department. He is currently an AssociateProfessor of Electronics in the Department of Electronics, Computer Scienceand Systems, University of Calabria. He is an Associate Editor of the Journal ofLow Power Electronics and Applications. His current research interests includehigh-performance arithmetic circuits, low-power design, VLSI architecture forimage processing, QCA-based circuits, and reconfigurable systems. He has au-thored or coauthored over 120 technical papers and holds two patents in thesefields.
Dr. Corsonello a member of technical committees of several VLSI confer-ences and a peer reviewer for several VLSI journals. He is an Associate Editorof the IEEE TRANSACTIONS ON VLSI SYSTEMS.
Giuseppe Cocorullo (M’93) was born in Italy in1952. He received the Dr.Eng. degree in electronicfrom the University of Naples, Naples, Italy, in 1978.
From 1983 to 1992, he was with the National Re-search Council (IRECE Institute-Naples), where hewas in charge of the microelectronic lab. Winner ofa national competition in 1992, he was appointed anAssociate Professor of Electronics at the Universityof Calabria, Rende, Italy, where he became a FullProfessor of Electronics in 2001 and is currently incharge of the Nanoelectronics and Microsystems Lab.
His current research interests include silicon optoelectronics, solar cells, bio-electronics, and embedded systems.
