October 22, 2018 - Index of UT Dallas Centers · October 22, 2018 TEXAS ANALOG CENTER SYMPOSIUM...

October 22, 2018THE UNIVERSITY OF TEXAS AT DALLAS

October 22, 2018TEXAS ANALOG CENTERSY M P O S I U M

Symposium Chair: Professor Brian MaPoster Session Chair: Professor Bilal Akin

D O W N L O A D T H E S Y M P O S I U M A P PFor schedule, speaker bios, talk abstracts, news and other information.

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MORNING SESSION Davidson Auditorium, JSOM

LUNCH (NOON – 1 P.M.) Davidson-Gundy Alumni Center

AFTERNOON SESSION Davidson Auditorium, JSOM

7:30 a.m. Registration and Full Breakfast, Davidson Auditorium, JSOM

Welcome: Joseph J. Pancrazio | VICE PRESIDENT FOR RESEARCH, UT DALLASIntroduction: Brian Ma | DISTINGUISHED CHAIR AND PROFESSOR, UT DALLAS

8:20 a.m.

David Wentzloff | ASSOCIATE PROFESSOR, UNIVERSITY OF MICHIGAN8:35 a.m.

Keynote: Richard K. Templeton | CEO, TEXAS INSTRUMENTSIntroduction: Richard C. Benson | PRESIDENT, UT DALLAS

9:15 a.m.

Coffee Break10:20 a.m.

Panel: Impact of TxACEModerator: Jim Wieser | DIRECTOR OF STRATEGIC TECHNOLOGY AND UNIVERSITY RESEARCH, TEXAS INSTRUMENTS

10:30 a.m.

Student Poster Previews11:25 a.m.

Wrap-up and Move to LunchNoon

10th Year Anniversary Recognition10:05 a.m.

Chris Mangelsdorf | FELLOW, ANALOG DEVICES12:35 p.m.

Poster Session and Competition1:15 p.m.

Move to Davidson Auditorium2:15 p.m.

Ram Krishnamurthy | SENIOR RESEARCH DIRECTOR AND SENIOR PRINCIPAL ENGINEER, INTEL2:30 p.m.

George Villarreal | DEPUTY DIRECTOR, TRAFFIC SAFETY DIVISION, TXDOT3:15 p.m.

Panel: Future Research for TxACEModerator: Ken Hansen | PRESIDENT AND CEO, SRC

4:10 p.m.

Coffee Break4:00 p.m.

TxACE Overview: Ken O | TXACE DIRECTOR5:00 p.m.

Student Poster Awards and Closing Remarks5:20 p.m.



ERIK JONSSON SCHOOL OF ENGINEERING AND COMPUTER SCIENCETHE UNIVERSITY OF TEXAS AT DALLAS

Joseph J. PancrazioVice President for ResearchThe University of Texas at Dallas

Welcome

David WentzloffAssociate ProfessorUniversity of Michigan

VLSA (Very Large-Scale Analog):Cell-Based, Synthesized ADPLLsAbstract: Cell-based, synthesizable ADPLLs are recently gaining significant traction in the age of FinFETs. This is fueled by the exponentially increasing number of DRC rules, added restrictions on custom layout, and overall increase in design time for full-custom, analog designs. This talk focuses on different techniques for cell-based ADPLL designs that are amenable to using existing automatic place and route tools to automate their physical design, thereby significantly reducing design time.Bio: David D. Wentzloff has been with the University of Michigan since 2007, where he is currently an Associate Professor of Electrical Engineering and Computer Science. His research focuses on RF integrated circuits, with an emphasis on ultra-low power design. In 2012, he co-founded PsiKick, a fabless semiconductor company developing self-powered sensing solutions, where he is currently the co-CTO. He is the recipient of several awards, including a Joel and Ruth Spira Excellence in Teaching Award and an ISSCC Outstanding Forum Presenter Award.

Richard K. TempletonCEOTexas Instruments

KeynoteBio: Rich Templeton is chairman, president and chief executive officer of Texas Instruments. He became chairman of the board in April 2008, and president and chief executive officer in May 2004. He has served on the company's board of directors since July 2003.As CEO, Rich has successfully reshaped the company, focusing resources on growth opportunities in TI's core businesses of Analog and Embedded Processing. This strategy has made the company stronger, with better technological and product positions in both of its core businesses. Throughout this process, he has maintained the company's strategic investments in R&D and manufacturing, while expanding the size of the sales and applications engineering team to better serve TI customers. Rich joined the company in 1980 after earning a Bachelor of Science in Electrical Engineering from Union College in New York. He has been among the top-ranked CEOs in Institutional Investor’s Best Semiconductor CEOs in America for several years. In addition to his TI duties, Rich has focused much of his external energies on public issues and initiatives that advance the high-tech industry, technological innovation, and education – particularly STEM (science, technology, engineering, and math) education. Under his leadership, TI and the TI Foundation have invested more than $150 million over the last five years to strengthen global education programs, including K-12 STEM teaching and student achievement. The industry has taken note of Rich's commitment and passion in this area. In 2012, the Semiconductor Industry Association awarded him its highest honor, citing his service as a "vigorous advocate for STEM education and longtime champion of research and innovation." For a number of years he has personally led TI’s United Way campaign, resulting in tens of millions of dollars of donations to a variety of charitable organizations and served as chair of the community-wide campaign for United Way of Metropolitan Dallas in 2012 – 13 and again in 2018-19. Rich believes the health of communities and its corporations are intertwined, often noting that “Strong companies build strong communities, and strong communities build strong companies.”



8:20 a.m. 9:15 a.m.

8:35 a.m.

Bio: Joseph J. Pancrazio has undergraduate degree in electrical engineering and a PhD in Biomedical engineering from the University of Virginia. He was program director for the neural engineering and neural prosthesis program at the National Institute of Neurological Disorders and Stroke at the NIH. He was the founding chair of the Department of Bioengineering at George Mason University in Virginia. As a Professor of Bioengineering at UTD, he is an active researcher in neural engineering with support from the DoD and the NIH. After a 3 year period serving as Associate Provost at UTD, Pancrazio was recently selected as VP for Research.

Chris MangelsdorfFellowAnalog Devices

Perverse Trends in Analog Technology

Ram KrishnamurthySenior Research Director andSenior Principal EngineerIntel

High performance and energy efficient SoCdesign challenges and opportunities for thesub-10nm technology era:From AI to IoT platformsAbstract: This lecture presents some of the prominent barriers to designing high performance and energy-efficient microprocessors and digital systems-on-chip in the sub-10nm technology regime and outlines new paradigm shifts necessary in next-generation tera-scale multi-core microprocessors and systems-on-chip. Emerging trends in SoC design for Artificial Intelligence, Machine Learning, and IoT platforms will be discussed, and key challenges in sub-10nm design are outlined, including (i) device and on-chip interconnect technology scaling projections, (ii) performance, leakage and voltage scalability, (iii) special-purpose hardware accelerators and reconfigurable co-processors for compute-intensive signal processing algorithms, (iv) fine-grain power management with integrated voltage regulators, and (v) resilient circuit design to enable robust variation-tolerant operation. Special purpose hardware accelerators and data-path building blocks for enabling high GOPS/Watt on specialized DSP tasks such as machine learning, encryption, graphics and video/media processing are presented. Specific chip design examples and case studies supported by silicon measurements and trade-offs will be discussed. Emerging industry trends in machine learning, hybrid computing, and neuromorphic brain-inspired design will be outlined.Bio: Ram K. Krishnamurthy is Senior Research Director and Senior Principal Engineer at Intel Labs, Hillsboro, Oregon. He heads the high performance and low voltage circuits research group. He has been at Intel Corporation since 1997. Krishnamurthy has filed over 175 patents (121 issued), and has published 200 papers and 3 book chapters on high performance energy efficient circuits. He serves as chair of the Semiconductor Research Corporation (SRC) technical advisory board for circuits, has been a guest editor of IEEE Journal of Solid-State Circuits, associate editor of IEEE transactions on VLSI systems, and on the technical program committees of ISSCC, CICC, and SOCC conferences. He has received two Intel Achievement Awards for pioneering the first sparse-tree ALU technology and the first AES security accelerator on Intel products. He is a Fellow of the IEEE and distinguished lecturer of IEEE solid-state circuits society. Krishnamurthy received his BE in electrical engineering from National Institute of Technology in India (1993), MS in electrical and computer engineering from State University of New York (1994), and PhD in electrical and computer engineering from Carnegie Mellon University (1997). University of New York (1994), and PhD in electrical and computer engineering from Carnegie Mellon University (1997).



12:35 p.m. 2:30 p.m.

Abstract: With decades of heroic effort -demanding unprecedented cooperation across economic, social and national boundaries- the semiconductor industry has changed the course of human history and set civilization on a bold new path. Of course, analog circuit designers have done everything they could to prevent this. Through accident, laziness or peevish recalcitrance, the analog community has managed to contradict everything positive in the grand march of Moore's Law. Sure, analog people bask in the shared glory of semiconductor industry progress, but the truth is they'd still be using bipolar transistors and 30V supplies if it were up to them. Come, explore the bizarre world of analog and the strange beings which inhabit it. Marvel in its contradictions, its twisted logic and its unlikely folk heroes. Enjoy the tour, but don't ask why. Diagnosing the cause all this perversion is best left to clinical professionals.Bio: Chris Mangelsdorf received a B.S. in physics, magna cum laude, from Davidson College, Davidson, NC in 1977. In 1980 and 1984, he received the M.S. and Ph.D. degrees in electrical engineering at M.I.T. where he held the first Analog Devices Fellowship. He has been associated with Analog Devices since summer employment in 1980 and has been a Fellow of Analog Devices since 1998.From 1996 to 2013, Dr. Mangelsdorf worked in Tokyo, running the Analog Devices Tokyo Design Center and then adding responsibility for the Shanghai and Beijing Design Centers with the title of Asia Technical Director. In 2013, he moved to the Analog Devices San Diego office, where he is engaged in the development of high speed A/D converters.Dr. Mangelsdorf is a member of Phi Beta Kappa and Sigma Pi Sigma (physics), and has served on both the ISSCC Program Committee and the AdComm for the IEEE Solid-State Circuits Society. He holds 18 patents and has won the ISSCC Best Evening Session Award seven times.

George VillarrealDeputy Director, Traffic Safety DivisionTxDOT

Perverse Trends in Analog Technology



Kenneth OProfessor of Electrical Engineeringand Director of TxACE andTexas Instruments Distinguished ChairThe University of Texas at Dallas

TxACE OverviewBio: Kenneth O received his S.B, S.M, and Ph.D. degrees in Electrical Engineering and Computer Sci¬ence from the Massachusetts Institute of Technology, Cambridge, MA in 1984, 1984, and 1989, respectively. From 1989 to 1994, Dr. O worked at Analog Devices Inc. developing sub-micron CMOS processes for mixed signal applications, and high speed bipolar and BiCMOS processes. He has been a professor at the University of Florida, Gainesville from 1994 to 2009. He is currently the Director of Texas Analog Center of Excellence and TI Distinguished University Chair Professor of Analog Circuits and Systems at the University of Texas at Dallas. His research group is developing circuits and components required to implement analog and digital systems operating at frequencies up to 40THz using silicon IC technologies. Dr. O was the Meetings Committee of IEEE Solid-State Circuits Society from 2011 to 2016, and currently the Vice President of the Society. He has authored and co-authored ~260 journal and conference publications, as well as holding 12 patents. Dr. O has received the 2014 Semiconductor Research Association University Researcher Award. Prof. O is also an IEEE Fellow.

3:15 p.m. 5:00 p.m.

Abstract: As integrated circuits technology has evolved over the decades, creative transportation professionals have leveraged these advances to increase safety for the traveling public. Transportation engineers utilize integrated circuits technology in improved traffic control devices, innovative traffic management systems, and sophisticated safety programs. TxDOT’s George Villarreal shares examples of how professionals improve our transportation system with integrated circuits technology applications that prevent crashes, reduce injuries and save lives.Bio: A native of Bovina, Texas, George Villarreal graduated from the University of Texas at San Antonio in 2003 with a Bachelor of Science Degree in Civil Engineering. He received his license as a professional engineer in 2008. George began his career in 2003 as an engineering assistant in the TxDOT Lubbock District. He entered the TxDOT Young Engineers Rotation Program, which enabled him to gain experience in design, construction, maintenance, and traffic operations. In 2010, he was named the Lubbock District Traffic Engineer, where he was responsible for working on district projects in signals, speed zones, signing, TMUTCD compliance, and with cities and counties on safety engineering projects. In 2012, he began working as an adjunct professor at the Texas Tech Whitacre College of Engineering, where he taught Highway and Transportation Engineering.In 2014, George began working for a private engineering firm, where he continued to work in the traffic engineering field. While working in the private industry, he used his TxDOT experience to assist other state DOT’s on traffic operations and safety engineering.George was recently named the Deputy Director of the TxDOT Traffic Operations Division in October 2017. In his new role, he is responsible for overseeing all aspects of the Traffic Operations Division, including the state’s Traffic Management System, Speed Zoning, Crash Records and Data Analysis, and the Traffic Safety Program. These responsibilities include the development and administration of policies, programs, and operating strategies for TxDOT.George and his wife Ruby have five children, the four oldest are in college and their youngest daughter is in high school.



PA N E L SImpact of TxACE

10:30 a.m. 4:10 p.m.

Future Researchfor TxACE

Jim WieserDirector of Strategic Technology and University ResearchTexas Instruments

Yun ChiuProfessor, The University of Texas at DallasFounder, Formula Electronics

Tod DicksonResearch Staff MemberIBM T.J. Watson Research Center

David YehDirector, Analog/Mixed-Signal Circuits, Systems, and DevicesSemiconductor Research Corporation

Baher HarounSenior FellowTexas Instruments

Yorgos PalaskasPrincipal EngineerIntel Communications and Devices Group

Moderator:

Panelists:

Ken HansenPresident and CEOSemiconductor Research Corporation

Shiva GowniVP of R&DNXP

Ram KrishnamurthySenior Research Director and Senior Principal EngineerIntel

George VillarrealDeputy Director, Traffic Safety DivisionTxDOT

Gary XuSenior Director, ResearchSamsung Research America

Wai LeeCTO, Sensing ProductsTexas Instruments

Dan RadackAssistant DirectorIDA

Moderator:

Panelists:

TxACE Analog Symposium 2018

Poster Session Proceedings

October 22, 2018 The University of Texas at Dallas

i

LIST OF POSTER ABSTRACTS Poster #

Gate Driving Techniques And Circuits For Automotive-Use GaN Power Circuits D. Yan, D. Brian Ma ........................................................................................................................................ 1

Analyzing Dielectric Constant and Loss Tangent of Packaging Materials from 10 MHz to 67 GHz N. Mahjabeen, S. Priya, H. McIntyre, Y. Goel, R. Henderson ......................................................................... 2 450 × 580 µm2 Pixel Incorporating TX and Coherent RX in CMOS for Mm-Wave Active Imaging Using a Single Reflector W. Choi, P.R. Byreddy, Z. Chen, Z. Chen, A. J. Newman, K. K. O ................................................................. 3 Different Operating Conditions’ Effect on Dynamic On-Resistance in Enhancement-Mode GaN HEMTs F. Yang, C. Xu, B. Akin ................................................................................................................................... 4 Hardware Trojans in Wireless Networks K. S. Subramani, A. Antonopoulos, A. Nosratinia, Y. Makris .......................................................................... 5

A Low Phase Noise CMOS VCO Using Post-Fabrication Selection With A PLL Based On-Chip Phase Noise Measurement Capability P. Yelleswarapu, F. Jalalibidgoli, K. K. O ........................................................................................................ 6 Investigation of Room Temperature Ionic Liquid Interface towards Designing Robust and Repeatable Gas Sensing A. Tanak, B. Jagannath, A. Bhide, R. Willis, S. Prasad .................................................................................. 7

Magnetic Domain Wall Neuron with Lateral Inhibition N. Hassan, X. Hu, L. Jiang-Wei, W. H. Brigner, O. G. Akinola, F. Garcia-Sanchez, M. Pasquale, C. H. Bennett, J. A. C. Incorvia, J. S. Friedman ............................................................................................. 8 On-Chip Patch Antenna Techniques for Better Radiation Efficiency H. Bakshi, H. Sarinana, A. Blanchard ............................................................................................................. 9

On-Die Learning-Based Self-Test and Self-Calibration of Analog/RF ICs G. Volanis, Y. Lu, Y. Makris .......................................................................................................................... 10

ii

A 25MHz 4-Phase SAW Hysteretic DC-DC Converter with 1-Cycle APC Achieving 190ns Tsettle to 4A Load Transient and Above 80% Efficiency in 96.7% of the Power Range B. Lee, M. K. Song, A. Maity, D. Brian Ma .................................................................................................... 11

Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming M. Shihab, J. Tian, G. Reddy, C. Sechen, Y. Makris .................................................................................... 12 Light Generation in Junctions Fabricated in CMOS B. Pouya, X. Li, A. Gharajeh, A. Moreno, Q. Gu, K. K. O .............................................................................. 13

Hardware Dithering: A Run-Time Method for Trojan Neutralization in Wireless Cryptographic ICs C. Kapatsori, Y. Liu, A. Antonopoulos, Y. Makris .......................................................................................... 14 Degradation Assessment and Precursor Identification for SiC MOSFETs under High Temp Cycling E. Ugur, S. Pu, F. Yang, B. Akin ................................................................................................................... 15 Deep Learning Solutions for ADAS: From Algorithms to Real-World Driving Evaluations S. Jha, M. Marzban, N. Al-Dhahir, C. Busso ................................................................................................. 16 Enablement of Semiconductor Based-Electrochemical Gas Sensing On a TI Hardware Platform A. Bhide, B. Jagannath, A. Tanak, R. Willis, S. Prasad ................................................................................ 17 300-GHz MSK CMOS Transceiver for Communication over a Dielectric Waveguide I. Momson, S. Dong, Z. Chen, Q. Zhong and K. K. O ................................................................................... 18 A 135-GHz Stacked LC VCO with Transformer Feedback in 65-nm CMOS Z. Chen, K. K. O ............................................................................................................................................ 19 Investigation of Performance Degradation in Enhancement-Mode GaN HEMTs under Accelerated Aging C. Xu, E. Ugur, F. Yang, S. Pu, B. Akin ........................................................................................................ 20 Conservative Skyrmion Logic System M. Chauwin, X. Hu, F. Garcia-Sanchez, N. Betrabet, C. Moutafis, J. S. Friedman ....................................... 21

iii

Ultrafast Shifted-Core Coaxial Nano-Emitter X. Li, Q. Gu ................................................................................................................................................... 22 Dual-Band Millimeter-Wave Planar Antenna Designs in 65 nm CMOS J. Bright, N. M. Vijayakumar, R. Henderson.................................................................................................. 23 High-Speed Compact Power Supplies for Ultra-Low-Power Wireless Sensor Applications K. Wei, D. Brian Ma....................................................................................................................................... 24 Real-Time Machine Learning-Based Gesture Recognition on mmWave Radar J. Smith, B. Ramanidharan, S. Thiagarajan, M. Torlak, Y. Makris ................................................................ 25 OTA Input Offset Correction using Analog Floating Gates S. Nimmalapudi, U. Patel, H. Stiegler, K. Jarreau, A. Marshall ..................................................................... 26 Adaptive Miller Plateau Sensing Mechanism for Independent Control of di/dt and dv/dt Applied in GaN Buck DC-DC Converter Y. Chen, D. Brian Ma .................................................................................................................................... 27 Energy Storage Microdevice with Carbon Nanotube Sheet B. Dousti, Y. Choi, G. Lee ............................................................................................................................. 28 Reduction of Noise Figure of 300GHz CMOS Receivers T. Dinh, S. Lee, K. K. O ................................................................................................................................. 29 Electrochemical Interface Modulation for CO2 Monitoring Using Low-Powered TI Microcontroller B. Jagannath, A. Bhide, A. Tanak, R. Willis, S. Prasad ................................................................................ 30 High-Performance Oversampling ADC Design Leveraging ΔΣ-SAR Hybrid Architectures S. Li, N. Sun .................................................................................................................................................. 31 Near-Field Millimeter-Wave Imaging for Concealed Item Detection M. Yanik, M. Torlak ....................................................................................................................................... 32

iv

In-situ SiC-MOSFET Condition Monitoring Based on Switch Transient Changes Over Aging S. Pu, E. Ugur, B. Akin .................................................................................................................................. 33 Proof-Carrying Hardware Intellectual Property (PCHIP): Framework Automation and Enhancement M. M. Bidmeshki, Y. Makris ........................................................................................................................... 34 Reliability Study of E-Mode GaN HEMT Devices A. Mehta, S. Shichijo, M. Kim ........................................................................................................................ 35

1

Gate Driving Techniques and Circuits for Automotive-Use GaN Power Circuits

D. Yan, D. Brian Ma

Email: [email protected]

Abstract 1- The automotive electronics has placed growing demand on the reliability and performance of silicon-based power converters. GaN FET is becoming a promising technology alternative for next generation because of its higher electron mobility than traditional silicon devices. However, the lack of GaN-compatible high-speed, efficient gate driver has been a major impediment to take advantage of GaN FET-based power circuits. In GaN-FET power converters, the switching node voltage VSW can drop to as low as −3V based on reverse current during deadtime intervals because there is no parasitic diode in GaN FET. When the high-side power switch is turned off, VSW starts to fall because of continuous positive inductor current. There will be large negative spike of VSW and the BST rail voltage can be overcharged to destroy GaN FET. This deteriorates reliability due to GaN FET breakdown and damage on internal driver circuits. The passive Zener diode DZ can be used to clamp BST rail. However, the large current through DZ degrades the driving efficiency. The efficient high-speed level shifter with dynamic pulse current is designed to achieve sub nanosecond propagation delay for high switching frequency. The high reliable active bootstrap balancing (ABB) circuit is proposed to control BST rail voltage. It improves the reliability of GaN power switches and driving circuits.

2

Analyzing Dielectric Constant and Loss Tangent of Packaging Materials from 10 MHz to 67 GHz

N. Mahjabeen, S. Priya, H. McIntyre, Y. Goel, R. Henderson


Abstract 2- The accuracy of material properties in the microwave range is crucial for circuit and system design. One of the key requirements is to have reliable dielectric constant and loss tangent values over a wideband at high frequency. Many substrate manufacturers have provided accurate results typically using resonant methods that are narrowband and only up to 10 GHz (X-Band). Having correct material properties across frequency can provide designers with the proper tools to achieve single iteration success in the design cycle. This poster presents the recent results of extracting material properties of packaging substrates using a published reference plane invariant technique where the frequency range has been extended to 67 GHz. The substrates have been machined as toroid and inserted in air coaxial transmission lines to provide results from 0.01 to 67 GHz using a Keysight E8361C vector network analyzer. The mathematical model has been implemented in MATLAB and used to extract the dielectric constant and loss tangent of standard laminates including Rogers Corporation RT/Duroid® 5880 and FR-4. ANSYS HFSS has been used to verify the code by simulating the airline with the industry reported material properties.

3

450 × 580 µm2 Pixel Incorporating TX and Coherent RX in CMOS for Mm-Wave Active Imaging Using a

Single Reflector

W. Choi, P.R. Byreddy, Z. Chen, Z. Chen, A.J Newman and K.K. O


Abstract 3- Terahertz radar imaging provides the possibility of higher precision because of its wider bandwidth due to shorter wavelength. A transceiver pixel for active imaging incorporating a transmitter (TX) and a coherent receiver (RX) is demonstrated at 260GHz in 65-nm CMOS process. The pixel occupies an area of 450 × 580µm2, and is the first demonstration of a pixel incorporating a transmitter and a coherent receiver which are smaller than (λ/2)2. The pixel exhibits −21.3 dBm total radiated power and −79.5dBm sensitivity at a 1-kHz noise bandwidth. This sensitivity is about 10 dB better than state of the art pixel with only a coherent receiver. The pixel consumes 18.7 mW of DC power.

4

Different Operating Conditions’ Effect on Dynamic On-Resistance in Enhancement-Mode GaN HEMTs

F. Yang, C. Xu, B. Akin


Abstract 4- The dynamic on-resistance issue is problematic in existing GaN HEMTs as it increases the conduction loss of the converter in real operations. In this poster, the different operating conditions’ effect on the dynamic on-resistance is evaluated experimentally for a commercial enhancement-mode GaN HEMT. Specifically, a double-pulse-test setup with a fast dynamic on-resistance measurement circuit is designed, and the impact of dc-link voltage, load current and turn-on gate resistance on the dynamic on-resistance is assessed. From the experimental results, it is observed, for the first time, that the turn-on gate resistance can affect the dynamic on-resistance especially at the high current and high voltage region. At 400 V/ 25A, more than 27% increase of dynamic on-resistance is observed when the turn-on gate resistance changes from 0 Ω to 20 Ω. Meanwhile, different from the previous studies, it is observed that the dc-link and load current’s effect on the dynamic on-resistance relies on the operating conditions. Specifically, their impacts are more significant at the high current and high voltage regions. To find out the reason for these experimental results, a quantitative correspondence of the dynamic on-resistance and the energy used to generate hot electrons is established. It is concluded that the dynamic on-resistance’s dependency on turn-on gate resistance, dc-link voltage and load current can be explained by the variation of the hot electron generation during the hard-switching transient.

5

Hardware Trojans in Wireless Networks

K. S. Subramani, A. Antonopoulos, A. Nosratinia and Y. Makris


Abstract 5- The area of hardware security has received intense scrutiny in recent years due to outsourcing of semiconductor device manufacturing, use of third party Intellectual Properties (IPs) in the fabricated design, Electronic Design Automation (EDA) tools and software from different vendors, etc. Therefore, there is a general notion that the IC supply chain isn't as secure as it used to be. This problem is further aggravated by the fact that the cost of having a fully trusted supply chain is too expensive. As a result, government entities, the semiconductor industry and academic groups have spent a lot of time and effort to secure the IC supply chain. Over the past decade, the area of hardware security has seen a lot of research activity, mainly focusing on the digital domain, addressing the design and development of secure microprocessors. However, little has been done in the Analog/RF design space including wireless networks. Therefore, in this research work, security vulnerabilities in wireless networks are explored, covering a broad design space spanning from the baseband to the Analog/RF front-end of a wireless device. The proposed approach is to develop a metric to quantify the hardware Trojan threat in wireless devices. Next, the design space in a wireless device is explored to identify blocks that possess vulnerabilities that can be represented in terms of the defined metric. For each identified vulnerabilities, a theoretical analysis of the hardware Trojan threat is performed, followed by simulation and experimental evaluation of the Trojan's impact on a user communication link. Accordingly, Trojan-agnostic defense techniques are developed to prevent these classes of hardware Trojan attacks and their effectiveness is evaluated under practical operating conditions.

6

A Low Phase Noise CMOS VCO Using Post-Fabrication Selection With A PLL Based On-Chip

Phase Noise Measurement Capability

P. Yelleswarapu, F. Jalalibidgoli, Dr. Kenneth K. O


Abstract 6- The low frequency noise varies considerably from one minimum sized transistor to another because the number of defects in each transistor is different. We propose a new VCO topology which takes advantage of these minimum-sized low noise transistors through post-fabrication selection. Using this technique, A 4.3-GHz VCO using an array of cross-coupled minimum size NMOS transistor pairs for post fabrication selection is demonstrated in 65-nm CMOS. An algorithm based on Hamming distance using the phase noise measurements of ~1,500 array combinations was used to identify combinations that have record phase noise of -130dBc/Hz at 1-MHz offset from 4.3-GHz carrier. In order to make this topology more practical and reliable, a PLL based on-chip phase noise measurement system is also included.

7

Investigation of Room Temperature Ionic Liquid Interface towards Designing Robust and Repeatable

Gas Sensing

A. Tanak1, B. Jagannath1, A. Bhide1, R. Willis, S. Prasad


Abstract 7- Thriving impact of airborne pollutants on occupational health and public safety has boosted the need to design gas sensors, especially for CO2. The vision motivating the proposed research work is to develop a novel detection methodology to design CO2 sensing platform empowering characterization of the physical and chemical properties of Room Temperature Ionic liquid (RTIL). Room temperature ionic liquids (RTILs) have gained a lot of interest for gas sensing. Among the various RTILs, EMIM[TF2N], a fluorinated based ionic liquid is of significant interest due to its chemical properties and affinity to capture CO2. In this work, the docking mechanism of CO2 between the cationic and anionic moieties has been characterized using ATR-IR spectroscopy to provide feasibility as a useful sensing platform. CO2 demonstrates an affinity to the fluorinated anionic moiety, and the CO2 bonds representing binding. Wettability characteristics evaluated using contact angle study confirmed the feasibility of using EMIM[TF2N] on the sensing electrode. The COMSOL results display the effect of geometry and electrode design in validating the enhancement of the CO2 signal response. To test the effective design for automobile application, the effect of elevated temperature on the material interface was characterized using electrochemical impedance spectroscopy. The developed platform was tested for sensitivity and specificity to CO2. Receiver operating characteristic (ROC) analysis was used to determine CO2 sensing performance metrics. The sensing response was compared against non-specific nitrogen and oxygen. Area under the curve for ROC was obtained to be 0.61 with sensitivity and specificity of 66%.

8

Magnetic Domain Wall Neuron with Lateral Inhibition

N. Hassan, X. Hu, L. Jiang-Wei, W. H. Brigner, O. G. Akinola, F. Garcia-Sanchez, M. Pasquale, C. H. Bennett, J. A. C. Incorvia, and J. S. Friedman


Abstract 8- The development of an efficient neuromorphic computing system requires the use of nanodevices that intrinsically emulate the biological behavior of neurons and synapses. While numerous artificial synapses have been shown to store weights in a manner analogous to biological synapses, the challenge of developing an artificial neuron is impeded by the necessity to include leaking, integrating, firing, and lateral inhibition features. In particular, previous proposals for artificial neurons have required the use of external circuits to perform lateral inhibition, thereby decreasing the efficiency of the resulting neuromorphic computing system. This work therefore proposes a leaky integrate-and-fire neuron that intrinsically provides lateral inhibition, without requiring any additional circuitry. The proposed neuron is based on the previously proposed domain-wall magnetic tunnel junction devices, which have been proposed as artificial synapses and experimentally demonstrated for non-volatile logic. Single-neuron micromagnetic simulations are provided that demonstrate the ability of this neuron to implement the required leaking, integrating, and firing. These simulations are then extended to pairs of adjacent neurons to demonstrate, for the first time, lateral inhibition between neighboring artificial neurons. Finally, this intrinsic lateral inhibition is applied to a ten-neuron crossbar structure and trained to identify handwritten digits, and shown via direct largescale micromagnetic simulation for 100 digits to correctly identify the proper signal for 94% of the digits

9

On-Chip Patch Antenna Techniques for Better Radiation Efficiency

H. Bakshi, H. Sarinana, A. Blanchard


Abstract 9- The aim of this work is to design and integrate (on chip) a patch antenna using the 65 nm CMOS fabrication process for applications in near field communication. A 20% fractional bandwidth, centered at 350 GHz and radiation efficiency of 80% is desired. To meet these specifications, multiple approaches are being examined. A multi-layer Corporate-Feed Slotted Waveguide Array Antenna shows promising simulation results in terms of return loss, efficiency and bandwidth, however its fabrication needs Deep Reactive Ion Etching (DRIE), a special processing technique. Also, meeting the size constraints with this approach seems difficult. The fabrication of a patch antenna seems to be a better alternative in terms of size and on chip fabrication process, trading off efficiency and bandwidth if compared to a conventional rectangular patch. The 65 nm fabrication process satisfies the metal thickness (t << λ0) and the dielectric constant requirements (2.2 < Ɛr < 12) for the design of a λ/2 rectangular patch antenna. For better efficiency, larger bandwidth and lose coupling of fields to the ground plane (for better radiation into free space), a thicker substrate with low dielectric constant (Ɛr) should be used. To achieve this in the 65nm process, multiple substrate layers will need to be combined and used between the patch and ground plane, thereby giving an effective (low) dielectric constant (Ɛeff). A thicker substrate also increases the gain to some extent, but may lead to undesired effects like surface wave excitation which in turn decreases efficiency and perturb the radiation pattern. Thus the optimum dimension needs to be determined to achieve the best performance. To achieve wider bandwidth, modifying the straight edges of the patch into a pattern (say sine wave pattern or fractals) and incorporating slots, lenses and cavities into the design seems to be a promising approach concluded from simulation studies of a bow tie antenna and fractal type antennas. Thus the above approaches will be incorporated to meet the project goals.

10

On-Die Learning-Based Self-Test and Self-Calibration of Analog/RF ICs

G. Volanis, Y. Lu, Y. Makris


Abstract 10- This poster describes a hardware architecture for performing self-test and self-calibration of a Low-Noise Amplifier (LNA) through the use of on-die learning. More specifically, a trained on-chip analog neural network will periodically evaluate the responses of low-cost on-chip sensors to an on-chip generated stimulus, in order to assess whether the chip continues to meet its design specifications. Thereby, LNAs whose performances are no longer compliant due to aging or wear-&-tear will be detected. In addition, the analog neural network can also be trained to periodically assess the operational conditions of a tunable LNA and select appropriate settings for a set of on-chip knobs, in order to calibrate its performances. Since the proposed architecture can be used to adapt the operating conditions of the device in the field, it is efficient both for post-production and post-deployment testing/calibration. The effectiveness of this architecture is demonstrated by using silicon measurements of tunable LNAs chip alongside an analog neural network chip. The monolithic integration of the LNA with neural network is fabricated in GF’s 130nm RF CMOS process.

11

A 25MHz 4-Phase SAW Hysteretic DC-DC Converter with 1-Cycle APC Achieving 190ns Tsettle to 4A Load Transient and Above 80% Efficiency in 96.7% of the

Power Range

B. Lee, M. K. Song, A. Maity, D. Brian Ma


Abstract 11- Modern application processors (APs) have been continuously advancing with escalated performance and power consumption. APs repetitively flips its operation from sleep mode to active mode with drastic load current slew rate 1A/ns. Accordingly, the switch mode DC-DC converter, which is commonly used to power these APs, is expected to facilitate such a drastic load current change at a comparable slew rate to ensure a steady power supply. Here we present a 25 MHz, 4-phase, switch mode power converter. The converter employs an adaptive window hysteretic control to facilitate ultra-fast transient response and minimize output voltage VO undershoot and overshoot. Its inherent clock synchronization ability ensures current balancing among phase sub-converters. To maintain high efficiency over a wide load range without degrading transient speed, an 1-Cycle active phase count (APC) scheme is introduced. A design prototype was fabricated in a 0.35-m CMOS process with an active die of 1.88 mm2. It operates at 25 MHz with a well-regulated VO ranging from 0.3 V to 2.5 V. It achieves more than 80 % efficiency over 96.7 % of output power range, with a peak value of 88.1%. Simple circuit structure benefits a power density of 3.98 W/mm2. In response to 4-A load step-up/down, the converter achieves 103 mV/123 mV VO undershoot/overshoot with 1% settling time of 190 ns/237 ns, respectively.

12

Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming

M. Shihab, J. Tian, G. Reddy, C. Sechen, and Y. Makris


Abstract 12- Widespread adoption of the fabless business model and employment of third-party foundries have increased the exposure of sensitive designs to security threats such as intellectual property (IP) theft and integrated circuit (IC) counterfeiting. As a result, intense interest in various design obfuscation schemes for deterring reverse engineering and/or unauthorized reproduction of integrated circuits has surfaced.To this end, we present a novel mechanism for structurally obfuscating sensitive parts of a design through post-fabrication transistor-level programming (TRAP). We first discuss the unique advantages of our TRAP-based obfuscation methodology, followed by the implementation options and the customized CAD tool-flow for a seamless integration with ASIC designs. We then analyze the resilience of TRAP-obfuscated designs against brute-force and SAT-based attacks. Finally, we present the advantages of leveraging TRAP for design obfuscation, as compared to conventional FPGAs, in terms of area, latency and power. Our results indicate that TRAP-obfuscated designs can successfully deter both brute-force and oracle-guided SAT attacks with significantly reduced overhead.

13

Light Generation in Junctions Fabricated in CMOS

B. Pouya, X. Li, A. Gharajeh, A. Moreno, Q. Gu, K. K. O


Abstract 13- Light emission in Silicon integrated circuits has received little attention due to the fact that silicon is an indirect bandgap material. Nevertheless, light emission from p-n junctions fabricated in CMOS has previously been reported without the efficiency data critical for evaluating its applicability. To address this, the emission spectra of junctions built in 65nm CMOS technology without any process modification are being measured over a wide spectral range. P+-n-well and silicide to n-well junctions in breakdown and forward bias are being measured. Use of electroluminescence of hot electrons in reverse-biased Si junctions operating in avalanche regime as an optical source can exhibit time and temperature stability.

14

Hardware Dithering: A Run-Time Method for Trojan Neutralization in Wireless Cryptographic ICs

C. Kapatsori, Y. Liu, A. Antonopoulos and Yiorgos Makris


Abstract 14- We introduce a hardware dithering methodology for neutralizing Trojans in integrated circuits (ICs). The proposed approach seeks to make the operating point of an IC an unpredictable moving target during run time. Thereby, the ability of a Trojan to exploit the process variation margins, wherein hardware Trojans typically find breathing room to operate while remaining concealed, is significantly restricted. To demonstrate this hardware dithering concept, we leverage tuning knobs operating on the power and frequency characteristics of the transmission of a wireless cryptographic IC. These knobs are driven by a random number generator, thus forcing the circuit into a random walk in the space of its parametric performances while in normal operating mode. In essence, while the circuit remains within its operating specifications during this random walk, its exact operating point varies, thus muddying the waters for the adversary. Experimental results on the wireless cryptographic IC, which was designed and fabricated in a 0.35μmCMOS technology, corroborate that hardware dithering imposes a significant and unpredictably dispersed bit error rate to the adversary, thereby impeding hardware Trojan operation.

15

Degradation Assessment and Precursor Identification for SiC MOSFETs under High Temp Cycling

E. Ugur, S. Pu, F. Yang, B. Akin


Abstract 15- SiC power MOSFETs are promising alternatives to Si devices in high-voltage, high-frequency, and high-temperature applications. The rapid and widespread deployment of SiC devices raises long term reliability concerns, particularly for mission and safety critical systems due to limited field data and potential uncertainties. Therefore, it is essential to investigate progressive degradations and parameter shifts in SiC devices to develop system integrated degradation monitoring tools for self-monitoring converters which can recognize failure precursors at the earliest stage and prevent catastrophic failures. This study presents a comprehensive long-term reliability analysis of commercially available SiC MOSFETs under high temperature operation and high temperature swing, degradation related key precursors and possible causes behind them. For this purpose, discrete SiC devices are power cycled and all datasheet parameters are recorded at certain intervals with the aid of the curve tracer. Variation of electrical parameters throughout the tests is presented in order to assess their correlation with the aging/degradation state of the switch. Among them, gate oxide charge trapping related threshold voltage drift and corresponding on-state resistance variation has been observed for all samples. For some samples bond wire heel cracking is found to be the root cause of sudden on-state resistance and body diode voltage increases. The discussions regarding aging precursors are supported by failure analysis obtained through the decapsulation.

16

Deep Learning Solutions for ADAS: From Algorithms to Real-World Driving Evaluations

S. Jha, M. Marzban, N. Al-Dhahir, C. Busso


Abstract 16- Designing intelligent algorithms to study the behavior of drivers and detect when they are distracted can be helpful in designing smart applications for Advanced Driver Assistance Systems (ADAS). Intelligent safety systems should monitor the situational awareness of the driver, providing valuable feedback by either taking control of the vehicle (in autonomous cars) or providing warning to the driver. Towards this purpose, we focus on predicting the visual attention of the driver by studying their head movement. To obtain continuous head pose of the driver in naturalistic settings, we have designed a helmet structure called FiCap with fiducial markers. This device provides ground truth data for continuous head movement without occluding the face by using one additional RGB camera placed behind the driver. Using this helmet, we plan to benchmark our recordings with RGB as well as depth cameras. We have experimented with various machine learning algorithms to predict the visual attention of the driver from the recorded head pose. The relation between gaze and head pose is one to many due to eye movements. We formulate the problem with probabilistic models that predicts a distribution representing the driver’s visual attention from the head pose, instead of a single estimate of the gaze. This problem can be modelled as a regression problem relying on frameworks such as Gaussian Process Regression (GPR) and Mixture Density Networks (MDN). The output of these approaches is a Gaussian distribution representing the gaze direction predicted from the driver’s head pose. We also explored a solution for this problem using a classification-based formulation. The gaze direction is discretized to obtain a probability for each interval in the horizontal and vertical angles of the driver’s gaze. Our novel formulation performs consecutive up sampling and 2D convolution to create a heat map of the probability distribution of the gaze, starting from the position and orientation of the driver’s head.

17

Enablement of Semiconductor Based-Electrochemical Gas Sensing On a TI Hardware Platform

A. Bhide, B. Jagannath, A. Tanak, R. Willis, S. Prasad


Abstract 17- In this work, we present a robust electrochemical sensor integrated on a TI hardware platform in a portable format for the detection of CO2 using a novel sensing material – Room temperature ionic liquid (RTIL). RTIL's are solvent free electrolytes consisting of organic cation and inorganic anion pairs with tunable chemical and physical properties for sensing. The innovation of this study is to develop an RTIL- electrode sensing element interfaced with the TI platform to detect the levels of ambient CO2 and breathe CO2 in real- time. The developed portable prototype is a promising strategy towards using RTIL’s as a novel sensing element for achieving low power environmental sensors. Prior to integration, the performance metrics of the RTIL in detecting CO2 such as lowest limit of detection, dynamic range, sensitivity, repeatability, and specificity in the presence of humidity and other ambient gases were established. The components of the RTIL form an ordered structure of alternating cation and anion stacks when it comes in contact on a charged electrode surface. We have leveraged the multiple electrochemical double layer (EDL) stack formation of the RTIL moieties in detecting CO2.We have leveraged the multiple electrochemical double layer (EDL) stack formation of the RTIL moieties in detecting CO2. CO2 molecules dock within the interstitial spaces formed between the RTIL moieties on the application of a bias potential. AC perturbation of the system causes charge redistribution in the EDL as a result of CO2 docking which is studied through an AC based technique- Electrochemical impedance spectroscopy (EIS). The frequency response of the EDL quantifies the changes occurring at the RTIL- electrode interface as the environment changes around them. These changes are represented by impedance from which capacitances can be extracted. The sensitivity of the RTIL in detecting CO2 was established by investigating the role of electrochemical bias voltages (ECW) on the performance of the RTIL. The RTIL was exposed to varying concentrations of CO2 at ambient and elevated temperature and humidity conditions to understand the CO2 detection range of the RTIL. The adsorption- desorption dynamics of CO2 over repeated cycles was investigated to understand the repeatability and reversibility in CO2 sensing mechanism over repeated cycles at ambient temperature and low humidity conditions. The cross sensitivity of the RTILs towards other interferent gases present in ambient environment was investigated to establish specificity of CO2 detection.

18

300-GHz MSK CMOS Transceiver for Communication over a Dielectric Waveguide

I. Momson, S. Dong, Z. Chen, Q. Zhong and K. K. O


Abstract 18- The advances of high frequency performance silicon integrated circuits technology have enabled generation of carrier signals in millimeter and submillimeter wave frequencies where narrow fractional bandwidths of carriers translate to large absolute bandwidths. These high frequency carriers and the associated wide bandwidths can make possible high data rate communications approaching that of optical systems by the implementation of a waveguide based communication link operating at submillimeter waves which only requires electronic components fabricated in conventional silicon technologies, thus bypassing the photonic component integration and coupling/packaging challenges of optical systems. In this work, we are developing a transceiver operating at 300-GHz capable of supporting up to 30-Gbps communications over a 1-m long dielectric waveguide which can provide one of the communication channels in a link employing frequency division multiple access (FDMA).

19

A 135-GHz Stacked LC VCO with Transformer Feedback in 65-nm CMOS

Z. Chen and K. K. O


Abstract 19- Millimeter wave applications have vastly increased including radar systems, imaging/spectroscopy and high data rate communication links. In all such transceivers voltage-controlled-oscillators(VCO) are one of the most critical building blocks. However, on-chip signal generation at frequencies close to fmax of today’s CMOs technology can be a difficult task due to the fact that the transconductance of a transistor gm degrades significantly as the frequency increases towards fmax. Moreover, varactor Q become dominant of the tank Q degradation. In this work, a 135-GHz stacked oscillator with transformer feedback is designed in 65-nm CMOS. Negative source resistance degeneration technique is used for boosting the effective transconductance of a cross-coupled pair by stacking another pair onto the existing one. And transformer feedback is also applied for larger oscillation swing and lower phase noise.

20

Investigation of Performance Degradation in Enhancement-Mode GaN HEMTs under Accelerated

Aging

C. Xu, E. Ugur, F. Yang, S. Pu, B. Akin


Abstract 20- In this poster, the performance degradation of GaN HEMFs under accelerated aging is presented in detail. A real-time degradation monitoring tool is essential to prevent costly shutdowns and minimize safety concerns. Specifically, a DC power cycling setup is first designed which operates within the safe operating area (SOA) of the device to mimic the field operation and accelerate the aging process. Using the curve tracer, the parameter shifts are periodically monitored at certain aging cycles. From the experimental results, it is observed that both of them show a gradual increase of the on-state resistance, which is a good candidate for failure precursor. Meanwhile, the threshold voltage of enhancement mode (E-mode) GaN are gradually increasing over the aging cycles and a variation in the transfer characteristics is observed. The failure mechanism of both types of GaN devices are made and a detailed theoretical analysis is provided to explain this parameter shift in experiments.

21

Conservative Skyrmion Logic System

M. Chauwin, X. Hu, F. Garcia-Sanchez, N. Betrabet, C. Moutafis, J. S. Friedman


Abstract 21- Conservative logic provides a vision for computing with no energy dissipation, in which information carriers are conserved as they flow through a logic circuit. Logic functions are executed through dissipation-free elastic interactions among these information carriers that conserve momentum and energy. However, the large dimensions of information carriers in previous realizations of conservative logic detract from the system efficiency, and a nanoscale conservative logic system remains elusive. Here we propose a non-volatile conservative logic system in which the information carriers are magnetic skyrmions, topologically-stable magnetic whirls . These quasiparticles interact with one another as they propagate through ferromagnetic nanowires via the spin-Hall and skyrmion-Hall effects to enable AND/OR and INV/COPY logic functions. These logic gates can be directly cascaded in large-scale systems that perform complex logic functions, with signal integrity provided by clocked synchronization structures. The feasibility of the proposed system is demonstrated through micromagnetic simulations of various logic gates including a cascaded one-bit full adder, and fabrication guidelines are enumerated. As skyrmions can be transported in a pipelined and non-volatile manner at room temperature without the motion of any physical particles, this conservative skyrmion logic paradigm has the potential to deliver scalable high-speed low-power computing.

22

Ultrafast Shifted-Core Coaxial Nano-Emitter

X. Li, Q. Gu


Abstract 22- The size mismatch between electronic and photonic devices is one of the major issues holding back the development of a fully integrated optical communication system based on electronic-photonic integration. For high speed chip-scale optical communication, the major obstacle is to integrate directly modulated light sources on-chip. In this study, we numerically demonstrate a III-V single mode shifted-core coaxial nano-emitter with an effective mode volume as small as 0.0078×(λ0/na)3, featuring a Purcell factor larger than 390, and modulation bandwidth up to 60 GHz. Along with its small footprint, high power efficiency and large modulation bandwidth, this nano-emitter will be a good candidate of light source for high speed on-chip optical communication.

23

Dual-Band Millimeter-Wave Planar Antenna Designs

in 65 nm CMOS

J. Bright, N. M. Vijayakumar, R. Henderson


Abstract 23- This research presents the performance of a dual-band dipole antenna fabricated in 65 nm CMOS technology for use in a high data rate wireline communication system. Two separate dipoles are designed at 180 GHz and 315 GHz to excite a dielectric waveguide that supports RF signals operating from 140 to 360 GHz. Due to the limited bandwidth of traditional dipoles, two separate designs are needed. Using the area of the 180 GHz dipole, spur lines are introduced to create the resonant mode of the 315 GHz design. This design uses a simplified feed to reduce radiation losses and to have a compact form factor. The design is implemented as a crossed dipole for future use to support vertical and horizontal polarization in the waveguides for multiple transceiver circuits. In addition, the simulation results of a complementary crossed-slot antenna operating in the same frequency range will be presented.

24

High-Speed Compact Power Supplies for Ultra-Low-Power Wireless Sensor Applications

K. Wei, D. Brian Ma


Abstract 24- This project is to deliver an efficient and compact switched-capacitor (SC) voltage regulator for ultra-low-power wireless sensors to adapt to wide input range, high-speed operation and high efficiency. A simple unit SC cell with all-NMOS implementation is presented to increase the number of the achieveable conversion ratios as well as retain low complexity. By implementing three unit cells, 5 step-down (<2:1) and 6 step-up (>1:2) conversion ratios are achieved to handle the input voltage varying from 0.4V to 5.5V. Moreover, to achieve fast wake-up/shut-down operation, the designed SC voltage regulator employs hysteretic control scheme to improve load transient response and minimize output voltage variations. Auto reset operation eliminates any need of the external clock in the proposed hysteretic controller. Load-dependent biasing technique is utilized in this project to adaptively adjust the static current and enhance efficiency at light load. 2-phase interleaving scheme is implemented to reduce output switching noise. With the input voltage range from 0.5V to 5.5V, the output voltage varies from 0.9V to 3.3V for the maximum load current of 10mA. The simulated peak efficiency is above 80%.

25

Real-Time Machine Learning-Based Gesture Recognition on mmWave Radar

J. Smith, B. Ramanidharan, S. Thiagarajan, M. Torlak, Y. Makris

Email: [email protected], [email protected]

Abstract 25- Of many applications of the mmWave radar technology, object and image recognition forms an important aspect which utilizes the capabilities of the radar imaging techniques. Among these capabilities, depth information, the ability to recognize objects without direct line of sight, and the possibility to scan objects through multiple opaque surfaces makes mmWave radar imaging more beneficial and diverse in application. Our objective is to leverage Texas Instrument's mmWave radar in recognizing various hand gestures and providing a real-time platform for gesture recognition. Towards this end, information on various gestures obtained from the frequency response of the 77-81 GHz range mmWave radar was used to train a machine learning-based classifier model for gesture recognition. Machine learning models are extremely adept at analyzing large data spaces and identifying correlation among various features which can be exploited to achieve gesture identification. Apart from machine learning models, multiple feature space reduction and optimization techniques like Singular value decomposition (SVD) and Principle component analysis (PCA) were explored in reducing computation complexity and in improving the accuracy of our models thereby improving their robustness. Machine learning models including Support vector machines (SVM), Decision trees, Random forests and Neural networks were trained and gesture identification with acceptable classification accuracy was achieved. Using MATLAB-based gesture interface, a real-time platform was setup for on-the-fly gesture recognition.

26

OTA Input Offset Correction using Analog Floating Gates

S. Nimmalapudi, U. Patel, H. Stiegler, K. Jarreau, A. Marshall


Abstract 26- Consideration of random device mismatch is an important factor in the design of high-performance analog circuits. Floating gate transistors have long been used for digital non-volatile memory applications (such as flash memory), but a variant to this technology using an “analog floating gate” allows for higher precision programming. Analog floating gate devices can address mismatch observed in small geometry analog circuits. Enabling smaller devices to be used allows lower operating currents and higher frequencies. This property is exploited here to compensate for input mismatch and device parameter variations in an Operational Transconductance Amplifier.

27

Adaptive Miller Plateau Sensing Mechanism for Independent Control of di/dt and dv/dt Applied in GaN

Buck DC-DC Converter

Y. Chen, D. Brian Ma


Abstract 27- A novel adaptive Miller Plateau sensing (AMPS) method is presented here, which is critical to realize the independent control of di/dt and dv/dt. It is applied to GaN Buck DC-DC converter to achieve the balance performance of low EMI noise and high power efficiency. By sensing the switching node voltage during the current freewheeling period, the Miller Plateau voltage (VMP) can be tracked dynamically. Two error terms are designed to compensate the difference between the actual VMP and emulated one. The proposed technique eliminates the issues of the large delay time and low accuracy which inherently present in the conventional sensing methods.

28

Energy Storage Microdevice with Carbon Nanotube Sheet

B. Dousti, Y. Choi, G. Lee


Abstract 28- Recent progress in MEMS devices, portable electronics, artificial electronic skins and wearable technology demands for lighter and more efficient miniaturized energy storage devices with higher energy delivery. Batteries fall short in long-term cycling, owing to the slow rate of redox reaction happening in bulk. Another state-of-the-art power units which have captured many attention recently are electrochemical supercapacitors. They provide higher power density and longer life cycle compared to batteries and higher energy density in comparison to dielectric capacitors. New class of microsupercapacitor with in-plane design has emerged for on-chip integration where bulky sandwich design indicates many shortcomings. Here, we leverage novel structure of carbon nanotube sheet to make a microsupercapacitor with higher performance than its counterparts. Results demonstrate a successful fabrication of a microsupercapacitor with a high specific capacitance of 0.8 mF/cm2 which is much higher than so-far reported double layer supercapacitors. CNT sheet offers long-term stability and highly mesoporous and aligned structure that provides a conductive pathway for electron transport for faster rate capability. Further improvement of performance is achievable via doping, surface treatment and metal oxide integration.

29

Reduction of Noise Figure of 300-GHz CMOS Receiver

T. Dinh, S. Lee, K. K. O


Abstract 29- This work aims to reduce the noise figure of 300GHz CMOS receivers for high bandwidth wireless communication to below 10dB. The receiver consists of a mixer that first downconverts the received signal to baseband, which is subsequently fed into a low noise amplifier (LNA) with a bandwidth of 5GHz. This work is investigating approaches to reduce the noise figure of down conversion mixer by optimizing the performance of anti-parallel diode pairs used to form a 2nd subharmonic mixer as well as investigating approaches to realize a mixer using the fundamental local oscillator. This effort is also investigating thermal noise cancellation in the LNA to reduce the noise figure of wide bandwidth LNA and thus that of the system.

30

Electrochemical Interface Modulation for CO2 Monitoring Using Low-Powered TI Microcontroller

B. Jagannath, A. Bhide, A. Tanak, R. Willis, S. Prasad


Abstract 30- This work demonstrates a low power portable CO2 monitor integrated on a semiconductor chip. The portable CO2 monitor leverages an electrolyte called room temperature ionic liquid (RTIL) to capture CO2. The developed CO2 sensor is integrated with Texas Instruments MSP430 microcontroller. Chronoamperometry was used to measure the capacitive current response for determining CO2 concentrations. A simple RC circuit with a series voltage divider was used for signal conditioning of the measured chronoamperometry signal, due the inherent amplified signal by the RTIL. The developed device using MSP430 demonstrated a wide dynamic range of 400- 15000 ppm. Furthermore, enhanced dynamic range and repeatability of the developed CO2 monitor was achieved compared to the lab-standard CO2 sensing device. In order to achieve enhanced signal response on the portable form-factor, the suitable operating voltage was optimized by operating RTIL at various voltage bias (1.6V, 2.3V and 2.8V) within the electrochemical window. The ability of the RTIL to reliably detect CO2 at various environmental conditions was evaluated at varying temperature and humidity. Furthermore, the cross-reactive results with N2 and O2 demonstrated that specific signal response to CO2. Cycling studies for adsorption and desorption of CO2 was performed to determine the repeatability of CO2 signal response.

31

High-Performance Oversampling ADC Design Leveraging ΔΣ-SAR Hybrid Architectures

S.Li and N. Sun


Abstract 31- The boom of Internet of Things (IoT) is driving the world into a ubiquitous sensing environment with an emphasis on edge computing. This regime brings stringent requirements for both high resolution and low power to its ADCs, as to satisfy the need for digitizing diverse high-dynamic-range sensor outputs under a tight power budget. Oversampling ADCs attract growing significance in the IoT era in light of their high-resolution capability. Nevertheless, with tighter constrains from power reduction and technology scaling, they also suffer greater challenges under the classic analog-intensive power-hungry design approaches. It is therefore in demand of new design solutions that emphasize “more digital, less analog”, as to leverage CMOS scaling to advance the power efficiency instead of being limited by them. This research explores an intriguing direction for low-power scaling-friendly oversampling ADC design focusing on the noise-shaping SAR, which hybridizes ΔΣ modulation inside the efficient SAR ADC to unveil many new possibilities for power reduction. A thorough study of existing designs is conducted to identify the key challenges and bottlenecks on performance improvement. To address them, we presents a new noise-shaping SAR design leveraging the error-feedback structure. This design highlights the co-realization of optimized noise transfer function, reconfigurability and background calibration using fully dynamic circuits with minimum modification to a standard SAR. Silicon prototypes are fabricated and measured, with comprehensive results demonstrating improvements over state-of-the-arts.

32

Near-Field Millimeter-Wave Imaging for Concealed Item Detection

M. Yanik, M. Torlak


Abstract 32- Recent progress in complementary metal-oxide semiconductor (CMOS) based frequency-modulated continuous wave (FMCW) millimeter-wave (mmWave) radars have made it possible to design low-cost and low-power mmWave imagers. As a result, there is a strong desire to exploit the progress in mmWave sensors in wide range of imaging applications including medical, automotive, and security. In this poster, we present a low-cost high-resolution mmWave imager that combines commercially available 77 GHz system-on-chip radar sensors and synthetic aperture radar (SAR) signal processing techniques for concealed item detection. To create a synthetic aperture over the target scene, the imager is built with two-axis motorized rail system which can synthesize a large aperture in both the azimuth and elevation. Signal processing techniques for near-field image formation are introduced. Our prototype system is described in detail along with various concealed item images. The experimental results confirm that our low-cost system design has a great potential for high-resolution imaging tasks in security applications.

33

In-situ SiC-MOSFET Condition Monitoring based on Switching Transient Changes over Aging

S. Pu, E. Ugur, B. Akin


Abstract 33- This work presents a SiC MOSFET health condition monitoring method based on the switching transient. Specifically, the device’s turn-on time is used as the aging precursor, and a picosecond resolution detection circuit is developed to detect the variations of the turn-on time. Such device monitoring approach benefits long term operation reliability of SiC based digitally controlled power systems. For this purpose, power cycles with constant junction temperature swing are applied on sample devices to accelerate their thermally triggered degradation. Over the aging process, automated curve tracer is used to take devices’ parametric measurement after every certain periods. Meanwhile, double pulse tester is used to evaluate devices’ switching transient changes throughout aging. Based on these results, both analytical discussion and experimental waveform imply device turn-on time a viable aging precursor at system start-ups. According to such degradation signature, high resolution capture module of system microcontroller is employed to measure the turn-on time length with auxiliary detection circuit. For experimental verification, aging detection is conducted on a buck converter and experimental results reveal that proposed in situ condition monitoring method is capable for SiC MOSFET state of health monitoring with 300 picosecond measurement precision.

34

Proof-Carrying Hardware Intellectual Property (PCHIP): Framework Automation and Enhancement

M. M. Bidmeshki, Y. Makris


Abstract 34- Proof carrying hardware intellectual property (PCHIP) introduces a new framework in which a hardware intellectual property (IP) is accompanied by formal proofs of certain security-related properties, ensuring that the acquired IP is trustworthy and free from hardware Trojans. PCHIP framework adds extra burdensome tasks in the hardware IP development process, hindering its wide acceptance by the hardware design community. In this poster, we present our efforts toward automating PCHIP, in order to simplify the adoption of PCHIP by hardware IP developers and consumers and, thereby, increase hardware IP trustworthiness. Additionally, we present tools and libraries that we developed for the PCHIP automation, namely VeriCoq and VeriCoq-IFT, and we demonstrate our efforts in enhancing the PCHIP framework with more capabilities including information flow tracking (IFT) in analog, digital and mixed-signal designs.

35

Reliability Study of E-Mode GaN HEMT Devices

A. Mehta, S. Shichijo, M. Kim


Abstract 35- The purpose of this study is to precisely investigate the failure mode and mechanism of E-Mode (Enhancement-Mode) p-GaN HEMT devices. Though commercially available, the exact mode of gate failure for p-GaN based devices is still obscured. An attempt has been made to characterize AlGaN/GaN layered devices for Time Dependent Dielectric Breakdown (TDDB) at various stressing voltages near breakdown voltage. The normal gate breakdown voltage for these devices is around 8 volts. Devices showed a unusual behavior of oscillation. The devices were stressed at 7 and 7.5 gate voltages. It was found that the device stressed on 7 V did not breakdown even after 18 hours while device stressed at 7.5 volts broke-down in about 30 minutes. This proves high dependence of device life on stressing gate voltages going near the breakdown values. Careful study of this lifetime dependence and the damage induced with the stressing can yield a concept for defining the failure mechanism. Furthermore, the damage is most likely to be around the gate/GaN interface. Also, High Resolution Transmission Electron Microscope imaging is suggested to identify the damage and changes taking place at Nano level.

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October 22, 2018 - Index of UT Dallas Centers · October 22, 2018 TEXAS ANALOG CENTER SYMPOSIUM...

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