Shanghai ChipRF Microelectronics Co., Ltd. • Phone 86-21-3390-7096 • Fax 86-21-33907096 • [email protected]•http:// www.chiprf.com 23-12-0001C • ChipRF Proprietary and Confidential • Product Information and Specification Subject to Change • October 2011 1 IP Product Brief PLL15G V0.0 P P r r o o d d u u c c t t B B r r i i e e f f Of P P h h a a s s e e L L o o c c k k e e d d L L o o o o p p o o f f 1 1 5 5 G G H H z z Prepared By: Chiprf Document Version: Rev 0.0 Last Updated On: May 22, 2012
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IP Product Brief PLL15G V0.0
Table of Contents
1. Abstract of 15GHz PLL .............................................................................. 4
1.1. General Description ............................................................................................ 4 1.2. Main Features ...................................................................................................... 4 1.3. Application .......................................................................................................... 5
2. Architecture of 15GHz SDPLL ................................................................... 6
3. Close Loop Frequency Response of 15GHz PLL ....................................... 7
4. Close Loop Transient Response (Time Domain) of PLL ............................ 8
5.1. Phase Noise of Reference clock in Loop ............................................................. 9 5.2. Phase Noise of PFD/CP in Loop ....................................................................... 10 5.3. Phase Noise of R2&R3 in Loop ........................................................................ 10 5.4. Phase Noise of VCO in Loop ............................................................................ 11 5.5. Phase Noise of Sigma Delta in Loop ................................................................. 12 5.6. Phase Noise of the Full Loop ............................................................................ 13
23-12-0001C • ChipRF Proprietary and Confidential • Product Information and Specification Subject to Change • October 2011 4
IP Product Brief PLL15G V0.0
1. Abstract of 15GHz PLL 1.1. General Description
The PLL_15G_LC_90nm is an IP cell that performs RF frequency synthesis for a variety of fixed ground applications.
The small die size and low external component count of this IBM 90 nm design meets the highly competitive cost and size requirements for building successful fixed ground products while delivering high performance at low current.
The cell supports both an external reference oscillator and external XTAL with load capacitors and works with an integrated Phase Detector /Charge Pump, VCO, Divider and patented Delta‐Sigma Modulator providing world class phase noise performance.
Additional features include Power Down and a standard I2C serial interface for functional control.
The circuit can be modified for other frequency ranges and phase noise contours can be tailored to address specific requirements.
Patented unique auto temperature compensation techniques greatly improve the system reliability and stability during environment variation
1.2. Main Features
LC VCO with 6.5GHz to 8GHz
PLL with I,Q differential output 13.75GHz to 15.5GHz using Freq. Doubler
10MHz or other input clock and support both external reference oscillator and XTAL
Support both fractional‐N and Integer‐N modes
Fully integrated RF VCO
Low in band phase noise < ‐105dBc/Hz at typical case
Low our of band phase noise <‐151dBc/Hz @10MHz offset when typical case
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IP Product Brief PLL15G V0.0
2. Close Loop Frequency Response of 15GHz PLL The 15GHz PLL archi. is listed in figure1, the reference clock frequency is 10MHz, the BW of PLL is 50KHz, the close loop response is as figure 2.
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IP Product Brief PLL15G V0.0
Figure 3 Close Loop Time Domain Transient Response As the loop is locking on 7.5GHz (The doubler output will be IQ 15GHz ), the locking time is about 50us in system analysis.
4. Phase Noise Analysis of 15GHz PLL （10MHz Ref Clock） The Phase Noise of each block and total can be illustrated as below section.
3. Close Loop Transient Response (Time Domain) of PLL
R2 noise at VCO output without loop responseR2 noise at VCO output with loop responseR3 noise at VCO output without loop responseR3 noise at VCO output with loop response
R2 noise at VCO output without loop responseR2 noise at VCO output with loop responseR3 noise at VCO output without loop responseR3 noise at VCO output with loop response
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IP Product Brief PLL15G V0.0
The Phase Noise of 7.5GHz PLL Loop is listed below (Unit dBc/Hz):
As well known, the Phase Noise after Doubler will be 6dB worse, so the final phase noise output for 15GHz PLL when 10MHz reference clock is listed in table 1.
Table 1: Phase Noise Result when 10MHz ref clock Freq. offset Phase Noise Spec. Comments
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IP Product Brief PLL15G V0.0
5. Suggestion From the simulation for this 15GHz PLL, it can be seen that the phase noise is very tough in 10KHz ~100KHz, the main reason is too large multiplier ratio from 10MHz to 7.5GHz or 15GHz. If possible, one solution is increasing the reference clock frequency such as 50MHz, the phase noise of total loop can be optimized to figure 10.
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IP Product Brief PLL15G V0.0
Figure 9: Total PLL phase noise when 50MHz reference clock So the final phase noise output for 15GHz PLL when the reference clock is increased to 50MHz is listed in table 2.
