I ~DiSTRIBUTI0i .. !

* MASSACHUSETTS INSTITUTE OF TECHNOLOGY VLSI PUBLICATIONS

COMPUTER-AIDED FABRICATION SYSTEM IMPLEMENTATION

I Final Technical Report for the period April 1, 1985 to December 31, 1988

I Massachusetts Institute of TechnologyCambridge, Massachusetts 02139

IPrincipal Investigators: Paul Penfield, Jr. (617) 253-2506Dimitri A. Antoniadis (617) 253-4693Stanley B. Gershwin (617) 253-2149Emanuel M. Sachs (617) 253-5831Stephen D. Senturia (617) 253-6869Donald E. Troxel (617) 253-2570

I T' C

This research was sponsored by Defense Advanced Research Projects Agency (DoD),monitored by Clifford Lau through the Office of Naval Research under ARPA Order No.5339, Contract No. N00014-85-K-02 13.

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3 i. Introduction

The Massachusetts Institute of Technology is pleased to submit this final report for contract N00014-85-K-0213, awarded by the Information Science Technology Office of the Defense Advanced Research ProjectsAgency, as monitored by the Office of Naval Research. The contract, and this report, cover the period betweenApril 1, 1985 and December 31, 1988.

j The major objective of this contract was to develop a computer system to aid the fabrication of VLSIintegrated circuits. Particular attention was paid to use of university and industry standards in the system, andan open architecture. Many of the ideas behind such a system were articulated by an inter-university group inan unpublished memo which subsequently was issued as an MIT VLSI memo: P. Penfield, Jr., S. B. Gershwin,D. A. Hodges, C. M. Osburn, J. Reynolds, J. Schott, A. J. Steckl, and D. E. Troxel, "Requirements forComputer-Aided Fabrication," MIT VLSI Memo No. 84-200, January 17, 1984.

I Other objectives of this contract were to extend the system architecture to encompass mechanicalproperties of integrated circuits, particularly as these may affect reliability, and to incorporate models for VLSIfabrication equipment. - - " "

The principal investigator was Professor Paul Penfield, Jr. Work was performed in the following fiveareas, under the direction of the individuals indicated:3 " CAF System Structure (Professor Donald E. Troxel)

" Modular Process (Professor Dimitri A. Antoniadis)* Scheduling (Dr. Stanley B. Gershwin)

Equipment Modeling (Professor Emanuel M. Sachs)* Mechanical Property TCAD (Professor Stephen D. Senturia)

The remainder of this report discusses progress made in each of these aieas. For further information,readers are referred to the publications listed in the final section.

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II. CA' System Structure

The olj,.ctivc of this task, the largest one in this contract, was to design, develop, and implement a CAF Isytmand deploy it in various MIT fabrication facilities. The system was named CAFE (Computer Aided

Fabrication Environment). It was designed to support more than one facility, and indeed data from threeseparate facilities was put into the system. The facility that relies most heavily on this work in its daily operationis the Integrated Circuit Laboratory (ICL). 3

In this activity, the most difficuit challenges were (1) the design and implementation of a data model thatwas independent of particular data base managers and presented a constant interface to application programs;and (2) the design of a process flow representation, that is, a language in which to express the fabrication 1sequence. These two tasks formed the basis of two doctoral theses. A challenge of a different kind was toimplement and maintain a hardware and software system for routine daily use. Without such a system, ofcourse, none of the research under this contract could proceed, yet this activity required more developmentthan research, and staff members were employed to carry it out. Several bachelors and masters theses werebased on portions of this work

The progress of this activity is chronicled below by quoting from the semiannual reports prepared for Ieach DARPA VLSI Contractor's Meeting, held each spring and fall.

Fall 1985 1We have implemented a preliminary version of a CAF system for use in our fabrication facility. The

architecture and capabilities of this system, named CAFE, Computer-Aided Fabrication Environment, weredefined during summer 1985, and the system was ready for brave users (who don't mind a few bugs) onSeptember 1, 1985. 3

The desired ultimate set of capabilities was described over a year ago by a multi-university group.During the summer a selection was made of features to be implemented first. The features with the highestperceived immediate value were not those of ultimate scientific and engineering interest, so much aF those thatenabled the new facility to start off immediately without paper. This was deemed important in setting people'sattitudes toward contamination right from the beginning. The specific features selected for the initialimplementation were: 3

User ListMachine listUser Qualification TableMessage-of-the-dayPersonal Laboratory NotebookMachine Operating InstructionsActivity Log

The hardware features deemed most urgent (aside from a central computer to run the system) wereterminals in key technicians' and engineers' offices, a terminal in the gowning room, and terminals in the clean Iroom.

The approach taken in this first implementation is to do as much as possible by using UNIX shell scripts,and other standard UNIX features. The user list was implemented by expanding the Unix password file. Each imachine is a directory in the data area, and therefore the machine list is merely a directory listing. Themessage-of-the-day is the standard UNIX facility. The laboratory notebooks were implemented by a rclafivcsimple shell wH"t which ", rely apperds tcraiinal input to a file. The data structures are all file-based. Noattempt was made to use a relational data base at this early stage.

At this time CAFE is being taught to the first group of users. It appears adequate to support thepaperless feature of the lab, but is still very crude.

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3 Spring 1986

Prior to the beginning of this reporting period, an initial, rudimentary CAF system was designed and* implemented. This included a personal notebook and data structures for the upcoming fabrication equipment

installation. This was implemented on a borrowed VAX 11/750 and some of the engineering staff started touse the lab notebook and editor. RS232 cables to the offices and labs were installed and some were checkedand connected to terminal concentrator ports. Three concentrators were assembled, connected to an MITEthernet, and were operational. The VAX 11/785 hardware was installed.

Since then, we have completed the computer hardware installation, evaluated and purchased terminalsfor both users and for use in the clean rooms, installed Unix version 4.3BSD, integrated local networkingsoftware, adapted mail software to our local needs, ported several applications programs to our CAF computer,instituted a weekly back-up procedure, substantially improved our terminal concentrators, created userdocumentation, interfaced to the MIT physical plant computer which monitors a large number of sensing pointsin our facility, initiated some student projects, initiated plans for including the teaching laboratories in ourdeveloping CAF system, acquired both documentation and software for the present Berkeley CAF system,initiated acquisition of additional main memory and disk storage, and expanded our user base to include3 virtually all of the faculty, students, and technical staff associated with our fabrication facility.

Our present computer hardware consists of a VAX 11/785 with 8 Mbytes of main memory, two 450Mbyte disks, GCR tape, 1600-cpi tape, laser printer, four phone lines and modems, and an Ethernet port to theIMIT network. Additionally there are seven 11/73-based terminal concentrators, each of which has 32 RS232ports. RS232 cables have been installed throughout our building, and numerous user terminals and PCs havebeen connected.

We have completed an extensive evaluation of terminals for use in the clean rooms, and by the technicalstaff and other CAF users. The information gleaned during our selection process has been communicated toother building occupants for their consideration. We chose Ergo 301 terminals as they had the bestcompromise considering cost, video quality, compatibility with existing software, and the fact that they do nothave fans, which allows their use in the clean room areas.

We installed the latest version of UNIX, Berkeley 4.3BSD, and have integrated local networkingsoftware and have adapted the mail software to enable local as well as remote communications. Our officialhost name is CAF.MIT.EDU; locally the computer is known simply as CAF.

I Several large applications programs have been successfully ported to run on CAF, Jluc r-g MAGICand PISCES. The success in porting these programs has resulted in greater use of the caf s., so much thatjwe will soon need increased primary memory and user disk space.

A back-up regimen has been initiated with full dumps taken every month and incremental dumps everyweek. This is intended primarily as protection against catastrophic disk failure.

Experiments with our terminal concentrators revealed service deficiencies when all ports were active.The cause was traced to inadequate use of the available buffer memory by the SWITCH software. This hasnow be, ,orr-'ted and satisfactory performance is achieved with 32 active lines per concentrator. We arereasonably confident that we could implement 48 lines per concentrator but are not sure that satisfactoryresponse times would be preserved if all 48 lines were active at once. We have more physical memory than cannow be used, probably enough to service twice the number of lines per concentrator. Ho,*.ver, it is doubtfulthat the rather substantial software rewrite required to use this memory is worth the effort.

We have automated thL, " ."',:r', for ippving fnr and approving new computer accounts. Aprogram named "open" has been written which enables prospective users to make requests for accounts andprovide the required information. Mail is sent to an "approver" after an account has been requested and newaccounts, including appropriate initialization filcs and directories, are automatically created after approval.

3 We have also been active in the generation of documentation for CAF users. User documentation nowcovers the use of terminal concentrators, obtaining accounts, obtaining documentation, using UNIX andI

Page 4 1EMACS, using Kermit with IBM PCs, and using the nroff text formatter with the -me macro package. Manualentries for the Cshell with command completion and Mail utility have also been made available for distribution.We have initiated a project to define laser printer hardware and software to provide both typesetting and hardcopy of arbitrary graphics.

We have interfaced to the MIT physical plant computer which monitors a large number of sensing pointssuch as resistance of DI water, etc., in our facility. We capture all alarms printed and have provided amechanism for remote query of the status of the monitored points. Our facilities personnel can now interrogatethe monitoring computer from either office or home and efficiently direct corrective action.

We have initiated a plan to expand the availability of the CAF system to the integrated-circuit teachinglaboratory. This will provide us with another active test bed for the CAF system, and will also allowindoctrination of entering graduate students (our present practice is to require new students to complete anintensive, short version of the undergraduate teaching laboratory subject). 3

We have advertised to our students several projects concerned with integrating measuring instrumentsinto the CAF system. One student has started work on a project relating to a CV measuring instrument.Another project has been defined concerning software for a scanning thermometer intended for use inmonitoring photolithography process parameters.

We have acquired both documentation and software for the present Berkeley CAF system. We are inthe process of installing a test version of this software and will study the integration of this software into oursystem or the integration of our system into the Berkeley software.

We now have. a ,ubstantial number of CAF users. The system response time remains quite good, but wehave had to make plans to augment primary memory and available disk space. Our primary future activity is tofurther the development of the CAF applications software and its use in the installation and operation ofequipment to be installed. 3Fall 1986

The memory on the computer CAF.MIT.EDU has been upgraded from 8 Mbytes to 16 Mbytes. Thiswas required as a number of users were starting to run large simulation and analysis programs resulting inexcessive paging activity. 3

A floating point accelerator was installed. Originally we had not intended that this computer be used forintensive computations but, instead, our plan was to farm out these computations to other processing engines.In deference to our users we installed a floating point accelerator to maximize the performance of the Icomputer.

We have substantially expanded our available disk space both to serve the needs of existing users and toprovide room for the enhancement of our caf software system by the use of a relational data base.

A second laser printer has been acquired. This laser printer has a Postscript interface and software hasbeen installed that allows Unix troff and plot output to be printed on this laser printer.

An additional terminal concentrator was installed in another building to service student offices.

All of our terminal concentrators have been upgraded to handle 48 lines each. We now have enoughport. for all existing czblths and aiso for the ones required for our new p!an.ncd crargcd terminal -o,m.

The Dektak profilometer has been connected together with software for transmitting screen plots to thecaf computer. Software has also been developed for printing these screen plots on either a laser printer or aterminal (graphics or ASCII). n

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The Nanospcc has been interfaced to the caf computer and initial software developed to receive the dataoutput and control the Nanospec. More work needs to be done in order to discard extraneous data.

The 11/23 computer included in the furnace controller has been interfaced to the caf computer.Software has been provided to allow recipe development from terminals logged into the caf computer.

Prior to the existence of any caf effort, a large number of monitoring points such as fans, alarms, DIwater resistance, etc. were implemented by connection to a computer operated by MIT Physical Plant. Thiscomputer was then accessed by a dedicated terminal and it also had a hard copy printer on which alarms wereprinted. Both the dedicated terminal lines and the printer line have been connected to the caf computer.Software has been developed which logs all alarms and also keeps a list of currently active alarms. As this datacan accumulate without bound, we have initiated an automatic purging of the historical log entries that aremore than 30 days old. These capabilities are actively used by lab personnel.

We have decided to use INGRES as a relational data base. We have initiated an active project to definea schema and implement it using "university" INGRES. We have investigated acquisition of a commercialversion of INGRES but have held off because MIT is in the process of negotiating a campus wide license and

* this should reduce the acquisition cost.

We have begun to look at desirable languages in which to denote process flow specifications. Since suchdescriptions need to be able to be both executed and analyzed, it is inappropriate to consider flows as either100% procedures or 100% data. We have begun to think of a LISP-based notation. We believe that such alanguage is now critical since it lies at the heart of almost all the functions that the CAF system is to perform.We believe that the language should firmly support, if not be designed explicitly around, the two-stage generic

I process-step model we have reported on earlier.

Spring 1987

Because of our success in getting faculty, staff, and students to use our computing facilities, and becauseof the increased use of our CAF system in actually operating the IC Laboratory, our VAX 785(CAF.MIT.EDU) is heavily overloaded. We must augment our facilities. We evaluated several possibilitiesand have initiated the purchase of two Sun Microsystems 3/280 computers. One of these will be used for theactual running of the CAF system CAFE for the IC Laboratory and the other will be reserved for developmentof CAF system software. We also have ordered RTI INGRES for use on the Sun computers. Delivery of thisequipment is expected during the first half of 1987.

We have made substantial progress in the development of a data model and schema. Our dataarchitecture being developed is similar to the Multibase system developed at CCA. This provides a uniformquery interface to data residing in multiple autonomous, heterogeneous data bases. Our current data base isdistributed across two relational systems, university INGRES and PRELUDE and a hierarchical file system.PRELUDE is a fast, lightweight UNIX-style data manager. Our system is very modular and, thus far, it hasbeen easy to incorporate new DBMSs into the system as well as move data from one data manager to another.

ty Our data model is the functional model with support of extended data types including various temporaltypes as well as inexact, interval, and null values. The schema captures several important aspects of plant andprocess management: fabrication facilities and equipment, users, equipment reservations, lots, lot tracking,wafers, process flow descriptions, WIP tracking, and lab activity information.

We have developed a generalized forms based user interface program, called FABFORM. This singleprogram, when called with a parameter file, produces a terminal display and allows a user to move from field tofield and enter data. The t'pe and content of the screen display is specified by an ASCI! file which is referencedby data included in the parameter file. The form may have arbitrary length and the user can scroll up or down.At present, user interface commands arc much like EMACS commands. When the user exits, or saves the data,3 an updated parameter file is written.

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Using FABFORM, we have implemented the electronic equivalent of a signup sheet for reserving;fabrication equipment in our lab. This program is in daily use and stores the signup data in our data base.Several improvements for the next version of this reservation program have been initiated.

We are developing a process flow language. This language has a lisp-like form, although this need not 3be apparent to process design engineers. We continue to embrace the concept of the two-stage generic processmodel with corresponding expression of goals, wafer environment, and machine settings. Adequate machinemodels, yet to be developed, will provide a transformation from machine settings to wafer environments.Process models similarly provide the transformation from the wafer environment to the wafer-state goals.

The meaning of our process flow language is to be provided by several interpreters: fabrication,simulation, production scheduling, and 'walk-through." We have completed an initial version of this "walk-through" interpreter. It interprets the process flow language and enables a process developer or potential user

to secv, hat will happen when the process is executed. It will, we think, prove useful in the design of a process,the communication of the process to others, and its approval by laboratory management. Substantial work has ibeen accomplished towards a fabrication interpreter.

We have defined and begun work on a browser which al!ows a user to review what actually happened inthe fabrication of a lot of wafers. We have vet to resolve how to browse through the future, especially when thefuture path is uncertain due to possible branches.

Fall 1987 1During the past year we have defined and installed both a hardware configuration and an initial CAF

software system architecture. Central to the hardware architecture is the use of computer networking, both toprovide integration of functions performed on different computers and to provide access to these computersfrom the integrated circuit processing facility and also from the users' offices. 3

The primary computer used for the actual operation of the CAF system within the integrated circuitprocessing facility consists solely of a Sun 3/280 processor with disk and network interface. Our processingfacilities and offices are equipped with ASCII terminals which are interfaced to diskless terminal concentrators, Iwhich in turn provide network connections to any available computer. There are eight terminal concentrators,each of which has provision for up to forty-eight 9600-baud RS232 ports. These concentrators also provide forcommunication paths and connection of some of the actual integrated circuit processing equipment. 3

Another Sun 3/280 is used as a development test bed for enhancements, tests, and debugging fixes. Thisinsulates the users of the primary CAF system from the introduction of untested software, and it also helps toprovide faster response time for the present users in that they do not have to share their CPU resources with Ithe developers of new software. The second Sun 3/280 allows the developers of new software in particular toexpcriment with data base application programs without corrupting the actual data base used for ongoingprocessing of integrated circuits.

A third computer system consisting of a DEC 785 serves as a common meeting ground for the somewhatwider community of people concerned with integrated circuit design and manufacture. This computer providesthe bulk of the text processing, printing, mail, simulation, and other facilities which are related to, but not Idirectly concerned with, the actual operations in the integrated circuit processing facility. The 785 also providesa connection to an MIT Physical Plant computer and maintains an active alarm log for the building containingthe integrated circuits fabrication facility.

Our initial CAFE (Computer Aided Fabrication Environment) software system was based upon theBerkeley Roving Shell with a file based data storage system. Our present CAFE system is based on theBerkeley system with an enhanced user interface menu and uses a commercial version of RTI INGRES database system. Users log into this facility in the gowning room and then attach to the CAFE system at a terminalclose by the equipment to be operated. 3

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We have provided an ever growing number of functions to be accessed via the CAFE system. We haveimplemented a personal laboratory notebook facility. We have developed a standard forms based user interfacemechanism which is used for most of our applications functions. Our implementation of an equipmentreservation mechanism has been enthusiastically accepted by our laboratory users. We have implemented anumber of transaction type applications such as defining of facilities and machines, starting lots, and reportswhich show machine status and the status of lots being fabricated. Just recently we have implemented an initial

version of a process flow language and have provided two interpreters and a browser for this language. We are3 now trying to get people to use this process flow language on a routine basis.

During this period we installed two Sun 3/280 computers. One of these is used for the actual running ofthe CAF system for the fabrication laboratory, and the other is reserved for development of CAF systemsoftware. We have installed RTI INGRES on the Sun computers.

We have initiated the purchase of extra memory for the two Suns and also for the 785. We plan toaugment each of these three CPUs to a total of 32 megabytes. Our 785 is often used by upwards of 30 users andextra memory is desirable in order to minimize page-outs. Both data base programs and lisp programs used for

our process flow languages consume large amounts of memory and our plan is that the increased memory onthe Suns will accommodate a sufficient number of lab users.

We have successfully ported all of the CAF software to the two Sun computers. While this entailed asignificant amount of work, the programs are now much more portable than before. In addition we have portedall data residing in the previous multi-database system to RTI INGRES running on the Suns. We have almostcompleted the task of converting the last vestiges of our file based data storage scheme to RTI INGRES.

The performance increase, in speed, that resulted from this conversion to the Suns and RTI INGRES isapproximately ten times. This is much appreciated by the lab users.

As all of our terminal concentrators use chaos protocols, it was necessary to install chaos networksupport in the Suns. We also had to make several increases in system resources in order to accommodate thelarger number of lab users.

3 Previously we developed a generalized forms based user interface program, FABFORM. This singleprogram, when called with a parameter file, produces a terminal display and allows a user to move from field tofield and enter data. The type and content of the screen display is specified by an ASCII file which is referercedby data included in the parameter file. The form may have arbitrary length and the user can scroll up or down.At present, user interface commands are much like EMACS commands. When the user exits, or saves the data,an updated parameter file is written.

3 Using FABFORM, we have implemented a new version of the equipment reservations program whichenables users to sign up for multiple machines at once. Users specify a list of machines that they will use intheir next processing operation and access the data base for the current status of reservations. A lockingmechanism has been devised so that multiple users cannot make conflicting entries. However differect usersmay make reservations for different machines or different days. This program is in daily use and stores the signup data in our data base.

I We have also used FABFORM to implement a new multi-level menu system for the CAFE shell. Werequired a multi-level menu as we are accumulating quite a number of functions and were running out of spaceon the two level menu system that we ported from Berkeley. By using FABFORM we were able to implementthis change fairly smoothly and also provide users with a more uniform interface.

We have continued to make substantial progress in the development of a data model and schema. Oursystem architecture is based on the Multibase system developed at CCA. This provides a uniform queryinterface to data residing in multiple autonomous, heterogeneous data bases.

Our data model is the functional model with support of extended data types including various temporaltypes as well is inexact, interval, and null values. The schema captures several importatit aspects of plant and

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Page 8 Uprocess management: fabrication facilities and equipment, users, equipment reservations, lots, lot tracking,wafers, process flow descriptions, WIP tracking, and lab activity information.

Pririarily because of the interface layer between the application programs and the data base accesses wewere able to changc the data base out from under the application programs without requiring changes in thoseapplications when we ported the data base to the Suns and RTI INGRES.

We have continued to progress on the development of a process flow language (PFL). The creation of aPFL and associated interpreters is the key to our approach for generating actual fabrication instructions and forcollecting the data resulting from actual fabrication steps. The interpreters provide the actual meaning of theprocess flows expressed in the flow language. Our PFL development is based on a two-stage process stepmodel which relates the goal of a change in wafer state first to the physical treatment parameters and finally tothe actual machine settings used to process the wafers.

We have completed initial versions of walk through and fabrication interpreters and a browser all ofwhich utilize our generalized forms based user interface program, FABFORM. The walk-through interpreterenables a process developer or potential user to see what will happen when the process is executed. Thefabrication interpreter is similar, but in addition, allows for convenient entry of data as the wafers are actuallyprocessed. We have also completed an initial version of a past history browser which allows a user to reviewwhat actually happened in the fabrication of a lot of wafers. We have not yet been successful in getting theseinterpreters into daily use in the lab. 3Spring 1988

This quarter, wc made substantial progress in the development of our data model and schema. OurGestalt system architecture provides a uniform query interface to data residing in multiple autonomous,heterogeneous data bases. Our functional data model provides support of extended data types including varioustemporal types as well as inexact, interval, and null values. We expanded our schema to represent more aspectsof plant and process management: fabrication facilities and equipment, users, equipment reservations, lots, lottracking, wafers, process flow descriptions, WIP tracking, and lab activity information.

The Gestalt data base interface routines were rewritten, expanded, and a new release (complete with anupdated documentation paper) was made.

We have started a project to provide a schema display to let laboratory managers and users give moremeaningful feedback about our schema.

We have completed a "data base walker" (DBW) program which enables application programmers (and Iothers) to find their way around the existing data base. It displays an existing entity and allows the user toexplore related entities. For example, one can display a facility and see that it has a list of machines. Fromthere one can display a particular machine and see its attributes, etc. I

We have written and released a new change status data entry program which is based on FABFORM.

We have developed, but not yet released, a generalized graphing program. This too, is based on IFABFORM and allows the user to conveniently specify captions, axes labels, etc. This information, along with adata file is then provided to the locally developed "giraphe" programs which then produce the output graphs ina form suitable for terminal display or laser printer.

We have written and arc now testing a generalized equipment uptimc report generator. This is designedto provide the data to the graphing programs described above. It can produce graphs of uptime for a selectedmachine for a selected period of time or, alternatively, a summary of the relevant log entries relating to machinestatus changes. I

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A new program which interfaces with the Nanospec has been developed. It operates the Nanospec viathe computer, initiates film-thickness measurements, and places the results in the appropriate fieldautomatically, thereby reducing the operator interaction required.

We have initiated a project to interface the Gyrex mask maker directly to the computer. Presently userswrite data to magnetic tape and carry these tapes to the Gyrex.

We have initiated and made substantial progress on the development of a "hands off terminal." Wechose a commercially available TI speech recognition module which plugs into an IBM PC/XT. Software hasbeen developed to interface the TI PC software to control a FABFORM interface. As this speech recognitionmodule is speaker dependent, the software automatically loads the data base appropriate to the login name.Several of us have "trained" the recognition software and the results are quite interesting. It remains to be seenif this recognition scheme is powerful enough to actually be useful in the fabrication laboratory, at least with thishardware.

We have continued to progress on the development of a process flow language (PFL). The creation of aPFL and associated interpreters is the key to our approach for generating actual fabrication instructions and forcollecting the data resulting from actual fabrication steps. The interpreters provide the actual meaning of theprocess flows expressed in the flow language.

Our previous PFL development was based on only the machine setting view, in order to get somethingworking as soon as possible. We now have a version of our PFL which is based on the two-stage process-stepmodel which relates the goal of a change in wafer state first to the physical treatment parameters and finally tothe actual machine settings used to process the wafers. We have recoded the CMOS baseline process in thisnew version and, in addition, have encoded a furnace monitor process which process is routinely used everyweek.

Besides a fabrication interpreter for this new version of the PFL, we have the rudiments of a simulationinterpreter.

We have come to realize that we must provide for operation of partial flows. At least one impediment tothe use of our PFL is that users change their minds about the process specification as they do the actualfabrication. By concatenating the processing history of fabrication with a number of partial flows we at leastwill have a trace which accurately reflects what happened.

i We have made substantial progress on an expert PFL editor. This editor uses FABFORM as the userinterface. Ideally one starts with an existing process flow, encoded in our lisp-like PFL syntax, which issomewhat similar to the desired process flow. The editor then displays this existing process flow with a formsba-d presentation and allows the user to modify the flow. The editor then produces the new flow encoded inPFL without the user even being aware of the lisp nature of the PFL. The editor supports the three viewsrequired by the two-stage generic process model and, in addition, allows any number of hierarchical levels of

i process flow definition.

3 Fall 1988

We made substantial progress in the development of programs relating to our data model and schema.Our Gestalt system architecture provides a uniform query interface to data residing in multiple autonomous,heterogeneous data bases. The Gestalt data base interface routines were expanded to include Lisp interfaceroutines in addition to C interface routines by Ken lshii.

Mike Ruf has completed his S.M. thesis proposal, "Management of IC Manufacturing Data," August 18,1988. Mike worked on our CAFE project this past spring and is now at TI on his VI-A internship companyassignment. His work is being done at TI. This thesis is an example of how our CAFE system data basephilosophy is influencing related work at TI. A comprehensive set of data base tools, DBTOOLS, weregcncrated by Ruf. These include:

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Page 10 U" dbinspcct - a "data base walker" program which enables application programmers (and others) to find their

way ai ound the existing data base. It displays an existing entity and allows the user to explore relatedentities. For example, one can display a facility and see that it has a list of machines. From there one candisplaN a particular machine and see its attributes, etc.

" dbcreate - enable the creation of entities without writing a special application program." dbquery - implement data base queries.

" dbmutate - enable changes to be made to existing entities." dhchoose - select entities from the data base. U

An S.B. thesis, "Schema Viewer: A Graphical Representation to Portray the Database Schema of theMIT CAFE System," was completed by Nazhin S. Zarghamee in May, 1988. This software provides a schemadisplay so as to allow lab managers and users to provide more meaningful feedback as to the appropriatenessand utility of our schema.

A number of application programs pertaining to status and log reports were written or modified by D. E.Troxel. These included change-status which is used for entering data relating to status changes, describe-machine to display current status, new-machine to enter a new machine into the data base, fornat-equipment toreport the status of all equipment in a facility, up which is a generalized status and log report generator, and dbtwhich was used to transfer file based data to the data base. The up program can produce graphs of uptime for aselected ma-hine for a selected period of time or, a!ternatively, a summary of the relevant log entries relating tomachine status changes. The graphs can be output on a terminal or laser printer via giraphe3 which was writtenby Duane Boning and Bob Harris.

A new program, operate-machine, was written by Mike Mcllrath. This is initially used to make logentries when a machine is operated. It also provides a base for the creation of machine specific data entry andwill be expanded substantially in the near future. In addition to being available from the CAFE menu, thisprogram or procedure will be called by the fabrication interpreter in order to actually effect the machineoperations. The operate-machine program is being expanded to create WIP entities when the program is exitedwithout the finish time being specified. When this is accomplished several programs (up, change-status, anddescribe-machine) will have to be modified to include reports on active WIPs.

The next stage in the development of operate-machine is to make it specific to the actual machine beingoperated. This requires generation of opdesc entities which embody the description of the parameters ormachine settings and the measurements or data which are to be collected.

A new program which interfaces with the Nanospec film thickness instrument has been developed. In iaddition to operating the Nanospec via the computer, it now initiates measurements and places the resultingthickness measurement in the appropriate field automatically, thereby reducing the operator interactionrequired to capture the measurement data for data base storage.

A program written by Peter Monta provides for an alternative direct interface between the Gyrex maskmaker and a computer as opposed to requiring users to write data to magnetic tape and transport these tapes to Ithe Gyrex.

We have developed and demonstrated a "hands off terminal." We chose a commercially available TIspeech recognition card which plugs into an IBM PC/XT. Software has been developed by Peter Monta tointerface the TI PC software to control a FABFORM interface. As this speech recognition module is speakerdependent, the software automatically loads the data base appropriate to the login name. Several of us have"trained" the recognition software and the results are quite interesting. This "hands off terminal" is now ready nto be installed as the terminal next to the Nanospec in the fabrication laboratory.

We have continued the development of a process flow language (PFI.). The creation of a PFL andassociated interpreters is the key to our approach for generating actual fabrication instructions and for Icollecting the data resulting from actual fabrication steps. The interpreters provide the actual meaning of theproccss flows expressed in the flow language.

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Our previous PFL development was based on only the machine setting view in order to get somethingworking as so)n as possible. We now have a version of our PFL which is based on the two-stage process stepmodel which relates the goal of a change in wafer state first to the physical treatment parameters and finally tothe actual machine settings used to process the wafers. We have recoded the CMOS baseline process in thisnew version and, in addition, have encoded a furnace monitor process which is routinely used every week.

We have made substantial progress on an expert PFL editor. An expert PFL editor has been completedby Rajeev Jayavant as his S.M. Thesis, "An Intelligent Process Flow Language Editor." This editor usesFABFORM as the user interface. Ideally one starts with an existing process flow, encoded in our lisp likesyntax, which is somewhat similar to the desired process flow. The editor then displays this existing processflow with a forms based presentation and allows the user to modify the flow. The editor then produces the newflow encoded in our lisp like PFL without the user even being aware of the lisp nature of the PFL. The editorsupports the three views required by the two-stage generic process model and, in addition, allows any number ofhierarchical levels of process flow definition.

Our standard user inerface, FABFORM, has been improved and extended so that it can now be calleda. a procedure from either C or Lisp.

S,We have made substantial progress on the development of a simulation interpreter. Duane Boning hascompleted his Ph.D. proposal, "Custom Fabrication Proces- Design: Tools and Methodologies," March 8, 1988.We have also realized that we must provide for operation of partial flows. One impediment to the use of our

PFL is that users change their minds about the process specification as they progress with the actual fabrication.By concatenating the processing history of fabrication with a number of partial flows we at least will have atrace which accurately reflects what happened. A prototype version of the Suprem-IIl Simulation Interpreterhas been completed. The interpreter generates Suprem-Ill fragments for multiple one-dimensional crosssections, produces a Makefile to minimize shared simulations, and provides analysis (plotting, sheet resistance,and threshold voltage) capabilities. Duane Boning is now working to get an accurate description of the CMOS

Baseline process, so that meaningful comparisons of fabrication and simulation of the MIT standard defectarray is possibl., and so that realistic work with the flow language can progress.

We completed a substantial reorganization and cleanup of our CAFE software. We now have it allexisting under a single directory, /USR/CAFE, in preparation for distribution to our fabrication laboratory andperhaps elsewkhere.

We have acquired another computer and several workstations. We installed a VAX 750, garcon, for useas a file server. We have installed three monochrome and two color VS2000s, two Symbolics Lisp machines,and relocated the TI Explorer. We have installed a terminal concentrator in building 13. All of our computers3 arc now on the same subnct with the result that file traisfer and NFS services are now robust.

This summer we made a major new release of our CAFE software. We installed INGRES 5.1, anupdated schema, operate-machine, and a series of applications programs related to status and log report.;.These programs were described in previous progress reports. In addition, Mike Hevtens generated a number ofnew database access routines which provide for more efficient fil .ing and sorting by implementing theseoperations at the underlying data base level instead of at the applications programming level. In spite of theseoptimizations we found that the system response time had deteriorated substantially both due to increasedprogram size and an increase in the number of active users.

We temporarily took the computer CAF1.MIT.EDU used for CAFRE development out of service inorder to provide better response time on CAF2.MIT.EDU, which is the computer used by fabricationlaboratory users Thi, doubled the memo y available on CAF2 from 8 to 16 megabytes. Later, we were able to

borrow, some memor and we restored CAF1 to sericc and now have 16 megabytes of main memory for CAF2.Wc conducted timing tests on CAF2 with 16, 24, and 32 megabytes of memory. Sever identical CAFEoperations were started in quick succession. One sample operation implemented in Lisp took 160 seconds withIf) meeablcs and 8 seconds with 24 or 32 megabves. A different operation implemented in C took 125U seconds with 16 mecgalytes and 85 to 9(1 seconds with 24 or 32 megabytes. The primary reason that the Lispprogram is slower than the C program is that it is much larger and the p.,ging time is thus lenger. Clearly weneed to acquire more memr%.II

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A fast method of logging in and out of the laboratory has been implemented by Rajeev Jayavant. The 3actual computations involved is not any faster but the user no longer must wait until they finish. This has beentested but not vet installed on CAF2.

An extension to the reservation program has been made and tested, though not yet installed on CAF2. IA new program to make periodic reservations was written by Joseph Kaliszewski and he also modified theexisting reservations program. Periodic reservation enables the convenient entry of lab hours and weeklyscheduled preventive maintenance. Reservations indicated by the periodic reservation data structure are Imcrgcd into blank areas of the reservation forms so as to provide this information to lab users. However, if alab user wants to make a reservation which overrides these, he or she can do so.

We plan to re-implement the Gestalt object-like interface to provide an in-memory storage option forthose sites and applications who do not want or need a persistent database, and do want and need fast, in-memory, object-like data structuring. 3

We have begun serious consideration of the integration of scheduling programs with CAFE. Xiewei Baihas started to integrate FABFORM jitio his factory simulation programs. We have discussed schema additionsto represent the data required for scheduling programs but have not yet settled on their final form. The present Iapproach is to write a single machine scheduler first with later extension to a multi-machine scheduler.

The programs relating to lot and wafer tracking have been rewritten and tested but not yet installed.Create lot and create.proessname were rewritten by Rajeev Jayavant. Showlot and tracklot were rewritten byD. E. Troxcl. The latter two programs include optional reports of the history of opinsts and existing WIPs.

A project to automate the operation of the HP wafer prober has been initiated by Merit Hung and 3Joseph Kalis/ewski under the direction of Professor Antoniadis. This project is proceeding in three phases, thefirst being development of a stand alone program on the computer supplied with the wafer prober. The secondphase w1il be to enable the operation of this machine from another computer (CAF and/or CAF2). A third Iphase will be to integrate the operation of this machine with the operate-machine program running underCAFE. I

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3 III. Modular Process

The objective of this task was to develop and implement a workstation environment for process anddevice design. The motivation came from the success of the workstation environments for VLSI chip design,many of which were based on university work. Process and device design is much more compute-intensive thanchip layout, because of the requirement for simulation of partial differential equations representing either thefabrication steps for wafers or the current flow in devices.

The progress of this activity is chronicled below by quoting from the semiannual reports prepared foreach DARPA VLSI Contractor's Meeting, held each spring and fall.IFall 1985

5 We have developed a preliminary architecture for a CAD program to implement modular processsynthesis. The program, called MASTIF (MIT Analysis and Synthesis Tool for IC Fabrication), implements aworkstation approach to IC fabrication process design. It is a menu- and window-oriented program which

i provides a methodology and uniform software structure for the connection of process- and device-design tools.

MASTIF is written in C and Fortran, which permits easy connection to existing and prospective processand device simulators and related tools. MASTIF currently supports incremental development and versionmanagement of a process specification under development. It also provides mechanisms for the simulation andanalysis of physical cross sections, and includes interactive graphics interfaces to SUPREM-IlI and MINIMOS.

Spring 1986

The focus of this project is the development of methods for IC fabrication process and device design inthe context of a Computer Aided Fabrication (CAF) research laboratory. The main thrust of our work centerson the development of what we call the MASTIF workstation. This is a menu- and window-oriented programwritten in C and FORTRAN which provides methodology and uniform software structure for the connection ofprocess and device-design CAD tools. MASTIF currently includes a facility for incremental development andversion management of a process description, management mechanisms for definition of physical cross sectionsde.riv in from the overall process description, and an interactive graphics interface and data interchange for

Sprocess and device simulators (SUPREM-[II and MINIMOS). With MASTIF the user can effectively developand evaluate a fabrication process via a single integrated workstation.

In parallel with the development of MASTIF, work is under way in the area of process and devicemodeling. Extensive use of SUPREM-II has revealed several shortcomings of the program. Perhaps the mostsignificant improvement that we have implemented in ar experimental fashion is the inclusion of dynamic clus-tering for arsenic atoms in silicon. Similarly, we have scrutinized, found inaccurate, and improved significantlythe electron-mobility model in the device simulator MINIMOS.

Two new process-simulation modules have been developed during this period. The first is used for thegeneration of as-implanted and diffused-doping profiles generated by means of Focused Ion Beam (FIB)implantation. This is in support of a separate FIB applications research program also supported by DARPA.

The second process-simulation module is still in an experimental form. It allows the simulation ofnonuniform silicon oxidation. The calculated results are the shape of the grown SiO 2 and the stress exertedduring the process at the Si/SiO, interface. A boundary-integral-equation method has been developed for thenumerical solution of the problem. Because of the many uncertainties in physical parameters for grown SiO 2 ,the present simulator allows the investigation of three different oxide-movement behaviors: elastic, viscous, andvisco-elastic. Work is under way to establish, by comparison with experimental data. the range of validity ofthese different models.I

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Accomplishments for the period April through September 1986 are in three related areas, all involvingCAD tools for process and device analysis. These include completion of the MASTIF project, modeling andsimulation of kinetic clustering and precipitation effects during diffusion, two-dimensional silicon oxidation, andfinally, investigation of a profile interchange format and database system.

The implementation of MASTIF was completed in May, 1986. The workstation incorporates tools forprocess specification and simple process verification, and interfaces (both front and back ends) to process anddevice simulation. Drawing on analogies from other areas of VLSI design, a blueprint for future developmentof tools beyond simple simulation has been completed [1. During the summer, MASTIF was successfullyported to run on a true workstation, the Vaxstation-II.

On the pure process simulation side of the project, we have made an effort to adequately simulate theeffects of impurity clustering and precipitation in silicon. The purpose was to implement models and methodspreviously developed [21 in a general and practical manner. A local version of the SUPREM-IlI (31 processsimulator was modified extensively, and now incorporates a general exchange mechanism between mobile andimmobile species of an impurity. Thus, both kinetic clustering and precipitation effects can be effectivelysimulated.

We have continued our effort on modeling two-dimensional thermal oxidation. A generalized BoundaryElement Method (BEM) was developed for modeling linear viscoelastic materials. This new approach was Ibased on Kelvin's solution modified for viscoelastic flow. It could handle a wide range of relaxation time,

dealing with elastostatic deformation and viscous incompressible flow at the two extreme ends withoutanomalies as previously encountered. Simulations on Local Oxidation of Silicon (LOCOS) structures indicatedthat stress created during oxidation could be extremely high, particularly when the mechanical barrier effect ofsilicon nitride mask is included. This suggested that both silicon nitride and oxide flowed or plasticly deformedmore readily than what we assumed. Stress-induced retardation of reaction rate and diffusivity of oxidants werealso studied. In addition to an overall lowering of stress, the shape of the oxide changed significantly when suchnonlinear effects were included.

One important finding of the MASTIF project has been to note the need for a uniform representation ofwafer and device structure information, both for use by individual tools in a complete design system, and forinterchange between different simulation sites. We have been investigating the form such an interchangeformat (PIF, or Profile Interchange Format) should take, as well as the need for standardization within theprocess and device simulation community. Preliminary proposals and implementations for both the "inter-change" format and the corresponding "database" format have been completed [4].

SNC, a hierarchical storage system designed for process and device simulators, was operational. Two ofthe goals of SNC were to

(1) enable a program to generate a complex data structure for use by other programs. Hierarchicalorganization ensures that the structure can be expanded without introducing compatibility problems. I

(2) aid program development by providing users a set of well-defined interface routines and run-time checking.With SNC, users need not create many output files. Most data can be put into a single SNC file.Retrieving data from a SNC file is simpler than from a normal ASCII or binary file.

A utility program was written for browsing SNC files, It could display the directory structure of a SNC file andprint the contents. Access speed of SNC was made extremely fast by mapping the data file into programmemory space.

References

[11 D. S. Boning, "MASTIF - A Workstation Approach to Integrated Circuit Process and Device Design," M.S.Thesis, MIT, May 1986.

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121 D. S. Boning, "Computer Simulation of Arsenic Clustering Effects in Integrated Circuit Processing," B.S.Thesis, MIT, May 1984.

13] C. P. Ho and S. E. Hansen, "SUPREM III - A Program for Integrated Circuit Process Modelling andSimulation," Stanford Technical Report DEL 83-001, July 1983.

[41 D. S. Boning and T.-L. Tung, "A Proposal for A Profile Interchange Format," CAF Working Papers, MIT,3 April 1986.

3 Spring 1987

The implemcntation of the first version of MASTIF was completed in May 1986. A menu- and window-oriented program has been developed as the first step in meeting the need for an integrated process designsystem. MASTIF includes aids for process specification and simple process verification, and provides interfaces(both front and back ends) to the SUPREM-I1 process simulator and the MINIMOS device simulator.MASTIF was successfully ported to run on a true workstation, the Vaxstation-H under VMS. The program is3 now in its second phase of development and in the process of being ported to a UNIX environment.

We have continued our effort on modeling two-dimensional (localized) thermal oxidation. Thermaloxidation of silicon involves the diffusion of oxidant species from the gas-oxide interface to the oxide-siliconinterface, and the transport of newly formed oxide away from the latter. Under suitable formulations, it can beshown that the diffusion process is a Laplace problem and the viscoelastic flow of oxide is a biharmonicproblem. For these boundary value problems, the unknown boundary parameters can be obtained from theknown boundary conditions without calculating the interior solutions. The diffusion problem is solved with astandard boundary element method (BEM) for potential problems. A generalized viscoelastic BEM has beendeveloped to model the oxide flow. Utilizing constant-velocity kernel functions, this viscoelastic BEM can dealwith a wide range of stress relaxation times, covering elastostatic deformation and incompressible creeping flow.Our approach achieves simplicity and efficiency by solving a two-dimensional problem as line integrals on theboundaries. Simulations of Local Oxidation of Silicon (LOCOS) structures indicated that stress created duringoxidation could be extremely high, particularly when the mechanical barrier effect of silicon nitride mask isincluded. This suggests that both silicon nitride and oxide flow or plasticly deform more readily than assumed.Stress-induced retardation of reaction rate and diffusivity of oxidants are also studied. In addition to an overalllowering of stress, the shape of the oxide changes significantly when such nonlinear effects were included.

Development of general analysis tools and interfaces requires a central, agreed-upon representation ofthe structures these simulators and associated tools manipulate. We have been heavily involved in standardswork related to a Profile Interchange Format (PIF), and are implementing a library of routines for accessingthese structures based on the PIF. Specific tools and components under development include SNC, a local"database" form for PIF storage, PIFLIB, a library of routines for tool interface to the database, and PIFPLOT,a general, interactive structure analysis tool interacting with the PIF database. It is expected that the availabilityof a general representation for process and device structures will greatly enhance the capabilities of theMASTIF workstation, and will spark development of additional tools to aid in the design of IC processes.

I Fall 1987

During the period of interest, substantial progress was made toward a computer-aided environment forprocess and device design. The two major aspects of this work were experimentation with a "ProfileInterchange Format (or PIF) for the exchange of geometry and attribute information about simulated ICstructures, and coupling between process design, simulation, and the development of a process flow language.

Earlier work with the MASTIF project has made it clear that work is needed to develop a commonrepresentation of simulated process and device structures in order to effectively interface and use existingTCAD tools. To this end, an international standards effort has been directed toward the specification of theProfile Interchange Format. A first-cut proposal for intersite exchange is on the table.

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We felt it was important to experiment with this format before adoption as a standard. To this end. wemodified the SUPREM-11 and SIMPL-2 process simulators to output ASCII PIF code. An ASCII PIF parserwas written, which reads the textual file into internal C structures. An interactive shell (the "PIF shell' orpshell) enables the user to browse the geometry and attributes, and to generate geometry or attribute plots.

We realized several benefits from this experimentation. First, we found several general and specificproblems with the proposed PIF standard, and have made recommendations to the standard committee.Second, we found that the textual, ASCII "intersite" PIF format is inappropriate for direct use by various tools,and that an "intertool" or database version of the format is critical for effective use by CAD tools. We haveformulated a plan for the coupled development and implementation of both an intersite and intertool version ofthe PIF. 3

The second aspect of this work relates to the interface between the rest of the CAF (Computer AidedFabrication) environment and the TCAD environment. First, we have developed extensions of the PIF, whichwas originally developed in the context of process and device simulation only, so that we may represent cross Isections and wafers in a uniform fashion for simulation, measurement, and manufacturing.

Secondly, we have been careful to consider the needs of process simulation during the development ofthe process flow language. We have built experimental interpreters of the flow language that provide input forthe SIMPL-2 program (as a "change in wafer state" interpreter) and SUPREM-I1 (as a "wafer treatment"interpreter). We arc working to enhance the interpreter, which in its current state might be best described as a"translator," so that we may effectively manage the design and simulation of the process flow.

Over the lasi six months, a few enhancements have been made to the two-dimensional thermal oxidationsimulator. This simulator uses the boundary element method to model the viscoelastic flow of silicon dioxideand the diffusion of oxidants.

The program has been converted from VAX/VMS Pascal, which is not portable due to its languageextensions, to C. It now runs on VMS and various Unix systems. Previous attempts of modeling nonlineardiffusion as a biharmonic system achieved only marginal success. We have switched to using domain cells,which are placed in critical regions only. Because only a few cells are used, the system matrix is smaller andcomputation is faster than the biharmonic approach. Better results have been obtained; also the anomaly of Inegative oxidant concentration has disappeared. It should be noted that the improvement is partly due to theusc of "staggered grid" technique whereby different parameters are computed on different coordinate points.

The method for computing str ,ss history has also been revamped. The "sources" are kept and updated Uat every time step to produce new stress fields. This arrangement permits stress relaxation time to be changedlocally to simulate visco-plastic flow. The effectiveness of such a approximation still needs to be verified,pending numerical results for cylindrical oxidation mentioned below. I

For his Ph.D. thesis at Stanford University, Dah-Bin Kao conducted a series of oxidation experiments oncylinders of different curvatures and proposed a viscous flow model for the effect of stress on oxide thicknesses.On convex structures, his model contains a positive feedback term that causes a self-consistent solution to blowup. The failure is partly due to the simplistic viscous flow model. A more realistic viscoelastic flow model willalways guarantee the existence of a solution. We find that the new model still has an undesirable effect offreezing up, namely the oxide (fluid) suddenly solidifies when the curvature is below a critical value. We areseeking different functional behaviors of stress to match Kao's experimental data. This remodeling effort isnecessary to provide parameters for use in the more general two-dimensional simulation.

Spring 1988

In the last six months, we have experimented with a "Profile Interchange Format" (or PIF) for the iexchange of geometry and aitributc information about IC structures. Prior work was based on an ASCII or"intersitc" representation of the PIF, as recently outlined by Steve Duvall of Intel. Our previousexperimentation with this ASCII PIF highlighted the unsuitability of the format for direct use by simulation Itools. I

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We have recently been working, then, toward an "intertool" version of the PIF. An interface to Gestaltforms the basis of the "intertool" or "database" form of the PIF. Utilities based on the PIT database include aSuprem-IIl to PIF database (sup2db) for stuffing the results of process simulation into the database, and adatabase to Suprem-Ill (db2sup) for generation of the wafer structure as demanded by Suprem-Jl. In addition,we have developed a limited intersite PIT parser which translates the ASCII format into the database PIF(pif'2db).

We are continuing development of the PIF database interface for direct use by a wide variety of processdevelopment tools, as well as pursuing implementation of tools based on this PIE database. The tools that musthave access to wafer information, and thus to the PIE database, include not only process simulators such asSuprem-lll, but also device simulators (such as MINIMOS), process flow language interpreters, gridmanipulation programs, and analysis and plotting utilities.

We are continuing development of a CAD environment for the design of fabrication processes. Thisenvironment must be based on solid representations of the two "objects" being designed: structures to befabricated, and fabrication processes. We have been working to lay the necessary representational groundworkupon which the complete CAD environment will be based: the PIF database provides the framework for therepresentation of the wafer, while the Process Flow Language (PFL) provides the representation of the process.In the last six months, these representations have been developed to the point where we were able to beginexperimentation with tools based on the PIF and PFL.

3 We have developed an experimental Process Simulation Manager, and coupled this with the need tosimulate the MIT Baseline CMOS process. The baseline process was represented in our experimental ProcessFlow Language. A nominal "Suprem-Ill Translator" produces fragments of Suprem-IIl code to simulateoperations within the flow. Using UNIX utilities, particularly make, the prototype Manager enables us tomaximize the sharing of computation between multiple cross sectional simulations, as well as minimize andautomate resimulation when the process changes. A number of post-processing utilities allow the interactive3analysis of final and intermediate simulated profiles.

The prototype Simulation Manager does not provide a tight coupling between the flow and simulation,nor does it manage other important aspects of design besides simulation. We are continuing development ofthe Simulation Manager, as well as a Design Supervisor to provide additional capabilities in process verification,analysis, and synthesis.

I Fall 1988

Development of the Profile Interchange Format (PIF) has proceeded in two areas: implementation of aPIF program interface, and development of individual PIF utilities. Taking the published proposal for the"intersite" (or ASCII) PIF as a starting point, we have been developing a set of routines through which CADand CIM programs may access PIF objects. This "intertool" format is based on the Gestalt database interfaceto a geometric and attribute schema definition tailored to the PIF, and provides a uniform or "standard"functional program interface. Tools implemented with this interface should, like the data itself, thus beportable. We have so far developed a small set of such utilities, including format conversion programs fromSUPREM-Ill to the PIF ("sup2pif" and "pif2sup"), between the ASCII and database versions ("pif2db" and"pifdump"), as well as a simple profile plotting utility ("pifplot"). Implementation of the interface and specificPIF utilities is continuing.

The Technology (encompassing both Process and Device) CAD Environment is based solidly on thewafer representation (PIE) and the process representation (PFL or Process Flow Language). During the lastsix months, we have focussed on development of two tools for this environment. The first of these is aprototype Simulation Manager, which has as a key component a translator from the PFL representation of theprocess to the input required by SUPREM-III. The specification and handling of multiple one-dimensionalcross sections for simulation has been a major addition to the Manager. Utilities allow minimal simulation ofthe process (the MIT CMOS Baseline process has been the vehicle for testing the manager), evaluation ofwhere the process diverges for multiple cross sections, as well as interactive examination of simulation results.

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The second area of research we have begun is to investigate simple process synthesis utilities. We have writteninitial versions of an "Oxidation Advisor," an "Implantation Advisor," and a "Diffusion Advisor" to providephysically-based initial guesses for process parameters during process design. Work is underway to furtherbuild "Correction Advisors," as well as to experiment with physically-based optimization methods. 3

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IV. Scheduling

The objective of this task was to develop algorithms to be used in scheduling operations in a VLSIfabrication facility. Suitable models were developed, that captured the essential features of the steps forscheduling purposes. Interesting challenges included the importance of setup times, frequency of equipmentfailures, and use of the same machine more than once in a single process flow.

The progress of this activity is chronicled below by quoting from the semiannual reports prepared foreach DARPA VLSI Contractor's Meeting, held each spring and fall.

Fall 1985

During this period, we have begun to gather information on the scheduling issues in semiconductorfabrication facilities. We plan to develop a model of such systems which will allow the development ofscheduling algorithms that incorporate feedback of state information. Such models will include phenomenasuch as machine failures, demand variations, set-up times, parts mix, maintenance, finite machine capacities,and other features. These very features are the ones that frequently make system scheduling difficult.

It is anticipated that the management system will be organized hierarchically. Short-term managementand control -- real-time control -- must be consistent with long-term management decisions. Lower levels in thehierarchy are more spatially (as well as temporally) limited than higher levels. That is, they deal with fewermachines. Higher levels have more power than lower, in the sense that they set objectives for the lower levels,which must indicate their capabilities to the higher levels.

Spring 1986

Research during this period focused on three activities: studying the integrated-circuit fabricationprocess at a systems level, formulating a mathematical model of an integrated-circuit fabrication facility, anddeveloping an electronic sign-up sheet for scheduling the laboratory.

The first study is to define the scheduling problem. This involves studying VLSI technology, theconstruction of the MIT Integrated Circuits Laboratory, and user requirements. It was discovered that a fewkey elements of the problem may have dramatic impact on the final schedule. A setup is required when there isan important change in type of operation at a machine, and can be due to changes of gases, water temperatures,or other required materials. Setups complicate scheduling because machines that are undergoing suchchangeovers are not available for productive operations. There is an incentive to put off changeovers as long aspossible because when they take place often, production capacity is reduced. On the other hand, if changeoversare performed too infrequently, some lots will be delayed a long t: .-e.

Randomness is due to machine failures and unpredictable demand on the facility. In a university setting,the mix of chips going through the facility has very little consistency from week to week. We will have to groupthe demands for scheduling purposes, and use guesses based on historical data. The presence of randomnessmeans that any schedule must have some idle time in it, so that a perturbation does not propagate indefinitely.It also means that there must be some means for rescheduling after events like machine failures.

We are also investigating the differences between a university laboratory and a commercial productionsystem. In a commercial facility, machine failures are no less important, but there is a more predictabledemand on the facility. The CAF Scheduling group visited DEC in Hudson, Massachusetts on February 11,1986 to observe their production system.

The second activity is to develop a scheduling model of the system. Developing such a model requiresidentifying scheduling objectives, decomposing the problem, solving each of the subproblems, developing adatabase to store the required information, and testing the solution on the facility. Scheduling is complicated bysetups and randomness, and various sources of both are being studied. The main focus of the analytic activity is

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Page 20 Ithe setup issue. The approach now being explored views setups as events that take place at a lower frequencythan machine operations and most other events. A slow-time-scale model is being explored that accounts forthe time that the system spends in each setup configuration, as well as the time spent in changing configura-tions. The impact of setups on capacity is modeled explicitly.

Remaining work on this formulation includes modeling the scheduling objective, and then translating thesetup frequencies that are calculated this way into actual times at which to perform the changes inconfigurations.

The purpose of this activity is to develop a simple Version 1 scheduler which will not use thesophisticated ideas that are described above, but which can be implemented and used relatively quickly. Theexisting paper system is being designated as Version 0, and the first electronic system as Version 1. Greatconsideration is being given to ease of use. It will be designed to emulate the paper sign-up sheet in the oldfacility, with no additional features except for the fact that it can be accessed from any terminal.

Fall 1986

Research during this period focused on three activities: Studying the integrated circuits fabrication Iprocess at a systems level; Formulating a mathematical model of an integrated circuits fabrication facility; andDeveloping simulation and scheduling software. 3

The effort to define the scheduling problem continues. We continue to study MIT laboratories andcommercial facilities. We are investigating the following phenomena: setups, machine failures, randomdemands, and other random, discrete events that complicate scheduling. 3

A model formulation is being developed that takes into account all the kinds of events described above.A combinatorial optimizzation approach would be infeasible because of the problem size, but, because theimportant events take place at different frequencies, there is structure that can be exploited. A multiple timescale decomposition is being explored.

Particular emphasis is being devoted to the long time that wafers spend in clean rooms. The response torandom events is influenced by the fact that a long time passes between the introduction of material into thesystem and when it encounters later operations.

We have begun an effort to test the ideas and model formulation described above. Based on our study Iof MIT and other facilities, and on the model summarized above, we are planning a multi-level schedulingprogram. The top levels will be based on a continuous formulation that emphasizes delay, and the lower levelswill perform simplified searches. I

A demonstration software designed to schedule the Integrated Circuits Laboratory at MIT is beingdeveloped. It makes use of an Artificial Intelligence approach to facilitate the search. The possibility ofresolving incomplete, inconsistent and qualitative information as well as learning through experience are alsobeing investigated. ISpring 1987

In the effort to define the scheduling problem, we are concentrating on using the MIT laboratories as 3case studies. Mathematical and simulation models, described below, are being based on what we learn here.

As a mathematical model of an IC fabrication facility, the multiple time scale decomposition underdevelopment shows great promise. A new basic model is being investigated which will help us refine and better Ijustify the tentative mathematical results we have developed thus far on hierarchical scheduling.

In this approach, the scheduling algorithm is divided into a set of levels which correspond to classes of 3events that are distinguished by their frequencies. At each level, two kinds of calculations are performed: small

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linear programs, to determine frequencies of higher frequency (lower level) events; and simple combinatorialoptimizations, to determine exact times for the events of that level, whose frequencies have been calculated athigher levels.

Software which will implement a multiple time scale decomposition approach to hierarchical schedulingis under development. A simulation is also under development. The scheduling software will first be testedwith the simulation, and then used to run the laboratory.

An electronic machine reservation system is also under development. In its initial version, it isessentially an electronic sign-up sheet for equipment. It will later be used, after modifications, as the lowest3 level of the hierarchical scheduler.

Fail 1987

During this period, the theoretical basis for the scheduling and planning hierarchy was strengthened.

Three kinds of aggregation/decomposition are required for a fully developed scheduling and planninghierarchy: temporal (in which higher level decision-makers make less frequent but individually more importantdecisions): spatial (in which higher level decision-makers affect a larger portion of the facility); and material (in3 which higher level decision-makers are concerned with broader classes of products).

Temporal decomposition divides the scheduling and planning problem along time scale or frequencylines; spatial decomposition puts boundaries in space around groups of pieces of equipment. Our goal is to fullydevelop all three parts of the hierarchy, and to implement them in a set of computer programs which will beintegrated with the CAFE system. These programs, and their communications, are likely to be complex, butthey offer great savings in computer time and accuracy in comparison to other methods.

U Most progress has been made in the temporal hierarchy. A structure has been developed based on a setof necssary conditions described in VlSI Memo 87-406. These conditions establish the data of interest at eachlevel of the hierarchy, as well as the relationships among the data at different levels of the hierarchy. Theserelationships in turn suggest the form of the computations that are required at each level.

Specific classes of events that we have been studying include operations, machine failures setup changes,and demand variations. In present formulations, we assume that each class of events occurs at a frequencywhich is substantially different from all the others, and each class is treated in detail at a different level of thehierarchy.

I We have also studied spatial decomposition by performing numerical experiments. We conclude that, ateach level of the hierarchy, local decisions should be made on the basis of the amount of material in the system,the amount of material found locally, and the difference between actual behavior and the requirementsspecified at higher levels. Some ideas for combining the spatial and temporal decompositions are beginning toemerge.

We have identified the roles of different kinds of users of the hierarchy (students or technicians;professors or engineers; managers; and scheduling system implementors). They will interact with the programsat different levels in different ways.

We have been designing a set of simulation programs that will have a variety of uses, including thetesting of the planning and scheduling methods developed here and the prediction of the actual behavior of aproduction system for managerial purposes. These programs will carefully separate the scheduling/planningprograms from the model of the plant. This will allow easy comparison of different schedulcrs, and willfacilitate transferring the scheduler to a real fabrication facility.

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IPage 22

Spring 1988 3A draft report has been written summarizing our knowledge of semiconductor fabrication from the point

ot view of a scheduler. We have sent it to many well-informed people in industry and academia and solicitedtheir comments by including a questionnaire. Some comments have come back, but we expect to get the bulk ofthe responses during April 1988. Readers who would like to review this draft and possibly make comments areurged to contact us.

The multiple-time-scale decomposition is under development and shows great promise. A new basicmodel is being investigated which will help us to refine and better justify the tentative mathematical results wehave developed thus far on hierarchical scheduling n

In this approach, the scheduling algorithm is divided into a set of levels which correspond to classes ofevents that are distinguished by their frequencies. At each level, two kinds of calculations are performed: smalllinear programs, to determine frequencies of higher frequency (lower level) events; and simple combinatorial Ioptimizations, to determine exact times for the events of that level, whose frequencies have been calculated athigher levels.

We are devoting a great deal of attention to the scheduling of setups since they are likely to becomeimportant in modern multiple-purpose fabs, i.e., those that can be used for more than one basic process.

Software which will implement this multiple time scale decomposition approach to hierarchical Uscheduling is under development. A simulation is also under development. The scheduling software will firstbe tested with the simulation, and then used to run the laboratory. 3Fall 1988

An important phenomenon was added to the set of models that have been part of our study, namely thefact that many semiconductor fabrication operations are performed on a batch of wafers simultaneously.Examples include oxidation, deposition, ion implantation, and others. While this is seen in other kinds ofmanufacturing, it is pervasive in this industry.

This feature is important because in order to realize the full capacity of a system, the machine chambersmust be as full as possible. There are two reasons for this: (1) it takes as much time to do an operation on one Iwxafcr as 1W), but 91)"'; of the capacity is wasted if only one wafer is in a chamber that can hold 100, and (2)

maintenance must be performed on machines that do deposition operations when the total amount depositedsince the last maintenance rcachcs a given level, independent of the number of wafers that were in the chamber,,hen the depositions took place.

One way to keep the chambers full is to have large lots. However, this is not desirable in a system thathas low ',olumc or that has a diversity of products. Another approach is to group together distinct wafers that Irequire the same operations. This leads to more complex modeling and scheduling issues, which we are

currently studying and simulating. A prototype scheduler has been built for a single machine.

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* V. Equipment Models

This task began in Fall 1986. Its objective was to develop models for semiconductor fabricationequipment that were capable of being used for several purposes, and to integrate those models into CAFE. InU fact, the integration into CAFE was delayed until the present contract expired. The principal results were thedevelopment of models incorporating a mix of empirical data and fundamental reasoning, and a demonstrationthat such models could be used to optimize the operating point of practical equipment. The first process step3 considered was LPCVD (Low Pressure Chemical Vapor Deposition) of undoped polysilicon.

The progress of this activity is chronicled below by quoting from the semiannual repo.ts prepared for3 each DARPA VLSI Contractor's Meeting, held each spring and fall.

Spring 1987

'VLSI machine modeling has taken a concrete form during the past several months. The thrust of thework is to combine analtical modeling with matrix experimental approaches and to provide an executableprogram which will facilitate the following:

1. Off-line quality control to determine the point in operating space which provides the greatest robustness3 against variations in process parameters and therefore vields the most consistent results.

2. On-line quality control used to tune a process based either on measurements made after a previous run or onin-situ measuremcnts.

Matrix experimentation is a collection of methods wherein some or all of the relevant process variablesare varied simultaneously in an experiment and information is extracted from the results statistically [1,21. In

contrast to conventional single-variable experimentation, the matrix approach offers a tremendous economy ofexperimental effort. This is crucial in a production environment as the interruption to work flow must be keptto a minimum. wkhilc in a research environment it is useful in order to optimize a new process as quickly aspossible. Matrix experimental techniques have been employed with great success on VLSI processes at AT&TBell Laboratories for approximately the last six years 13.4.

Our process modeling effort wil begin by utilizing analytical and experience based background to definethe process variables and their values for a matrix experimental approach. The analytical work will be basedboth on process models available in the literature and on simple physical models. Future extensions of the workwill attempt to more closely couple the analytical and experimental approaches by using matrix experimentation3 toerifv analytical models, specify numerical values for the anal.tical models, and also to improve analyticalmodel,,.

The first process selected for the machine modeling effort is LPCVD of polysilicon. Optimization ofthickness uniformity across a wafer, between wafers in a single lot, and between runs will be the goal.

References

U [t[ (;. Box. W. Hunter. and J. Hunter, "Statistic.; for Experimenters and Introduction to Design Data Analysisand Model Building." Wiley, 1978.

[21 G. Tauchi. "Introduction to Quality Engineering." Krauss International Publications, White Plains,. NY,l .

[31 N. Phadke, N. Kuckar, D. Spccnev, and M. Grieco, "Off-Line Quality Control in Integrated CircuitFabrication Using Experimental Design," The Bell System Technical Journal, 1983.

14 R. Nackar and A. Shoemaker, "Robust Design: A Cost-Effective Method for Improving ManufacturingProcc,,sc,,," AT&T Technical J .urnal, March/April, 1986.

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Page 24 IFall 1987

During this period significant progress was made by George Prueger, a master's candidate, on themodeling of LPCVD of undoped polysilicon. The principal area of progress was on the experimental side of theproject. AI, ,rthogonal array experimental design was created using two flow rates, an injector position, and Ipressure as the process parameters. Arrangements were made with BTU Bruce of Billerica, Massachusetts toconduct experiments on equipment in their laboratory. A complete experimental regimen was established withBTI i's full cooperation.

The experimental work consisted of running lots of 150 six-inch wafers, of which thirteen were testwafers and the remainder reused dummy wafers. Approximately 5000 A of poly was deposited in eachexperimental Iun. Thickness measurements were made at five spots on each wafer using optical measurementtechnique,, Data was plotted for each of the nine experiments of the orthogonal array.

Several of the data points were repeated in an effort to cxmine consistency of results. A second smallerarras of experiments was conducted using only the load-end injector (the other two injectors were turned off) ina depletion type experiment. These experiments were designed to yield information on the rate constants of thechemical reactions.

Analytical modeling usine a finite difference model incorporating both diffusion and coneclion in the,,stem has begun.

Spring 198

Durinv this period the first equipment model was completed. This model concerns the low pressureher:mical vapor deposition oi polysilicon in a hori/ontal tube furnace. The model consists of a one dimensional

hnite differencc numerical formulation which encompasses convective and diffusive mass transport in theannular space between the wafers and the tube liner, and accounts for the surface reaction rate limiteddepition of p l.silicon on the wafers with the associated generation of hydrogen and incorporation into thebulk of lh ga,. The model permits as input the gas flowrate to th, three injectors, positions of the injectors,rcactor Veometrs, tcmpera'urc profile down the tube, and operating pressure. The adjustable coefficients in the Imodel ha~e bcen c.librated using a seric, of designed experiments performed at the applications lab of BTL'lirue, o ,f Billcria. Massachu,,tts. In th,,e experiments. 150 wafer loads of six-inch wafers were used. The\,11c rmcn!, il ,,d our parameters., to ea tic , rates. one injector position, and operating pressure. 3

The rcsuh from the modcl arc in cxccllent agreement with the experimental work. The model appearspredict the profile of grolth rate down the tube accurately. The model is accurate enough to be interrogated

for pr, 'ce,, oplimi/ation. and gives a predicted optimum set of process parameters which is very close to that Itound bs the experimental Taguchi oplimi/,tion.

In the near future, the model will be tcqcd in on-line quality control for its ability to predict changes 3around an opcratinv point.

During this period. (icorge Pruccr has completed his master's thesis on LPCVD of poly. A paper is inpreparation for submission to the Journal of Semiconductor Manufacturing.

Also during thi, period. Nlichclc Storm has invcstivated the use of a software package calledLLTRAMAX for on-lin quality control in CAF.

Fall 1988

Durine this lime period, progress was madc on three projects, and a fourth project was initiated. Thefirst ongoing project is an equipment model for the LPCVD of doped polysiiicon. The second ongoing projectconcerns Ihe usc of dimenional analysis in the design of experiments. The third ongoing effort concerns the

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use of sequential design of experiments for process optimization and control. The new project concerns thedevelopment of a general framework for process control.

A common element in our equipment modeling efforts is the fusion of statistical design of experimentswith physically based mechanistic modeling. Our first completed work is an equipment model for LPCVD ofpoiysilicon in a horizontal tube furnace. In this work, George Prueger developed a finite difference model forthe equipment and process and calibrated that model using data derived from designed experiments. Ourcurrent projects or modeling of doped poly and the use of sequential design of experiments seek to further theeffort at the combination of experimental design and physical knowledge.

The project on modeling of the LPCVD doped poly is being carried out by Master's student ParmeetChaddha with experimental support coming from the BTU applications lab, in Billerica, MA. The goal of thiswork is to develop an equipment model which aids in the design of the cage in the doped poly process. Thefunction of the cage is to serve as a deposition site for reactants formed in the annular layer between the cageand the tube walls, thereby resulting in uniform thickness deposition on the wafers. The challenge in cagedesign is to specify the size and distribution of the holes so that the deposit is unilorm on the wafers, and thedeposition rate is as high as possible. Our approach is to develop a highly simplified analytical model whichpredicts deposition uniformity and ratc as a function of cage geometry, and to calibrate this model using dataderived from designed experiments. Roughly one half of the experiments have been completed during thisreporting period, with the work being performed on 4 inch wafers at BTU, Inc.

3 Master's student William Wehrle has been developing methods of using dimensional analysis in thedesign of experiments. Dimensional analysis is a relatively easy means of deriving relationships betweenvariables based on physical arguments. A very general theorem called the Pi Theorem provides a set of ruleswhich can be followed to create the dimensionless groupings which chaiacterize a problem. The theorem,however, results in a tremendous choice of sets of these groupings. Mr. Wehrle has developed two rules whichnarrow the choice down when the Pi theorem is applied to the design of experiments. He will test the theory inIapplication to the LPCVD of LTO.

Masters student Michclc Storm is working on the use of sequential design of experiments for processop'imization and control, in collaboration with Ultramax Corp. of Cincinnati, OH. Sequential optimization is atechnique particularly well suited to manufacturing, where processes are inherently sequential. The basis of themethod is to perform a local regression to the measured data, thereby calibrating a quadratic response surfacecentered near the current point of operation. This response surface may be considered to be a Taylor seriesrepresentation of the process. The polynomial representation is then used to design the next experiment in acontinuous cycle of "learning and advising." Our goal is to use dimensional analysis to create grouped variablesfor use in the models, as a replacement for the primitive variable currently used. Ms. Storm has written asequential optimization program and will shortly begin experimental work on wire bonding. She will comparethe effectiveness of grouped (dimensionless) variables with the effectiveness of primitive variables foroptimization of wire bonding.

Doctoral student Rucy-Shan Guo was hired toward the end of the summer (August 1988). Mr. Guo hasspent the intervening months acquiring a background in statistics and experimental design.

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Page 2 UVI. Mechanical Property TCAD

This task was initiated in the last year of the contract. The objective was the development of TCADtools which could predict the mechanical, as opposed to electrical, properties of integrated circuits andstruci urcs. Particular attention was paid to residual stress, because of its importance in some catastrophicfailure mechanisms. The task was undertaken because of its importance for device reliability, and was relevantto the objectives of this contract because of the overlap of many of the equipment and process models in CAFE,anti khe attractiveness of incorporating the concepts into CAFE and into the process-design workstation.

Th,I progress of this activity is chronicled below by quoting from the semiannual reports prepared forcach DARPA VLSI Contractor's Meeting, held each spring and fall. 1Spring 1988

This project is directed toward the development of Technology CAD (TCAD) tools with which topredict the mechanical behavior of microfabricated devices. The application of these tools will be twofold:prcdiction and modeling of microsensor and microactuator devices as part of the design process; and analysis ofstress, distributions in microelectronic parts for reliability assessment. There are many well-documentedexamples of device failure produced by mechanical failure (cracking of dielectrics and conductors, anddclamination of coatings). At present, these are handled on a case-by-case basis, and only when the fault isdetected during life test of finished parts. The goal here is to use research on test structures to build a database and CAD environments with which to model the stress distributions in microelectronic structures prior tofabrication in order to identify high-risk sections of a design that might be prone to catastrophic mechanicalfailure. In addition, these tools, developed initially with the use of experiments on deformable structures, such Ias beams, cantilevers and diaphragms, will be used for predictive modeling during the design of sensors andactuators that include such deformable components. Effort to date has concentrated on developing data on the,tre, and modulus of polysilicon as a function of its processing history. 3Fall 1988 3

The ovcrall goal of this projcct is the development of a design capability that includes the mechanicalproperties of microelectronic materials. The specific goal during this past year has been to dcevelopexperimental methodologies with which to determine the residual stress in microelectronic thin films. The Imaterial selected for the first set oi cxpcrimcnts was polycrystalline silicon, because it is well known that itsresidual stress is very dependent on process conditions. Several experiments were carried out on polysilicon asa function of its deposition and doping. Using techniques of surface micromachining, suspended polysiliconbeams and cantilevers w ere fabricated in various thickness, doped variously, and subjected to differentsequences of thermal annealing. The residual stress in the polysilicon and the stress uniformity were thendetermined by examining vertical deflection of cantilevers with optical interferometry. In addition, themaximum free-standing non-buckled beam length was determined, which can also be related to residual stress. IThe detailed descriptions and conclusions arc contained in two papers which have resulted from this work,which are attached to this report.

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U Page 27

VII. Publications

Here is a list of publications based on work supported in part by this contract. Those readers interestedin more detail on any parti,.uidr topic may consult these publications. Single copies of MIT VLSI Memos forpersonal use may be obtained without charge (supplies permitting) by writing to the Microsystems TechnologyLaboratories, Room 39-321, MIT, Cambridge, MA 02139.

I PUBLICATIONS

Duane S. Boning and Dimitri A. Antoniadis, "MASTIF - A Workstation Approach to Fabrication Process

Design," Digest of Technical Papers, IEEE International Conference on CAD, ICCAD-85, Santa Clara,California, November 18-21, 1985, pp. 280-282; also MIT VLSI Memo No. 85-259, September 1985.

T.-L. Tung and D. A. Antoniadis, "A Boundary Integrated Equation Approach to Oxidation Modeling," IEEETransactions on Electron Devices, vol. ED-32, no. 10, pp. 1954-1959, October 1985.

Christopher Lozinski and Stanley B. Gershwin, "Dynamic Production Scheduling in Computer-AidedFabrication of Integrated Circuits," Proceedings, 1986 IEEE International Conference on Robotics andAutomation, San Francisco, California, April 7-10, 1986; also MIT VLSI Memo No. 86-304, March 1986.

Stanley B. Gershwin, "Stochastic Scheduling and Set-Ups in Flexible Manufacturing Systems,"ORSA/TIMS/Conference on Flexible Manufacturing Systems: Operations Research Models andApplications, Ann Arbor, Michigan; also MIT VLSI Memo No. 86-314, May 1986.

Duane S. Boning, MASTIF - A Workstation Approach to Integrated Circuit Process and Device Design, M.S.Thesis, MIT, Department of Electrical Engineering and Computer Science, May 1986; also MIT VLSIMemo No. 86-325, June 1986.

Sheldon X. C. Lou. Garrett Van Rvin, and Stanley B. Gershwin, "Scheduling Job Shops with Delays,"Proceedings, 1987 IEEE International Conference on Robotics and Automation, Raleigh, North Carolina,March 31-April 3, 1987, vol. 3, pp. 1345-1349; also MIT VLSI Memo No. 87-368, March 1987.

Thye-Lai Tung, Jerome Connor, and Dimitri Antoniadis, "A Viscoelastic BEM for Modeling Oxidation,"Fundamental Research on the Numerical Modelling of Semiconductor Devices and Process, Proceedings fromNUMOS 1, The First International Workshop on Numerical Modelling of Semiconductors, Los Angeles,

California, December 11-12, 1986, vol. 9, pp. 115-121; also MIT VLSI Memo No. 87-369, March 1987.

Oded Z. Maimon and Stanley B. Gershwin, "Dynamic Scheduling and Routing for Flexible ManufacturingSystems that have Unreliable Machines," Proceedings, 1987 IEEE International Conference on Robotics andAutomation, Raleigh, North Carolina, March 31-April 3, 1987, vol. 1, pp. 281-288; also MIT VLSI MemoNo. 87-370, March 1987.

Oded Z. Maimon and Stanley B. Gershwin, "Dynamic Scheduling and Routing for Flexible ManufacturingSystems that have Unreliable Machines," Operations Research, vol.. 36, no. 2, pp. 279-293, March-April1988; also MIT VLSI Memo No. 87-370, March 1987.

Stanley B. Gershwin, "A Hierarchical Framework for Discrete Event Scheduling in Manufacturing Systems,"Springer-Verlag Lecture Notes in Control and Information Sciences, vol..103, pp. 197-216, August 1987; alsoMIT VLSI Memo No. 87-406, September 1987.

Stanley B. Gershwin, "A Hierarchical Framework for Discrete Event Scheduling in Manufacturing Systems,"ILISA Workshop on Discrete Event Systems. Models and Applications, August 3-7, 1987, Sopron, Hungary;also MIT VLSI Memo No. 87-406, September 1987.

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Page 2, S

Stanley B. Gershwin, "A Hierarchical Framework for Manufacturing Systems Scheduling: A Two MachineExample," Proceedings, 26th IEEE Conference on Decision and Control, Los Angeles, California, December I9-11, 1987,vol 1, pp. 651-656; also MIT VLSI Memo No. 87-409, September 1987.

E. Sachs and G. Prueger, "Process Model Testing and Optimization Using Matrix Experimentation," IProceedings, ASME Winter Annual Meeting, December 1987; also MIT VLSI Memo No. 87-405, September1987

E. M. SacIs, G. Prueger, and R. Guerrieri, "Process Model Testing and Optimization Using Orthogonal ArrayExperimentation," presented at the 1988 WinterAnnual Meeting American Society of Mechanical Engineers,Boston, Massachusetts, January, 1988, PED vol. 27.

T.-L. Tung, J. Connor and D. A. Antoniadis, "A Boundary Element Method for Modeling Viscoelastic Flow inThermal Oxidation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.7, no. 2, pp. 215-224, February 1988; also MIT VLSI Memo No. 87-397, July 1987.

Emanuel Sachs and George Prueger, "Process Model Construction and Optimization Using StatisticalExperimental Design," Proceedings, Manufacturing International 88, Atlanta, Georgia, April 17-21, 1988;also MT V.,l Memo No. 88-442, March 1988.

D. S. Boning and D. A. Antoniadis, "A Workstation Approach to IC Process and Device Design," IEEE Designand Test of Computers, vol. 5, no. 2, pp. 36-47, April 1988.

N. S. Zarghamee, Schema Viewer: A Graphical Representation to Portray the Database Schema of the MITCAFE SYStem, S. B. Thesis, MIT, Department of Electrical Engineering and Computer Science, May 1988. I

T. A. Lober, J. Huang, M. A. Schmidt, and S. D. Senturia, "Characterization of the Mechanisms ProducingBending Moments in Polysilicon Micro-Cantilever Beams by Interferometric Deflection Measurements,"Proceedings, IEEE Solid-State Sensors Conference Workshop: Technical Digest, Hilton Head Island, South ICarolina, June 6, 1988: also MIT VLSI Memo No. 88-490, November 1988.

R. Jayavant, An Intelligent Proces- Flow Language Editor, M. S. Thesis, MIT, Department of ElectricalEngineering and Computer Science, September 1988; also MIT VLSI Memo No. 88-475, September 1988.

J. Huang. T. A. Lober, M. A. Schmidt, and S. D. Senturia, "The Maximum Free-Standing Length ofPolycrystalline Silicon Microbeams, 'Proceedings, International Conference on Material and Process ICharacterization, Shanghai, China, October 1988.

Stanley B. Gershwin, "Hierarchical Flow Control: A Framework for Scheduling and Planning Discrete Events Iin Manufacturing Systems," Proceedings, IEEE Special Issue on Discrete Event Systems, Revised VLSI MITMemo 87-406; also MIT VLSI Memo No. 88-482, October 1988. 3

N I. L. Heviens and R. S. Nikhil. "GESTALT: An Expressive Database Programming System," submitted to theSIGMOD Record; vol. 18, no. 1, March 1989, pp. 54-67; also MIT VLSI Memo No. 88-484, November 1988.

T.-L. Tung, Boundary Element Techniques for Modeling Thermal Oxidation of Silicon, Ph.D. Thesis, MIT, IDepartment of Electrical Engineering and Computer Science, September 1988; also VI..SI Memo No. 88-489, November 1988.

G. H. Prueger, Equipment Model for the Low Pressure Chemical Vapor Deposition of Polvsilicon, M.S. Thesis,MIT, Department of Mechanical Engineering, MIT, March 1988; also, MIT VLSI Memo No. 88-485,November 1988.

E. Sachs, G. Prueger, and R. Gucrrieri, "Equipment Models for Process Optimization and Control Using SmartResponse Surfaces," Proceedings, Electrochemical Society, Chicago Illinois, October 1988; also MIT VLSIMemo No. 89-513, March 1989.

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I INTERNAL MEMORA NDA

Stanley B. Gershwin, "Dynamic Production Scheduling in Computer-Aided Fabrication," MIT VLSI Memo No.85-243, April 1985.

Thye-Lai Tung, Jerome Connor, and Dimitri A. Antoniadis, "A Boundary Element Method for ModelingViscoelastic Flow in Thermal Oxidation," MIT VLSI Memo No. 87-397, July 1987.

Emanuel Sachs and George Prueger, "Process Model Testing and Optimization Using Matrix3 Experimentation," MIT VLSI Memo No. 87-405, September 1987.

Robert M. Harris and Duane S. Boning, "GIRAPHE V3.3: A User's Manual with Examples," MIT VLSIMemo No. 88-487, November 1988.

Rajeev Jayavant, "A User/Programmer Guide to the Fabform User Interface," MIT VLSI Memo No. 88-487,November 1988.

X. Bai and S. B. Gershwin, "A Manufacturing Scheduler's Perspective on Semiconductor Fabrication," MITVLSI Memo No. 89-518, April 1989.

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