Proceedings of the ASP-DAC '97

Asia and South Pacific Design Automation Conference 1997

January 28-31, 1997 Makuhari Messe

Nippon Convention Center, Chiba, Japan

Sponsored by:

IEICE (Institute of Electronics, Information and

IPSJ (Information Processing Society of Japan) ACM SIGDA (Association for Computing Machinery) IEEE Circuits and Systems Society

Communication Engineers)

Supported by:

ElAJ (Electronics Industries Association of Japan) STAR C ( Se m i co n d u ct o r Tech n o I og y Aca d e m i c

Research Center)

Additional copies may be order from:

IEEE Order Dept. 445 Hoes Lane P.O. Box 1331 Piscataway, NJ 08854, U.S.A.

Copyright and Reprint Permission: Abstracting is permitted with credit to the source. Libraries are permitted to photocopy beyond the limit of U S . copyright law for private use of patrons those articles in this volume that carry a code at the bottom of the first page, provided the per-copy fee indicated in the code is paid through Copynght Clearance Center, 222 Rosewood Drive, Danvers, MA 0 1923. For other copying, reprint or republication permission, write to IEEE Copyrights manager, IEEE Service Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855-133 1. All rights reserved. Copyright01996 by the Institute of Electrical and Electronics Engineers, Inc.

IEEE Catalog Number 97TH823 1 ISBN 0-7803-3662-3 (softbound) ISBN 0-7803-3663- 1 (microfiche) Library of Congress Number 96-78 107

Table of Contents

... Organizing Committee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Advisory Board Members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi

Steering Committee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

General Chair’s Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

Technical Program Committee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii

Technical Program Chair’s Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv

Best Paper Award Candidates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X v i

Keynotes Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii

University LSI Design Contest Chair’s Message . . . . . . . . . . . . . . . . . . . . . . . . . . 657

University LSI Design Contest Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658

University LSI Design Contest Award Recipients . . . . . . . . . . . . . . . . . . . . . . . . . 659

University LSI Design Contest Papers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661

Conference Author Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687

ASP-DAC ’98 Call for Papers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

Session 1A Rapid Prototyping

Chair: Sanjay Sawant Co-chair: Kazuhiro Shirakawa Co-evaluation of FPGA Architectures and the CAD System for Telecommunication

Tsunemasa Hayashi, Atsushi Takahara, Ken-nosuke Fukami . . . . . . . . . . . . . . . . . . . . 1 A Rapid Prototyping Method for Top-down Design of System-on-Chip Devices Using LPGAs

1A. 1

1A. 2

Fumio Suzuki, Hisao Koizumi, Katsuhiko Seo, Masanobu Hiramine, Hiroto Yasuura Kazuo Okino, Zvi Or-Bach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Jang-Hyun Park, Yea-Chul Rho . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9

19 1A. 3 Performance Test of Viterbi Decoder for Wideband CDMA System

Session 1B Delay Estimation and Optimization

Chair: Wolfgang Kunz Co-chair: Tomoyuki Fujita Delay Estimation and Optimization of Logic Circuits: A Survey (Embedded Tutorial)

Delay Estimation for Technology Independent Synthesis

Performance and Reliability Driven Clock Scheduling of Sequential Logic Circuits

1B. 1

Masahiro Fujita, Rajeev Murgai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

YutakaTamiya . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Atsushi Takahashi, Yoji Kajitani . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1B.2

1B.3

xxiii

Session 1C Circuit Partitioning

Chair: Chung-Kuan Cheng Co-chair: Masato Edahiro CBLO: A Clustering Based Linear Ordering for Netlist Partitioning 1c . 1

1c.2 Design Driven Partitioning

1C.3S

1C.4S

Kwang-Su Seong, Chong-Min Kyung . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Dirk Behrens, Erich Burke, Robert Tolkiehn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A RTL Partitioning Method with a Fast Min-Cut Improvement Algorithm

Kenichi Kawaguchi, Chie Iwasaki, Michiaki Muraoka . . . . . . . . . . . . . . . . . . . . . . . . . Acceleration of Mincut Partitioning using Hardware CAD Accelerator TP5000

Masahiro Sano, Shintaro Shimogori, Fumiyasu Hirose . . . . . . . . . . . . . . . . . . . . . . . .

43

49

57

61

Session 1D (Invited Talk) Computing Brokerage and Its Application in VLSI Design

Youn-LongLin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

2A. 1

2A. 2

2A. 3

2A. 4

Session 2A Application Specific Design

Chair: Neil Weste Co-chair: Hzroakz Kunieda A Programmable Application-Specific VLSI Architecture and Implementation for Speech Word-Recognizer

A High Performance FIR Filter Dedicated to Digital Video Transmission

An Efficient Hierarchical Clustering Method for the Multiple Constant Multiplication Problem

Structural Approach for Performance Driven ECC Circuit Synthesis

An-Nan Suen, Jhing-Fa Wang, Tswen-Duh Wang . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Shun Morikawa, Keisuke Okada, Isao Shirakawa, Sumitaka Takeuchi . . . . . . . . . . . . 77

Akihiro Matsuura, Mitsuteru Yukishita, Akira Nagoya . . . . . . . . . . . . . . . . . . . . . . . . . .

Chauchin Su, Kathy Y. Chen, Shyh-Jye Jou . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

83

89

Session 2B Power: Estimation and Synthesis

Chair: Massoud Pedram Co-chair: Yusuke Matsunaga Statistical Estimation of Combinational and Sequential CMOS Di Activity Considering Uncertainty of Gate Delays

95 An Entropy Measure for Power Estimation of Boolean Functions

101 An Enhanced Iterative Improvement Method for Evaluating the Maximum Number of Simultaneous Switching Gates for Combinational Circuits

Kai Zhang, Haruhiko Takase, Terumine Hayashi, Hidehiko Kita . . . . . . . . . . . . . . . . . 107 A Power Driven Two-Level Logic Optimizer

Jyh-Mou Tseng, Jing-Yang Jou . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 A Note on the Relationship between Signal Probability and Switching Activity

Qing Wu, Massoud Pedram, Xunwei Wu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

2B. 1

Tan-Li Chou, Kaushik Roy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chi-Hong Hwang, Allen C.-H. W u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2B.2

2B.3

2B.4S

2B.5S

xxiv

2c . 1

2c.2

2C.3

3A. 1

3A. 2

3A. 3

3B. 1

3B.2

3B.3

3C. 1

3C.2

3c.3

Session 2C Timing-Driven Layout

Chair: Wayne Wei-Ming Dai Co-chair: Takashi Mitsuhashi Modeling and Layout Optimization of VLSI Devices and Interconnects in Deep Submicron Design (Embedded Tutorial)

Jason Cong . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 A New Layout-Driven Timing Model for Incremental Layout Optimization

Fang-Jou Liu, John Lillis, Chung-Kuan Cheng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Par-POPINS: A Timing-Driven Parallel Placement Method with the Elmore Delay Model for Row Based VLSIs

Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru . . . . . . . . . 133

Session 2D (Invited Talk) Java'" in Electronic Design Automation

Peter Denyer, Jean Brouwers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Session 3A Co-Design Experience

Chair: Ahmed Amine Jerraya Co-chair: Masaharu Imai Polling-based Real-time Software for MPEG2 System Protocol LSIs

Synthesis and Analysis of an Industrial Embedded Microcontroller

ASAver.1: An FPGA-Based Education Board for Computer Architecture/System Design

Jiro Naganuma, Makoto Endo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Ing-Jer Huang, Li-Rong Wang, Yu-Min Wang . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

HiroyukiOchi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Session 3B Design Verification-Case Studies

Chair: Kuang-Chien Chen Co-chair: Tomohiro Yonedu Property Verification in the Design of Telecom Applications

Verification Methodology of Compatible Microprocessors M. Bombana, P. Cavalloro, F. Ferrandi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Joon-Seo Yim, Chang- Jae Park, Woo-Seung Yang, Hun-Seung Oh, Hee-Choul Lee, Hoon Choi, Tae-Hoon Kim, Seung- Jong Lee, Nara Won, Yung-Hei Lee, In-Cheol Park, Chong-Min Kyung . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

RTL Verification of Timed Asynchronous and Heterogeneous Systems using Symbolic Model Checking

Vida Vakilotojar, Peter A. Beerel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Session 3C Circuit Modeling

Chair: Hideaki Asai Co-chair: Atsushi Takahara CB-Power: A Hierarchical Cell-Based Power Characterization and Estimation Environment for Static CMOS Circuits

Power Consumption in CMOS Combinational Logic Blocks at High Frequencies

A New Approach for an AHDL Based on System Semantics

Wen-Zen Shen, Jiing-Yuan Lin, Jyh-Ming Lu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Sri Parameswaran, Hui Guo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Youcef Bourai, N . Izeboudjen, Y. Bouhabel, A. Tafat . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

XXV

Session 3D (Special Session) PCB Design and Electromagnetic Compatibility

- Integration of Layout and Signal-integrity Tools - “EMC-Adequate Design of Printed Circuit Boards as a Part of the System Development”

“Crosstalk Noise in High Density and High Speed Interconnections due to Inductive Coupling”

“A System for Supporting Multi-Layered Printed Wiring Board Design”

W.John . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Tetsuhisa Mido, Kunihiro Asada . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Toshimasa Watanabe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Session 4A Analysis and Trade-offs in System Synthesis

Chair: Daniel D. Gajski Co-chair: Mitsuo Ikeda Embedded Architectural Simulation within Behavioral Synthesis Environment

Evaluating Cost-Performance Tradeoffs for System Level Applications

A Quantitative Analysis for Optimizing Memory Allocation

4A. 1

4A. 2

4A. 3

A. Jemai, P. Kission, A. A. Jerraya . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Wei-Liang Ing, Allen C.-H. Wu, Cheng-Tsung Hwang . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Youn-Sik Hong, Choong-Hee Cho, Daniel D. Gajski . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

4B. 1

4B.2

4B.3

Session 4B Technology Mapping

Chair: Rajeev Murgai Co-chair: Kiyoshi Oguri Concurrent Cell Generation and Mapping for CMOS Logic Circuits

Logic Synthesis for Cellular Architecture FPGAs Using BDDs

BDD Based Lambda Set Selection in Roth-Karp Decomposition for LUT Architecture

Mineo Kaneko, Jialin Tian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

GueesangLee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Jie-Hong Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei . . . . . . . . . . . . . . 259

Session 4C Floorplanning and Placement

Chair: Jason Cong Co-chair: Takahiro Watanabe General Floorplanning with L-shaped, T-shaped and Soft Blocks Based on Bounded Slicing Grid Structure

Maggie Kang, Wayne W.-M. Dui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 A Building Block Placement Tool

VEAP: Global Optimization based Efficient Algorithm for VLSI Placement Kong Tianming, Hong Xianlong, Qiao Changge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

A n Improved Objective for Cell Placement Yu-Wen Tsay, Hsiao-Pin Su, Youn-Long Lin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

i

4C. 1

4C.2

4c.3s

4C.4S

Jonathon Dufour, Robert McBride, Ping Zhang, Chung-Kuan Cheng . . . . . . . . . . . . . . 271

4D.lP

4D.2P

4D.3P

4D. 4P

4D.5P

4D.6P

4D.7P

4D.8P

4D.9P

4D.10P

4D.11P

4D.12P

4D.13P

5A. 1

5A.2

5A.3

5B. 1

Session 4D (Special Session) University LSI Design Contest Presentation

Chair: Kenji Yoshida Co-chair: Hitoshi Kitazawa HK386: An x86-compatible 32bit CISC Microprocessor

C. M. Kyung, I. C. Park, K. S. Seong, S. J. Lee, H. Choi, S. R. Maeng, D. T. Kim, J. S. Kim, S. H. Park, Y. J. Kang, S. K. Hong, B. S. Kong . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661

Super Low Power 8-bit CPU with Pass-Transistor Logic Kazuo Taki, Bu-Yeol Lee, Hideki Tanaka, Kenzo Konishi . . . . . . . . . . . . . . . . . . . . . . . . 663

A Functional Memory Type Parallel Processor for Vector Quantization K. Kobayashi, M. Kinoshita, M. Takeuchi, H. Onodera, K. Tamaru . . . . . . . . . . . . . . . . 665

High Speed Bit-Serial Parallel Processing on Array Architecture Kazuhito Ito, Takenobu Shimizugashira, Hiroaki Kunieda ....................... 667

Self-timed 1-D ICT Processor Johnson T. C. Pang, Oliver C. S. Choy, C. F. Chan, W. K. Cham . . . . . . . . . . . . . . . . . . 669

A Real-Time High Performance Edge Detector for Computer Vision Applications Fahad Alzahrani, Tom Chen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

An LSI Implementation of the Simple Serial Synchronized Multi-stage Interconnection Network

The RDT Network Router Chip Takayuki Kamei, Masashi Sasahara, Hideharu Amano ......................... 673

Hiroaki Nishi, Hideharu Amano , Katsunobu Nishimura, Ken-ichiro Anjo, Tomohiro Kudoh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675

Joon-Seo Yim, Hee-Choul Lee, Tae-Hoon Kim, Bong-I1 Park, Chang-Jae Park, In-Cheol Park, Chong-Min Kyung . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677

VLSI Implementation of a Real-time Operating System Takumi Nakano, Yoshiki Komatsudaira, Akichika Shiomi, Masaharu Imai . . . . . . . . . 679

A CMOS Delayed Locked Loop (DLL) for Reducing Clock Skew to Under 5OOps Yong-BinKim,Tom W.Chen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681

A Current Mode Cyclic A/D Converter with a 0.8pm CMOS Process

A Current-mode, 3V, 20MHz, 9-bit Equivalent CMOS Sample-and-Hold Circuit

Single Cycle Access Cache for the Misaligned Data and Instruction Prefetch

Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru ........................... 683

Yasuhiro Sugimoto, Tetsuya Iida . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685

Session 5A Co-Design: Architecture and Partitioning

Chair: Stan Krolikoski Co-chair: Kazutoshi Wakabayashi Hardware-Software Co-Design: Tools for Architecting Systems-On-A-Chip (Embedded Tutorial)

Trade-off Evaluation in Embedded System Design via Co-simulation RajeshK.Gupta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

Claudio Passerone, Lucian0 Lavagno,Claudio Sunso&, Massimiliano Chiodo , Alberto Sangiovanni-Vincentelli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

A Transformational Codesign Methodology Tommy King-Yin Cheung, Graham Hellestrand, Prasert Kanthamanon . . . . . . . . . . . . 299

Session 5B HierarchicaVHigh-Level Testing

Chair: Chauchin S u Co-chair: Terumasa Hayashi A Testability Analysis Method for Register-Transfer Level Descriptions

Mizuki Takahashi, Ryoji Sakurai, Hiroaki Noda, Takashi Kambe . . . . . . . . . . . . . . . . . 307

xxvii

5B.2

5B.3

5B.4S

5B.5S

5C.2

56.3

5c.4

6A. 1

6A. 2

6A.3S

6A.4S

1 Non-Scan Design for Testable Data Paths Using Thru Operation

Block-Level Fault Isolation Using Partition Theory and Logic Minimization Techniques

Katsuyuki Takabatake, Toshimitsu Masuzawa, Michiko Inoue, Hideo Fujiwara . . . . . 313

C.-J.RichardShi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 The Use of Hierarchical Information to Test Large Controllers I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F.Fummi,D.Sciuto 325 ~

Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

Hierarchical Fault Tracing for VLSI Sequential Circuits from CAD Layout Data in the CAD-Linked EB Test System k

Session 5C Technology Related Issues

Chair: Kenji Taniguchi Co-chair: Hiroshi Matsumoto Monte Carlo Simulation for Single Electron Circuits

Parallel Calculation of 3-D Parasitic Resistance and Capacitance with Linear Boundary Elements

Simulation of Gate Switching Characteristics of a Miniaturized MOSFET based on a Non-Isothermal Non-Equilibrium Transport Model

Masaharu Kirihara, Kenji Taniguchi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

Wenming Zhou, Zeyi Wang, Lan Rao . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Won-Cheol Choi, Hirobumi Kawashima, Ryo Dang . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

Session 5D (Special Session) Multiproject Chip (MPC) Services for University and Industry

Organizers: Hideharu Amano, Tokinori Kozawa Chair: Kazuhiro Ueda Presented by “The EUROPRACTICE MPC Service”

“Multi-Project Chip Activities in Korea -IDEC Perspective -”

“Multi-Project Chip Service for University and Industry in Taiwan”

“VLSI Design and Education Center (VDEC) Current Status and Future Plan”

CarlDas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

Chong-Min Kyung, In-Cheol Park, Ho-Jun Song . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

Jen-Sheng Hwang . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

Kunihiro Asada, Koichiro Hoh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

Session 6A Simulation Environment

Chair: Alee Stanculescu Co-chair: Fumiyasu Hirose Choosing a Digital Simulator

JohnHillawi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 A Hardware/Software Co-simulation Environment for Micro-processor Design with HDL Simulator and OS Interface

VIDE: A Visual VHDL Integrated Design Environment

Advanced Processor Design Using Hardware Description Language AIDL Takayuki Morimoto, Kazushi Saito, Taisuke Boku, Hiroshi Nakamura, Kisaburo

Yoshiyuki Ito, Yuichi Nakamura . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

Jinian Bian, Hongxi Xue, Ming S u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

Nakazawa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

xxviii

6B. 1

6B.2S

6B.3S

6B.4S

6B.5S

6C. 1

6C.2

6C.3S

6C.4S

7A. 1

7A.2

7A.3

Session 6B Circuit Evaluation for Testability and Power Consumption

Chair: Sunil D. Sherlekar Co-chair: Yukiya Miura Adaptive Models for Input Data Compaction for Power Simulators

Fuzzy-based Circuit Partitioning in Built-in Current Testing

Reducing the Complexity of Path Classification by Reconvergence Analysis

Modeling and Detection of Dynamic Errors due to Reflection- and Crosstalk-Noise

Fault Coverage Improvement Based on Error Signal Analysis

Radu Marculescu, Diana Marculescu, Massoud Pedram . . . . . . . . . . . . . . . . . . . . . . . . . 39 1

Wang-Dauh Tseng, Kuochen Wang . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

Paul Tafertshofer, Andreas Ganz , Manfred Henftling ........................... 401

JurgenSchrage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

Mike W. T. Wong, Y. S. Lee, Yingquan Zhou, Yinghua Min . . . . . . . . . . . . . . . . . . . . . . . 409

Session 6C Circuit Design and Methodology

Chair: James B. Kuo Co-chair: Hidetoshi Onodera Low-Power Multiple-valued Current-Mode Integrated Circuit with Current-Source Control and Its Application

Takahiro Hanyu, Satoshi Kazama , Michitaka Kameyama ....................... 413 Analysis and Design of Multiple-Bit High-Order C - A Modulator

Hao-Chiao Hong, Bin-Hong Lin, Cheng-Wen W u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 Optimal Loop Bandwidth Design for Low Noise PLL Applications

Kyoohyun Lim, Seunghee Choi, Beomsup Kim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 k 1.5V CMOS Four-Quadrant Multiplier

SimonC.Li . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

Organizer: Moderator: Panelists:

Session 6D (Panel Discussion) Collaboration between University and Industry

Tokinori Kozawa Tokinori Kozawa Ralph Cavin, Paul S i x , Taro Okabe, Akihiko Morino, Hiroto Yasuura, Youn-LongLin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

Session 7A High-Level Synthesis Techniques for FPGA’s and Regular Arrays

Chair: David Skellern Co-chair: Akira Nagoya ChipEst-FPGA A Tool for Chip Level Area and Timing Estimation of Lookup Table Based FPGAs for High Level Applications

MinXu,FadiJ.Kurdahi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 Bit-Serial Pipeline Synthesis and Layout for Large-scale Configurable Systems

Tsuyoshi Isshiki, Hiroaki Kunieda, Wayne Wei-Ming Dui ........................ 441 An Optimal Scheduling Method for Parallel Processing System of Array Architecture

Kazuhito Ito, Tadashi Iwata, Hiroaki Kunieda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

xxix

7B. 1

7B.2

7B.3S

7B.4S

7C. 1

7C.2

7c.3

8 A ~ 1

8A. 2

8A. 3

8A.4

8B. 1

8B.2

8B.3

Session 7B Decision Diagrams and Their Applications

Chair: G. Venkatesh Co-chair: Shinji Kimura AQUILA: An Equivalence Verifier for Large Sequential Circuits

On the Representational Power of Bit-Level and Word-Level Decision Diagrams

Learning Heuristics for OKFDD Minimization by Evolutionary Algorithms

On Properties of Kleene "DDs

Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen . . . . . . . . . . . . . . . . . . . . . . . . . 455

Bernd Becker, Rolf Drechsler, Reinhard Enders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

Nicole Gockel, Rolf Drechsler, Bernd Becker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469

Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura . . . . . . . . . . . . . . . . . . . . . . . . . . 473

Session 7C Circuit Analysis and Simulation

Chair: Beomsup Kim Co-chair: Yasuaki Inoue A Time-Domain Method for Numerical Noise Analysis of Oscillators

A New Linear-Time Harmonic Balance Algorithm for Cyclostationary Noise Analysis in RF Circuits

J.S. Roychowdhury, P. Feldmann . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 Enhancement of Parallelism for Tearing-based Circuit Simulation

Koutaro Hachiya, Toshiyuki Saito, Toshiyuki Nakata, Norio Tunabe . . . . . . . . . . . . . . 493

Makiko Okumura, Hiroshi Tanimoto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Session 7D (Tutorial) Processor-Core Based Design and Test

PeterMarwedel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

Session 8A Estimation from High-LeveVRTL Descriptions

Chair: Rajesh K. Gupta Co-chair: Toshihiro Hattori Architecture Evaluation Based on the Datapath Structure and Parallel Constraint

A Constructive Method for Data Path Area Estimation During High-Level VLSI Synthesis

RT Level Power Analysis

Statistical Design of Macro-models For RT-level Power Evaluation

Masayuki Yamaguchi,Akihisa Yamada, Toshihiro Nakaoka, Takashi Kambe . . . . . . . 503

V. Natesan, Anurag Gupta, Srinivas Katkoori, Dinesh Bhatia, Ranga Vemuri . . . . . . . 509

Jianwen Zhu, Poonam Agrawal, Daniel D. Gajski . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

Qing Wu, Chihshun Ding, Chengtah Hsieh, Massoud Pedram . . . . . . . . . . . . . . . . . . . . 523

Session 8B Logic Synthesis and Modeling

Chair: Yosinori Watanabe Co-chair: Hiroyuki Ochi AND/OR Reasoning Graphs for Determining Prime Implicants in Multi-Level Combinational Networks

Efficient Synthesis of ANDBOR Networks

An Optimization of AND-OR-EXOR Three-Level Networks

Dominik Stoffel, Wolfgang Kunz, Stefan Gerber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

Yibin Ye, Kaushik Roy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

Debatosh Debnath, Tsutomu Sasao . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545

XXX

8B.4

8C. 1

8C.2

8C.3

8C.4

9A. 1

9A.2

9A. 3

9B. 1

9B.2

9B.3

A New Description of CMOS Circuits at Switch-Level Massoud Pedram, Xunwei W u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

Session 8C Module Generation and FPGA Layout

Chair: Xianl ong Hong Co-chair: Hitoshi Kitazawa A Two-dimensional Transistor Placement for Cell Synthesis

DP-Gen: A Datapath Generator for Multiple-FPGA Applications

A Simultaneous Placement and Global Routing Algorithm with Path Length Constraints for Transport-Processing FPGAs

Not Necessarily More Switches More Routability

Shunji Saika, Masahiro Fukui, Noriko Shinomiya, Toshiro Akino . . . . . . . . . . . . . . . . . 557

Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen, Tsair-Chin Lin .................... 563

Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569

Yu-Liang Wu, Douglas Chang, Malgorzata Marek-Sadowska, Shuji Tsukiyama . . . . . 579

Session 8D (Panel Discussion) Design Standardization for 2001

Organizer: Hisakazu Edamatsu Moderator: Hitoshi Yoshizawa Invited talk “The SEMATECH Chip Hierarchical Design System - New Paradigms for Deep Submicron Design”

Gregory Ledenbach Panel Panelists: Steven L. Glaser, Andrew Graham, Klaus ten Hagen, Gregory Ledenbach,

“The Role of Design Standaradization in Future Complex Design”

Tadahiko Nakamura, Yoshihide Sugiura . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

Session 9A Aspects of Hardware and Software Synthesis

Chair: Graham R. Hellestrand Co-chair: Toshiaki Miyazaki On the Control-subroutine Implementation of Subprogram Synthesis

A Procedure for Software Synthesis from VHDL Models

Built-in Chaining: Introducing Complex Components into Architectural Synthesis

Cheng-tsung Hwang, Hsiao-Chien Weng, Yu-Chin Hsu, Mike Tien-Chien Lee . . . . . . . . 587

Venkatram Krishnaswamy, Rajesh Gupta, Prithviraj Banerjee . . . . . . . . . . . . . . . . . . . 593

Peter Marwedel, Birger Landwehr, Ruiner Domer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599

Session 9B Sequential Synthesis

Chair: Nachiket Urdhwareshe Co-chair: Hitomi Sat0 BDD-based Logic Partitioning for Sequential Circuits

Cube-Embedding Based State Encoding for Low Power Design

On Synthesis of Speed-Independent Circuits at STG Level

Ming-Ter Kuo, Yifeng Wang, Chung-Kuan Cheng, Masahiro Fujita . . . . . . . . . . . . . . . . 607

De-Sheng Chen, Majid Sarrafzadeh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

Kuan- Jen Lin, Chi- Wen Kuo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

xxxi

Session 9C Theoretical Aspects of Layout Design

Chair: Chong-Min Kyung Co-chair: Atsushi Takahashi A Mapping from Sequence-Pair to Rectangular Dissection

H. Murata, K. Fujiyoshi, T. Watanabe, Y. Kajitani . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 Solving Constrained Via Minimization by Compact Linear Programming

C.-J.RichardShi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 Efficient Routability Checking for Global Wires in Planar Layouts

Naoyuki Iso, Yasushi Kawaguchi, Tomio Hirata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 Topological Routing Path Search Algorithm with Incremental Routability Test

Toshiyuki Hama, Hiroaki Etoh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

9c . 1

9C.2

9c .3s

9c .4s

Session 9D (Tutorial) VHDL Analog and Mixed-Signal Extensions Through Examples

AlainVachoux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649

xxxii