Image Topic: o Nam elementum commodo mattis. Pellentesque malesuada blandit euismod. Topic: o Nam elementum commodo mattis. Pellentesque malesuada blandit euismod. o Nam elementum commodo mattis. Pellentesque malesuada blandit euismod. Topic: o Nam elementum commodo mattis. Pellentesque malesuada blandit euismod. TITLE CEI-112G: THE NEXT WAVE OF ELECTRICAL INTERFACES Nathan Tracy, TE Connectivity Ed Frlan, Semtech Tom Palkert, MACOM Brian Holden, Kandou Bus
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TITLE
CEI-112G: THE NEXT WAVE OF ELECTRICAL INTERFACES
Nathan Tracy, TE ConnectivityEd Frlan, SemtechTom Palkert, MACOMBrian Holden, Kandou Bus
� CEI IA is a clause-based format supporting publication of new clauses over time:� CEI-1.0: included CEI-6G-SR, CEI-6G-LR, and CEI-11G-SR clauses.� CEI-2.0: added CEI-11G-LR clause� CEI-3.0: added work from CEI-25G-LR, CEI-28G-SR � CEI-3.1: added work from CEI-28G-MR and CEI-28G-VSR
� CEI-11G and -28G specifications have been used as a basis for specifications developed in IEEE 802.3, ANSI/INCITS T11, and IBTA.� CEI 56G projects are in progress:
� LR: backplane� MR: chip to chip� VSR: chip to module� XSR: chip to optics engine (separate chips)� USR: chip to optics engine (2.5D or 3D package)
� ….. or, channels need to be shorter; optics must get closer to the host switch
� Likely a combination of all the above will be required
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QUESTIONS?
Thank you!
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TITLE
CEI-112G: Considering Electrical Channels
Nathan Tracy, TE ConnectivityOIF Board Member and Marketing VP
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VSR - Connecting Chips to Modules - Typical Reach up to 10”
LR - Channels in Chassis - Typical Reach = 1m
4-10”, PWB trace
Connector with footprint0.7-1.5”, PWB trace
• ~1m of improved PWB• 2 backplane connectors
• 0.5m of PWB• 1 orthogonal connector
• 14” of improved PWB• 1m of cable• 2 cable backplane connectors
Channels Considered for this Discussion
• Used 25G (published) and 50G (in development) OIF and IEEE industry standards as starting point
• Based on the shift towards PAM4 with the transition from 25G to 50G we can assume 100G will likely be PAM4
• Other encoding schemes were not considered but new emerging methods could enable next generation high speed links.
• For 100G the actual data rate will likely be 112GBaud/s with a Nyquist frequency around 28GHz (PAM4)
• The bandwidth of interest is assumed to be 10MHz – 56GHz• The Insertion Loss/Return Loss requirements were extrapolated using a
combination of,– Historical trends in data rate leaps, using current 50G targets as reference– Successful demonstrations of actual channels at 50G (PAM4 and NRZ)
Conclusions:• Passes up to the Nyquist frequency but may be impractical lengths • Footprint is critical. FP causes significant degradation beyond 33GHz
23
4”, PWB trace0.7” PWB trace
Megtron6EM888
Improved Connector with footprint
Meg6 provides 2” of additionaltrace on DC
Shorter VSR Channels
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2”, PWB trace
Board mounted cable connector
18” of 33 AWG cableOR
23” of 30 AWG Cable
Improved Connector with footprint
0.7” PWB trace
Conclusions:• Passes up to the Nyquist frequency with margin• Utilizing cable provides extended reach and flexibility
Megtron6, Typical FPMegtron6, Short FP
- 3.5mm thick- 8mil stub- Long via barrel
Using Cables to Extend Channel Length
25
14.00
GHz
12.50
GHz
11.00
GHz
9.500
GHz
8.000
GHz
6.500
GHz
5.000
GHz
3.500
GHz
2.000
GHz
500.0
MHz
0
-2
-4
-6
-8
-10
FREQ
dB
B2_T0B2_EOL
Variable
PCB T0 vs. EOL VarianceSDD21- PCB B2
1250011000950080006500500035002000500
0
-2
-4
-6
-8
-10
Freq (MHz)
dB
Pair 14-15_cable1_1Pair 14-15_cable1_after
Variable
Whisper T0 vs. EOL VarianceSDD21 Pair 14-15
T0 vs EoL: Temperature/Humidity cycling per EIA-364-31 Method III200mm PWB Megtron 6 traces vs. 500mm twinax cable assemblies
Ideal mating zone & short footprintRealistic mating zone & short footprintIdeal mating zone & typical footprint (thick board with 8mil stub)Realistic mating zone & typical footprint (thick board with 8mil stub)
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4”, PWB trace0.7” PWB trace
VSR Sensitivity to Connector Design
29
Cable termination Impedance varied +/- 10%
Nominal+/-10% Impedance
- Excess solder paste- Inaccurate cable placement - Stripping of signal insulation and shield- Manufacturing control is critical
Example dies to connect with the Logic-Logic application
KANDOU BUS
Logic-Driver application
KANDOU BUS
� Five key questions exist for each application:
1. Use DC or AC coupling (or on-die only AC coupling) in order to support a Silicon-to-SiGe (or III-V) connection
2. Use a shared forwarded clock or use Clock-Data Recovery (CDR)
3. Rely on the FEC of the I/O subsystem or not4. Require pair orientation or not5. Use CNRZ-5 or PAM-4 for the modulation technique
o .
Key questions for the CEI-112G in MCM interface
KANDOU BUS
� Logic-Logic: – Wants to have DC coupling to minimize the area required and
signal integrity impairment produced by AC coupling.
– It also wants to save power by not using a line code and scrambling.
� Logic-Driver:– Often requires AC coupling to marry the common-mode
voltage levels of devices made from very different semiconductor processes such as SiGe or GaAs.
– A compromise is to restrict the AC coupling to on-die AC coupling.
DC or AC Coupling
KANDOU BUS
� Logic-Logic: – Since Logic-Logic applications are almost always outside of the
I/O subsystem and use packet mechanisms, there are no relevant line clocks to work with.
• Power can be saved by using a shared forwarded clock
� Logic-Driver:– With the rise of 25GE and the future single lane 50GE & 100GE,
for VSR the incoming clocks on the different lanes can be different since the links can come from different chassis.
• This makes it inconvenient to use a shared forwarded clock when those multiple clocks have to be carried, so CDR is a more universal choice
• Intra-system uses can often use a shared forwarded clock
Shared Forwarded Clock or CDR
KANDOU BUS
� Logic-Logic: – Are typically outside of the I/O subsystem and thus cannot rely
on its Forwarding Error Correcting block. – Often use credit-based flow control that cannot tolerate a high-
latency FEC
� Logic-Driver:– The location w.r.t. the I/O subsystem can be mixed. The lanes
bound for outside of the system are protected by the FEC, but intra-system lanes may not be.
� Both applications generally need good native error performance.
FEC or not
KANDOU BUS
� Logic-Logic: – Just wants the most throughput for the least power
• Does not care about pair-orientation.
– Wide packet busses are common.
� Logic-Driver:– Typically wants the data kept within pairs
• The data is often bound for an optical device.
Pair-orientation or not
KANDOU BUS
� Logic-Logic: – CNRZ-5 is an excellent choice given its NRZ-shaped eyes, high
native signal integrity, and low power.
– CNRZ-5’s eyes are ~ 70% wider and 95% taller than those of PAM-4 in the included simulations. Implementations need much less equalization.
� Logic-Driver:– PAM-4 is a good choice to allow a driver device to have the
same modulation on both of its sides.
� NRZ is not likely to be viable for either given its excessive switching speed, which looks to exceed what is possible in silicon
Modulation technique: CNRZ-5 or PAM-4
KANDOU BUS
• 5 bits on 6 wires• 5 comparators
• Ideal for shorter connections including die-to-die interconnect inside a package
• Delivers NRZ shaped eyes at the decision point
• 69.6 GBaud delivers 116 Gb/s equivalent
• 50 GBaud delivers a useful product
CNRZ-5
KANDOU BUS
� Channel– Real 1.2 cm MCM channel, extended
to 100GHz– Uses GX13 substrate (er = 3.1, tandD =
0.019 @ 10GHz)– Assumed 0.4ps skew between wires
• For example, PAM4 uses 2 wires. The skew between the 2 wires is 0.4ps. CNRZ5 uses 6 wires. The skew between every wire and its neighbor is 0.4ps. The total skew across the 6 wires is 2ps
� Noise and jitter– Gaussian noise with std dev of 2mV– Rj (1 sigma) = 1% UI– Dj p-p = 10% UI
