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On Chip Nonlinear Digital Compensation for
RF ReceiverKaren M. G. V. Gettings, Andrew K. Bolstad, Show-Yah Stuart Chen, Benjamin A. Miller
and Michael Vai
HPEC 2011
This work is sponsored by the Department of the Air Force under Air Force contract FA8721-05-C-0002. Opinions, interpretations, conclusions and recommendations are those of the author and are not necessarily endorsed by the United States Government.
System On Chip Equalization
• We designed a nonlinear digital compensation circuitry that is part of a System On Chip (SOC) design
• SOC implementations are an attractive solution for SWaP restricted applications, partly because of targeted design needs
• We exploit the benefits of SOC implementations by co-designing the analog hardware and digital processing
ADC IP core
Frequency Synthesizer
I
QNonlinear Digital
Equalizer
System-on-chip
Homodyne receiver with anti-alias filter
Previous Work:NLEQ Processor
+20~25 dB SFDR/IFDR
@500MHz BW
>1 Teraops
< 2 Watts
In-Band Intermodulation Distortions
Before Equalization
Po
we
r (d
B)
Frequency (bin)
After Equalization
Frequency (bin)
Po
we
r (d
B) Dynamic
range improvement
Song et al., “Nonlinear Equalization Processor IC for Wideband Receivers and Sensors,” HPEC 2009
• Established a low-power standard-cell synthesis design flow– IBM 65 nm CMOS process
• Created an overall compensation architecture customized for our current front end system– Design is optimized to minimize power consumption
Nonlinear Digital Equalizer Design
ii
ip
i hmnxmnxnxny i
5
1,2,1 )()()()(
SFinal Accumulatorshifter
shifter
shifter
shifter
PE1
PE2
PE3
PE4
PE5
Analog Input
shifter
Delay
Offset Binary to Two’s
Complement Conversion
x(n)
x2(n)
x3(n)
x4(n)
Projected Design Performance
• The digital compensation architecture has been synthesized, placed, routed and taped-out – Core size: 200 mm by 200 mm – Simulation results show:
Approximately 10 mW of power at 200 MHz Compensation of front end filter:
15 dB improvement for median dynamic range
15 dB200 mm