March 6, 2008 JST-DFG WSP, A. Toriumi 1
Akira Toriumi
Department of Materials EngineeringThe University of Tokyo
Tokyo, Japan
On the control of GeOOn the control of GeO22/Ge and /Ge and metal/Ge interfaces metal/Ge interfaces
toward metal source/drain Ge CMOStoward metal source/drain Ge CMOS
March 6, 2008 JST-DFG WSP, A. Toriumi 2
New things are not always healthy.New things are not always healthy.
What is a promising candidate for non-Si Materials?We have to take account of not only channel but also contact.
Si CMOSSi CMOS
photon, photon, qbitqbitnonnon--Si MaterialsSi Materials
spin, phasespin, phase
2007 2050gapgap
nonnon--Si MaterialsSi Materials
March 6, 2008 JST-DFG WSP, A. Toriumi 3
Si
Si
SiSi Microelectronics Research will end in 2015.
What is the Problem in Si ?What is the Problem in Si ?
Si microelectronics isin the metabolic syndrome
Requirements for something new Requirements for something new in the next stepin the next step
Material should be simple.Material should be simple.Operation principle should be simple.Operation principle should be simple.Process should be simple.Process should be simple.
SiSi
March 6, 2008 JST-DFG WSP, A. Toriumi 4
1. Background and ObjectiveWhy Ge now ?
2. Ge MISGeO desorption
Ge/GeO2 MIS Capacitors3. Ge Schottky
Fermi-level Pinning
Ohmic contact to n-Ge
4. Ge-CMOSp-MOSFET
n-MOSFET
5. Conclusions
OutlineOutline
March 6, 2008 JST-DFG WSP, A. Toriumi 5
DeviceScalingLow Power
FinFE
T,Q
W
FinFE
T,Q
W
3D Structure3D Structure
MiniaturizationMiniaturization Planar, FD-SOIPlanar, FD-SOI
MaterialsMaterials Ge, III-V, CNT
Ge, III-V, CNT
FinFET
SOI
Si
Ge-FinFET
SiGe Ge
Electron Devices in the Next StepElectron Devices in the Next Step
March 6, 2008 JST-DFG WSP, A. Toriumi 6
1. Background and ObjectiveWhy Ge now ?
2. Ge MISGeO desorption
Ge/GeO2 MIS Capacitors3. Ge Schottky
Fermi-level Pinning
Ohmic contact to n-Ge
4. Ge-CMOSp-MOSFET
n-MOSFET
5. Conclusions
OutlineOutline
March 6, 2008 JST-DFG WSP, A. Toriumi 7
Demand for High Quality GeODemand for High Quality GeO22/Ge Interface/Ge Interface
High-k/Si
GeO2/Ge is thermodynamically unstable.
“high-quality” GeO2/Ge ?
High-k/Ge
SiO2 interface layer is inevitable for good device characteristics.
An appropriate High-k ?
Ge
metal
High-k
GeO2K. Kita et al., APL 85 (2004)
March 6, 2008 JST-DFG WSP, A. Toriumi 8
CC--V Characteristics of GeOV Characteristics of GeO22//SiOSiO22/Si MIS/Si MIS
GeO2 / SiO2 / Si (N2 annealing at 600oC)
GeO2
Si
SiO2 (5nm)
Au
-3 -2 -1 0 1 20.0
0.1
0.2
0.3
0.4
13.4 nm
9.8 nm
4.8 nm
C
apac
itanc
e (μ
F/cm
2 )
Gate Voltage (V)
H. Nomura et al., IWDTF 2007
March 6, 2008 JST-DFG WSP, A. Toriumi 9
CC--V Characteristics of GeOV Characteristics of GeO22 MIS CapacitorsMIS Capacitors
10nm-thick sputtered GeO2 after N2 annealing at 600oC
-3 -2 -1 0 1 20.0
0.2
0.4
0.6
0.8
1.0
on Si
on SiO2/Si
on Ge
N
orm
aliz
ed C
apac
itanc
e (C
/CM
AX)
Gate Voltage (V)
freq.=1MHz
K. Kita et al., ECS Trans. 3 (2007)
March 6, 2008 JST-DFG WSP, A. Toriumi 10
GeO2 (25nm)
Evidence of GeO Volatilization from GeOEvidence of GeO Volatilization from GeO22/Ge/Ge
Thermal desorption spectroscopy (TDS)
400 500 600 700 8000
2
4
6
8
10
GeO from
GeO from
Inte
nsity
(arb
.uni
t)
GeO2/SiO2
GeO2/Ge
Temperature (oC)
Si
GeO2 (25nm)
SiO2 (30nm)
Ge (15nm)
GeO2/Ge
Si
SiO2 (30nm)
GeO2/SiO2
m (GeO) =86,88,89,90
S. Suzuki et al., SSDM 2007
March 6, 2008 JST-DFG WSP, A. Toriumi 11
Suppression of GeO Suppression of GeO DesorptionDesorption by Si Capby Si Cappingping
Si capping layer can suppress GeO volatilization.
Ge
Si (10nm)
GeO2 (25nm)
Si cap layer
0 20 40 60 805
10
15
20
25
30GeO2/GeWITH Si cap
GeO2/GeWITHOUT Si cap
GeO
2 Thi
ckne
ss (n
m)
Annealing Time (sec)N2 anneal at 600oC
March 6, 2008 JST-DFG WSP, A. Toriumi 12
Dramatic Improvement of GeODramatic Improvement of GeO22/Ge MIS /Ge MIS Characteristics with CapCharacteristics with Cappingping LayerLayer
(~25nm-thick GeO2,after N2 600oC anneal)
(1MHz)
-6 -4 -2 0 2 4 60.00
0.05
0.10
0.15
0.20
GeO2/Ge withConventional PDA
GeO2/Ge withNiSix Cap
C
apac
itanc
e (μ
F/cm
2 )
Gate Voltage (V)
S. Suzuki et al., SSDM 2007
March 6, 2008 JST-DFG WSP, A. Toriumi 13
1. Background and ObjectiveWhy Ge now ?
2. Ge MISGeO desorption
Ge/GeO2 MIS Capacitors3. Ge Schottky
Fermi-level Pinning
Ohmic contact to n-Ge
4. Ge-CMOSp-MOSFET
n-MOSFET
5. Conclusions
OutlineOutline
March 6, 2008 JST-DFG WSP, A. Toriumi 14
Strong FermiStrong Fermi--level Pinning at Metal/Gelevel Pinning at Metal/Ge
Metal/Ge
CB
VB
0
3
4
5
6Ene
rgy
leve
l fro
m v
acuu
m le
vel (
eV)
ErErYYbb
ZrZr
Metal
La,ScLa,ScHfHf
AlAl
AuAu
PPtt
NiNi
TiTi
YY
Vacuum Level
Metal/Si
CB
VB
Metal/Ge
CB
VB
0
3
4
5
6Ene
rgy
leve
l fro
m v
acuu
m le
vel (
eV)
ErErYYbb
ZrZr
Metal
La,ScLa,ScHfHf
AlAl
AuAu
PPtt
NiNi
TiTi
YY
Vacuum Level
Metal/Si
CB
VB
Metal/Si
CB
VB
T. Nishimura et al., APL (2007)
EG(Ge)EG(Si)
1) Metal source/drain2) Low ohmic contact
resistance
p-Gen+
March 6, 2008 JST-DFG WSP, A. Toriumi 15
1. Forming gas annealingMetal: Al
(annealing temp. 200~500ºC)
2. Germanide reactionMetal: Er, Ni
(annealing temp. 200~500ºC)
3. Substrate orientationMetal: Ni(Orientation:(100), (110), (111))
Interface Modulation EffectsInterface Modulation Effects
5
4
30
VB
Eff
ectiv
e w
ork
func
tion
(eV
)
CB
● without modulation■ with modulation
vacuum metal WF
Al
Er
Ni Ni
Y
Al
AuFG MGex Sub. GeOx
(110)(111)(100)
Ev
Ec
March 6, 2008 JST-DFG WSP, A. Toriumi 16
Ge(100)
NiGe
XTEM of NiGe/Ge(100) InterfaceXTEM of NiGe/Ge(100) Interface
Still Strong Fermi level Pinning even after Reaction
March 6, 2008 JST-DFG WSP, A. Toriumi 17
Metal dependent VFB
-3 -2 -1 0 10.0
0.2
0.4
0.6
0.8
1.0
Cap
acita
nce
(μF/
cm2 )
Gate Voltage (V)
Al
Au
Metal
Ge
Al2O3
1MHz
Unpinned Ge MIS CapacitorUnpinned Ge MIS Capacitor
No Fermi Level Pinning thanks to Insulator InsertionNo Fermi Level Pinning thanks to Insulator Insertion
Al2O3 5nm
March 6, 2008 JST-DFG WSP, A. Toriumi 18
Possible Origin of FermiPossible Origin of Fermi--level Pinninglevel Pinning
Metal-induced Gap States (MIGS) Formation
Metal wave function penetrationGe intrinsic properties
CBE
VBEGe
ScalcSexp
0.02 0.04***
***W. Monch; JVST. B 17 (1999) 1867.
Ge 4.63**4.58 eV 4.48*
Branch PointCNL (This work)
*J. Tersoff; PRL 32 (1984) 465.**M. Cardona and N. Christensen; PRB 35 (1987) 6182.
CNL
T. Nishimura et al., APL (2007)
March 6, 2008 JST-DFG WSP, A. Toriumi 19
-1 0 1
0.3 nm
V (V)
w/o
-1 0 110-4
10-2
100
1020.3 nm
Cur
rent
(A/c
m2 )
V (V)
w/o
n-Ge p-Ge
GeAl Ultra-thin
Al2O3GeAl
-1 0 10
20
40
-1 0 10
20
40
II--VV Characteristics Characteristics @Al/Ge@Al/Ge
T. Nishimura et al., submitted.
-1 0 10
20
40
-1 0 10
20
40
March 6, 2008 JST-DFG WSP, A. Toriumi 20
1. Background and ObjectiveWhy Ge now ?
2. Ge MISGeO desorption
Ge/GeO2 MIS Capacitors3. Ge Schottky
Fermi-level Pinning
Ohmic contact to n-Ge
4. Ge-CMOSp-MOSFET
n-MOSFET
5. Conclusions
OutlineOutline
March 6, 2008 JST-DFG WSP, A. Toriumi 21
-1.0 -0.5 0.00
5
10
15
20
0 V-0.2 V
-0.4 V
I s (μA
)
Vds (V)
Vgs-Vth = -0.8 V
-0.6 V
W/L=530 μm/ 190 μmp-MOSFET GeO2
-1.0 -0.5 0.00
5
10
15
20
0 V-0.2 V
-0.4 V
I s (μA
)
Vds (V)
Vgs-Vth = -0.8 V
-0.6 V
W/L=530 μm/ 190 μmp-MOSFET GeO2
Metal source/drainMetal source/drain pp--chch Ge MOSFETGe MOSFET
n-GePtGe
FUSILYO or GeO2
n-GePtGe
FUSIGeO2
Metal source/drain p-ch Ge(100) MOSFET
No Impurity Doping ! T. Takahashi et al., iedm2007
March 6, 2008 JST-DFG WSP, A. Toriumi 22
[1] P. Zimmerman et al., IEDM 2006, 655, [2] W. Zhu et al., IEEE Trans. on Electron Devices 51, 98 (2004)
Inversion Hole mobility of Ge MOSFETInversion Hole mobility of Ge MOSFET
GeO2 /Ge
LaYO3 /Ge
w/o correction
w/o correction
SiO2 /Si
0.0 5.0x1011 1.0x1012 1.5x10120
100
200
300
400μ h(cm
2 /Vs )
Ns ( /cm2 )
peak mobilityw/ corr.
[2]
GeO2 /Ge(this work)[1]
GeO2 /Ge
LaYO3 /Ge
w/o correction
w/o correction
SiO2 /Si
0.0 5.0x1011 1.0x1012 1.5x10120
100
200
300
400μ h(cm
2 /Vs )
Ns ( /cm2 )
peak mobilityw/ corr.
[2]
GeO2 /Ge(this work)[1]
GeO2 /Ge
LaYO3 /Ge
w/o correction
w/o correction
SiO2 /Si
0.0 5.0x1011 1.0x1012 1.5x10120
100
200
300
400
GeO2 /Ge
LaYO3 /Ge
w/o correction
w/o correction
SiO2 /Si
0.0 5.0x1011 1.0x1012 1.5x10120
100
200
300
400μ h(cm
2 /Vs )
Ns ( /cm2 )
peak mobilityw/ corr
μ h(cm
2 /Vs )
Ns ( /cm2 )
peak mobilityw/ corr.
[2]
GeO2 /Ge(this work)[1]
GeO2 /Ge
LaYO3 /Ge
w/o correction
w/o correction
SiO2 /Si
0.0 5.0x1011 1.0x1012 1.5x10120
100
200
300
400 .
[2]
GeO2 /Ge(this work)[1]
GeO2 /Ge
LaYO3 /Ge
w/o correction
w/o correction
SiO2 /Si
0.0 5.0x1011 1.0x1012 1.5x10120
100
200
300
400μ h(cm
2 /Vs )
Ns ( /cm2 )
μ h(cm
2 /Vs )
Ns ( /cm2 )
peak mobilityw/ corr.
[2]
GeO2 /Ge(this work)[1]
March 6, 2008 JST-DFG WSP, A. Toriumi 23
Metal Source/DrainMetal Source/Drain Ge nGe n--FETsFETs
p-GeAl
AuGeO2
p-GeAl
AuGeO2
p-GeAl
AuGeO2
T. Takahashi et al., iedm2007
Schottky-Ohmic conversion with ultra-thin GeOx No Impurity Doping !
0.0 0.5 1.00
-5
-10
-15
-0.2 V0 V0.2 V
0.4 V
I s (μA
)
Vds (V)
Vgs-Vth = 0.6 VW/L=530 μm/ 190 μm
n-MOSFET GeO2
10 nm
AlGeOx(~2 nm)
Ge
March 6, 2008 JST-DFG WSP, A. Toriumi 24
1. Background and ObjectiveWhy Ge now ?
2. Ge MISGeO desorption
Ge/GeO2 MIS Capacitors3. Ge Schottky
Fermi-level Pinning
Ohmic contact to n-Ge
4. Ge-CMOSp-MOSFET
n-MOSFET
5. Conclusions
OutlineOutline
March 6, 2008 JST-DFG WSP, A. Toriumi 25
ConclusionsConclusions
Origin of deterioration in GeO2/Ge MIS is due to GeO desorption.
GeO2/Ge MIS can be dramatically improved by suppressingGeO volatilization with NiSi cap layer.
Origin of FLP at Metal/Ge is attributable to metal-induced gap states (MIGS).
Ultra-thin dielectric film insertion into metal/Ge can shift MIGS-related CNL.
Metal source/drain Ge CMOS is coming soon.