On the Horizon: Semiconductor Packaging Trends, Challenges and

Innovations

Dr. Mahadevan "Devan" Iyer Director of WW SC Packaging

Texas Instruments

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Outline

• Semiconductors are at the center of a new era

• Packaging’s  role  in  product  differentiation

• Emerging low power applications

• Packaging trends and challenges

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Digital Cameras & Camcorders

Multimedia Players

Video Conferencing &

Surveillance TV &STB

Communication Infrastructure

Gateway, Router & Switch

Medical Electronics

Industrial Motor Control, ATE &

Automation

Automotive Entertainment, NAV &

Vision

Communication Peripherals

IP Phones, PoE & WAPs

Digital Radio & Audio

Mobile Phones Computing

Semiconductors enable great new products

Growing Internet of Things requires personalization, connectivity

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1960s 1970s 1980s 1990s 2000s 2010s

$1B

$1000B

$100B

$10B

Total SC Market

Mainframe Transistors

Minicomputer TTL/Logic

Personal Computers

Microprocessor

1 device: thousands of people

1 device: hundreds of people

1 device: 1 person

Transportation

• Auto electronic power steering

• Smart cars • Automatic parking, pilot

Quality of Life

• Smart houses • Remote/home healthcare • Wireless connectivity • Lower cost/higher feature

mobile phones

Security

• Health monitoring connection to home security

• Electronics  that  “know”  the  user   • Enhanced use of video • Intelligent cameras

Education

• Remote learning • Mobile access to Web

Analog & Embedded Processing 10 devices: 1 person

Cell phone multimedia appliance

CD digital entertainment

We are at the center of a new era

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New markets New applications New solutions to old applications

Analog and embedded processing are key drivers

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Packaging enables convergence of products

Smart Phones & Mobile Internet Devices

Intelligent and Autonomous Cars

Lab on Chip

Portable Medical Imaging Devices

System Integration

Needs

Integration and Miniaturization

enabling systems

TI Information: Selective Disclosure 1990 2000 2010 2020

1ML-CSP

MCM

DIP

PLCC

PGA

TAB

QFP

BGA

BGA

SO TQFP

Hi-Perf BGA

Hi Perf PGA

ML-CSP

WSP

SIP

POP1

SON

HTQFP

QFN

FC CSP/POP

FC CSP

POP2

FC SiP/POP2

HiCTE Ceramic

Embedded Si

F2F

TSV

RFID

Enab

ling

te

chno

logi

es

Syst

em a

pplic

atio

ns

Prim

ary

Pack

age

Plat

form

s

DIP, PGA, PLCC, QFP SMT

BGA, u*BGA, CSP, FC BGA Bump, Flip Chip interconnect

Thermal management

Stacking die, Wafer thinning Au-stud FC, POP, FC CSP,

WSP, SON, QFN

FC BGA

Embedded Si, Face-to-Face interconnect, bio-compatible

Materials& packaging , ultra-thin, Thru Si via, substrateless pkg

Packaging technology trends reflect applications and end equipments

Embedded Si

SD/MCM QFN

FC QFN (HoTRoD)

MRQFN Chip-on-MEMs

Sub Systems Integration

Passives Integration

100’s

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Thin is in QFN 1 mm

Thin QFN 0.8 mm

WCSP (NanoStar) 0.6/0.5 mm

X-QFN 0.4 mm

PicoStar 0.15/0.1 mm

SOIC 1.75 mm

TWCSP 0.4/0.3 mm

MicroStar 1 mm

U*CSP 0.45mm

TSSOP 1.2 mm PicoStar-2G

0.075mm

Invisible to naked eye ~0.04 mm

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Package family proliferation

Each  package  type  has  a  “sweet  spot”  combination  of  cost, performance, form factor and reliability, driven by: • Cost • Electrical speed, power distribution and noise immunity • Power dissipation • Thickness, weight, PCB area consumption • Board level reliability (BLR, drop) • Environmental reliability • Technical maturity vs. risk in high-volume manufacturing • Testability • Compatibility with Si process

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Packaging challenges: Materials & assembly

• Low stress M/C & D/A, right adhesion promoters for LF & MC, Surface finishes of LF

• Low stress underfills to support finer pitch bumps. • Right flow of properties to meet high through put

requirements in manufacturing, CTE, Tg & Modulus selection for FC bonding

• Cost effective high yielding organic substrates with finer LW/LS.

• Coreless substrates to support advanced 3D packages

• Finer pitch interconnections (Finer pitch FC, Solder Bump FC, Au & Cu wire)

• High accuracy, high throughput finer pitch FC bonding

MC, D/A, LF

Underfills

Substrates

Interconnect & assembly

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Role of IC package materials

There is increasing pressure for package materials to meet these requirements in performance applications

IC package materials must: Be cost neutral - Be electrically invisible - Provide thermal management - Enable device integration

Electrical Interconnection Structure Supporting Indirect Materials

Performance Devices

Device Protection Reliability Heat Dissipation Processing

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• 3D integration in Power Packaging is a critical element to creating a strong value proposition

− Reduced parasitics and noise − Improved power density and thermals − Significant ease of use − Superior solution reliability and cost

• Future integration − High voltage − Isolation − High accuracy current sensing − Integrated magnetics

Electrical Performance

Thermal Performance

Power Density

Cost

Reliability

Ease of Use

Increased functionality

Market demands

Power packaging and integration plays an increasingly important role.

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Every application needs power

Power management optimizes system performance: efficiency, responsiveness and reliability

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Battery Management

Power Supply Control Point-of-Load Portable Power

Conversion

TI: Power management for any application

• Chargers, gauges and protection for EVERY application

• Battery life

• Support for any battery chemistry

• State-of-health

• Power converters, backlighting, PMICs, power for power amplifiers

• Extend battery run-time

• High conversion efficiency

• Integration

• AC/DC converters, power factor, protection, digital power controllers

• Energy efficiency

• Intelligent control

• DC/DC, voltage regulators, protection circuits

• High-voltage POL

• System protection

• Low noise

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Reduction of package parasitics

Improved thermal management and PCB layout

Power density: PowerStack™  

ControlFET

SyncFET

Input Supply

LO

ILCO

Load

Driver

CINPUT

Switch Node

CESR

CESL

RPCB

LDRAIN

LSOURCE

PWM

Driver

LDRAIN

LSOURCE

CTOTAL

X

X X

HS FET

LS FET IC

HS FET CLIP

LS FET CLIP

• Stacked NexFET™  ,  ~  2X  greater  power density

• Low resistance Cu clips, ~ 30% lower power loss

• Ability to optimize and deliver higher efficiency

• Single grounded DAP

• Simple PCB layout for optimized performance

Package impact can be = to two generations on silicon

improvement!

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• Telecom, industrial trends: – Higher current levels – Greater power density, efficiency

• 25-A step-down converters with integrated NexFET™   – Highest power density,

smallest package – Smallest total footprint – Highest efficiency (>90%) – Ease of use – Qualified in multiple fabs and

assembly/test sites

• Differentiated by: – Process technology – Packaging innovation

Differentiating through technology

High Side Clip High Side NexFET

Low Side Clip

DC/DC Controller

Lead Frame

Low Side NexFET

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• Advancements in packaging deliver differentiation, and a broad range of solutions are required

• Materials and assembly processes are interlinked and play a major role in addressing next-gen challenges

• 3D integration in Power Packaging is a critical element to creating a strong value proposition

Summary