Cadence Op-Amp Schematic Design Tutorial forTSMC CMOSP35Till Kuendiger, Joseph Schrey, Iman Taha, Yi Lin,Tao Dai, Li Liang, Song-Tao Huang, Yue HuangDecember 7, 2001ContentsPreface iv1 Introduction 11.1 Review of CMOS FETs . . . . . . . . . . . . . . . . . . . . . 11.2 Creating a New Library in Cadence . . . . . . . . . . . . . . . 21.3 Schematic Capture . . . . . . . . . . . . . . . . . . . . . . . . 41.3.1 Virtuoso Schematic Editor . . . . . . . . . . . . . . . . 41.3.2 Virtuoso Symbol Editor . . . . . . . . . . . . . . . . . 51.3.3 Arma Analog Circuit Design Environment . . . . . . 61.3.4 The Waveform Window . . . . . . . . . . . . . . . . . 71.3.5 The Cadence Calculator . . . . . . . . . . . . . . . . . 81.4 Generating the Characteristic MOSFET Curves . . . . . . . . 91.4.1 N-channel Enhancement-Type MOSFET . . . . . . . . 91.4.2 P-channel Enhancement-Type MOSFET . . . . . . . . 142 An Introduction to Op-Amps 172.1 Parameters of an Op-Amp . . . . . . . . . . . . . . . . . . . . 172.1.1 Oset Voltage . . . . . . . . . . . . . . . . . . . . . . . 172.1.2 Input Current . . . . . . . . . . . . . . . . . . . . . . . 182.1.3 Input Common Mode Voltage Range . . . . . . . . . . 192.1.4 Maximum Output Voltage Swing . . . . . . . . . . . . 192.1.5 Output Impedance . . . . . . . . . . . . . . . . . . . . 202.1.6 Common-Mode Rejection Ratio . . . . . . . . . . . . . 202.1.7 Supply Voltage Rejection Ratio . . . . . . . . . . . . . 212.1.8 Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . 212.1.9 Unity Gain Bandwidth and Phase Margin . . . . . . . 222.1.10 Settling Time . . . . . . . . . . . . . . . . . . . . . . . 242.2 Methodology of Choosing Op-Amp Parameters . . . . . . . . 242.3 How to Adjust the Parameters . . . . . . . . . . . . . . . . . 25iCONTENTS ii2.3.1 Specication . . . . . . . . . . . . . . . . . . . . . . . 252.3.2 Procedure of Optimization . . . . . . . . . . . . . . . 252.3.3 Optimize the Parameters of the Op-Amp . . . . . . . 272.3.4 How to get the Quiescent point in a complex circuit . 332.4 Target Op-Amp Specications . . . . . . . . . . . . . . . . . . 343 Current Mirrors and Biasing Networks 353.1 Ideal Characteristics of a Current Mirror . . . . . . . . . . . . 363.2 Basic Current Mirror Derivation . . . . . . . . . . . . . . . . 363.3 Benchmark Test Circuit . . . . . . . . . . . . . . . . . . . . . 383.4 Examined Current Mirrors . . . . . . . . . . . . . . . . . . . . 393.4.1 Basic Current Mirror . . . . . . . . . . . . . . . . . . . 393.4.2 Cascade/Cascode Current Mirror . . . . . . . . . . . . 413.4.3 Wilson Current Mirror . . . . . . . . . . . . . . . . . . 433.4.4 Modied Wilson Current Mirror . . . . . . . . . . . . 443.4.5 Reduced Cascade Current Mirror . . . . . . . . . . . . 453.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 Dierential Input Stage 484.1 The Unbuered Op-Amp . . . . . . . . . . . . . . . . . . . . 484.2 Small Signal Equivalent Circuits . . . . . . . . . . . . . . . . 494.3 The Frequency Response . . . . . . . . . . . . . . . . . . . . . 534.4 Phase Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . 574.5 Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 584.6 Adding Rz in series with Cc . . . . . . . . . . . . . . . . . . . 604.7 Gain Bandwidth Product . . . . . . . . . . . . . . . . . . . . 614.8 Large Signal Consideration . . . . . . . . . . . . . . . . . . . 624.9 Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634.10 The Common-Mode Range . . . . . . . . . . . . . . . . . . . 644.11 Important Relationships for The Design . . . . . . . . . . . . 664.12 Tradeos for Increasing the Gain of the Two Stage Op-Amp. 664.13 Design Methodology for the Two Stage Op-Amp . . . . . . . 674.14 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . 694.15 Limitations of the Two Stage Op-Amp . . . . . . . . . . . . . 724.16 The Cascode Op-Amp . . . . . . . . . . . . . . . . . . . . . . 725 Inverting Ampliers 765.1 Inverter with Active Resistor Load . . . . . . . . . . . . . . . 775.2 Inverter with Current Source/Sink Load . . . . . . . . . . . . 835.3 Push-Pull Inverter . . . . . . . . . . . . . . . . . . . . . . . . 87CONTENTS iii5.4 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925.5 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926 Control Network and Output Stage 956.1 Classication of Output Stage . . . . . . . . . . . . . . . . . . 966.2 Class-A Output Stage . . . . . . . . . . . . . . . . . . . . . . 966.2.1 Simple output amplier using a Class-A, current-sourceinverter . . . . . . . . . . . . . . . . . . . . . . . . . . 966.2.2 Common-Drain (Source-Follower) Output Amplier . 986.2.3 Power Analysis . . . . . . . . . . . . . . . . . . . . . . 986.3 Class-B Output Stage . . . . . . . . . . . . . . . . . . . . . . 996.3.1 Push-Pull, Inverting CMOS amplier . . . . . . . . . 996.3.2 Power Analysis . . . . . . . . . . . . . . . . . . . . . . 1016.4 Class-AB Output Stage . . . . . . . . . . . . . . . . . . . . . 1016.5 Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . 1026.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036.7 Design Considerations . . . . . . . . . . . . . . . . . . . . . . 1066.7.1 Negative Feedback . . . . . . . . . . . . . . . . . . . . 1066.7.2 Frequency Compensation . . . . . . . . . . . . . . . . 1067 Integrating the Sub-Circuits 1087.1 Overall Performance . . . . . . . . . . . . . . . . . . . . . . . 1097.2 The Measurement of Some Main Parameters . . . . . . . . . 1107.2.1 Input Oset Voltage . . . . . . . . . . . . . . . . . . . 1107.2.2 Common-Mode Rejection Ratio (CMRR) . . . . . . . 1127.2.3 Output Resistance - Ro . . . . . . . . . . . . . . . . . 1147.3 Delivering Power to the Load/Instantaneous Power . . . . . . 1177.4 Improving the Output Buer . . . . . . . . . . . . . . . . . . 1187.4.1 Stabilizing the Output . . . . . . . . . . . . . . . . . . 1207.4.2 The Final Schematic . . . . . . . . . . . . . . . . . . . 1218 Closing Remarks 1228.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1228.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239 Bibliography 124PrefaceThe purpose of this document is to familiarize the reader with the Cadenceset of tools in order to do analog micro-electronic circuits. The design processwill use TSMCs CMOSP35 technology and as a result requires access to therestricted technology les.ivChapter 1IntroductionThis tutorial assumes that the user is working in the CMC supplied envi-ronment for CMOSP35 design.1.1 Review of CMOS FETsThe Complimentary Metal Oxide Semi-Conductor Field Eect Transistor isa four terminal device: Base, Emitter, Collector and Substrate. Unlike theBipolar Transistor the MOSFET is a symmetrical device: the source anddrain can be interchanged.The models which SPICE uses for the CMOSP35 technology are veryaccurate, however, are too complex to be used by humans. A quick overviewof the device operation follows, for a more complete discussion please referto an appropriate text book. The gate of the device is insulated from therest of the device, meaning that no current will ow into the gate of aMOSFET. The substrate connection, for an N-channel transistor, is alwaysconnected to VSS (which usually means ground). When the voltage on thegate of the device is large enough an inversion layer forms under the gate,between the drain and source. This means that a channel of charge carriersexists between the two N-type regions. For an N-channel transistor thesecharge carriers will be electrons. This allows current to ow from the sourceterminal to the drain terminal. Some generalized relationships are statedbelow.1CHAPTER 1. INTRODUCTION 2Ids = effCoxWL__VgVfb2B Vds2_Vds_effCoxWL_22siqNa3Cox_(2B +Vds)32(2B)32__ (1.1)1.2 Creating a New Library in CadenceOnce Cadence has been started the icfb window is shown. This is the mainwindow for Cadence; all messages, including error and warning messages,will be displayed in this window.Figure 1.1: Cadence icfb Window with CMOSP35 technologyIn order to create a new library select the following menu options:Tools Library ManagerFrom the Library Manager window it is possible to access all availablelibraries and to create new libraries. In order to create a new library:File New LibraryThis will pop-up a new window where the library name can be specied.In this example we will use the name mylib.Once you have entered the name of the library which is to be created,press OK. The next dialog will ask information about the technology lewhich is to be associated with the new library. For this tutorial we will beusing CMOSP35, therefore, select Attach to existing techle: this will bringanother dialog window which lets us select which technology le we will use.Select cmosp35.CHAPTER 1. INTRODUCTION 3Figure 1.2: Cadence Library ManagerFigure 1.3: NewLibrary DialogWindowFigure 1.4: Technol-ogy File For New LibraryWindowFigure 1.5: Attach Design Library WindowCHAPTER 1. INTRODUCTION 41.3 Schematic CaptureIn this section we will be showing step by step how to enter a circuitschematic into Cadences Virtuoso Schematic Editor and how to create asymbol view for the schematic using the Virtuoso Symbol Editor. This sec-tion will not give a circuit directly, but rather leave the reader to use someof the schematics presented later in the document (Section 1.4 is a goodstarting circuit for a novice user).In order to create a new Cell View, open the Library Manager and clickon the new library which has been created, followed by:File New Cell ViewA dialog window will appear asking for the name of the new Cell View:enter OpAmp. This will automatically open the schematic capture session.1.3.1 Virtuoso Schematic EditorFigure 1.6) is the main window from which all of the schematic capture isperformed. Along the left boarder of the window are icon-buttons whichallow for easy access to the more common commands. Moving the mousecursor over these windows will show a tool-tip which explains which com-mand is executed with each button. All commands are also available via themenus at the top of the window. Most commands will also have a short-cutkey associated with them.When a schematic is entered the Insert Instance but is used (alterna-tively Add Instance may be used) is used in order to place componentsinto the schematic. We will mostly be using transistors, resistors and ca-pacitors (which are found in the library cmosp35) and power supplies andgrounds (which are found in the library analogLib). If the exact name ofthe desired cell is not known the Browse button may be used to open theLibrary Manager and graphically select the component. Components areconnected with narrow wires which may also be added via the icon-buttonsor the menus.When an instance of a component is added to a schematic all of theavailable parameters to the model may be set. These parameters may bechanged later using the Properties option. Some parameters are mandatoryto be entered (e.g. power supply voltage) whereas some parameters willdefault to certain values if they are not entered. Values may also be set tovariables, by entering a string instead of a numeric value, which can be setCHAPTER 1. INTRODUCTION 5Figure 1.6: Cadence Virtuoso Schematic Editorin the simulation stage.Once a design has been entered, it can be saved with a Check and Saveicon-button. This will do a general check of the circuit in order to make surethat all circuits have and ground and that all device terminals are connectedto something.An example of schematics for generating the characteristic curves isshown in Section 1.4. We will not discuss all of the options available forthis window since they are very numerous and are mostly self-explanatory.1.3.2 Virtuoso Symbol EditorOnce the schematic for the circuit is done, a symbol view must be created.This is the view which is used when an instance of the circuit is put intoanother schematic (e.g. a test bench circuit). Create a default symbol byclicking:Design Create Cell View From Cell ViewSimply except the defaults and this opens the Symbol Editor. On start-up the symbol editor will have a plain looking rectangle with terminal pinsfor each I/O pin inserted in the schematic. Once again we will simply acceptthe defaults andIn order to use the circuit which has been created is it necessary tocreate a test bench circuit. This test bench circuit is created similarly tothe original circuit, except that no symbol is generally required. The symbolof the newly created circuit may be inserted as any other sub-circuit.CHAPTER 1. INTRODUCTION 61.3.3 Arma Analog Circuit Design EnvironmentOnce a test bench circuit has been created and saved it is possible to startthe simulation environment:Tools Analog EnvironmentThe Arma window, gure 1.7, is the window from which all simulationsare congured and executed.Figure 1.7: Arma Analog Environment Simulation WindowIn order to run a simulation there are several things which must bedened: Selecting a simulator. The Avant Star-HSPICE simulator is the bestsimulator available; in order to select the simulator: Setup Simu-lator. In the dialog window which appears change the simulator se-lection to hspiceS; click OK. It is also important to dene the en-vironment for the simulator so that all of the correct models lesare used by the simulator: Setup Environment. The dialog boxwhich appears contains a eld entitled Include File. Set this eld to/CMC/kits/cmosp35/models/hspice/icdhspice.init,click OK. Setting variables from the schematic. If there are any parameter set-tings which are set to variables, these variables must be copied fromthe cell view to the analog environment: Variables Copy From Cellview. All variables which appear in the cell view will now be listed inthe bottom left of the Arma window. By double-clicking the vari-ables it is possible to change the value of the variable for the nextsimulation run. All variables must be assigned values before a simula-tion may be performed.CHAPTER 1. INTRODUCTION 7 Selecting and conguring the simulations. There are several types ofsimulations which may be performed at the same time. In order tochoose the simulation settings: Simulation Choose. Most of theparameters available in the simulation settings are relatively straightforward and are left to the reader to lookup. Selecting which variables are saved/plotted from the simulation. Thelast step required to run a simulation is to set which variables shouldbe plotted and saved. By default not all variables are saved sincethis could lead to vary large amounts a data being generated by thesimulation, this becomes more important for larger designs. In orderto plot/save a set of values: Outputs To Be Plotted Select onSchematic. This allows the user to click on all nodes (voltages) anddevice terminals (currents entering/leaving) in the schematic. Theschematic should reect which nodes/terminals have been selected.Once the selection is done press ESC.Simulation may now be started by using the menu system or with theicon-buttons located on the right side of the Arma window.1.3.4 The Waveform WindowOnce the simulation is complete all outputs which were selected to be plot-ted, will be in Waveform Window, Figure 1.8.Figure 1.8: Waveform WindowThe Waveform Window allows may customizations in order to generatedesired plots; it is possible to add annotations, titles, modify plot ranges& axis and add additional plots. Most of these options are fairly straightCHAPTER 1. INTRODUCTION 8forward and will not be discussed in detail, the reader is encouraged toexperiment with the various display options.One of the more advanced features available from the window is thecalculator which is discussed in the next section.1.3.5 The Cadence CalculatorThe Cadence Calculator is an extremely powerful tool for analyzing datagenerated by the simulation. Some of the many features of the Calculatorare: basic arithmetic operations on waveforms, Discrete Fourier Transforms,Total Harmonic Distortion analysis, and many more.Figure 1.9: Cadence CalculatorThe calculator allows entry of waveform information by a variety of ways.One way of easily accessing the data is to use the wave button and followedby selecting one of the waveforms displayed in the waveform window. If thesimulation contains a larger number of simulated values than the browserbutton may be employed to browse through all of the information storedfrom the simulation.The order in which operations are entered into the calculator may becounter intuitive to new users: The calculator uses a Postx notation. Thetable below shows some examples of the default order of operations:a +b a, b, +a b +c a, b, , c, +sin a + cos b b, cos, a, sin, +In the above table each letter represents one expression/waveform from thesimulation. The display stack options is useful for evaluating large expres-sions. In order to learn more about the many functions available in thecalculator the reader should refer to the Cadence documentation.CHAPTER 1. INTRODUCTION 91.4 Generating the Characteristic MOSFET CurvesThe enhancement-type MOSFET (Metal-Oxide Semiconductor Field-EectTransistor) is the most widely used eld-eect transistor in the FET family,which signicance is on par with that of the bipolar junction transistor,witheach having its own areas of application. The current-control mechanism isbased on an electric eld established by the voltage applied to the controlterminal. And the current is conducted by only type of carrier(electrons orholes) depending on the type of FET (N channel or P channel).1.4.1 N-channel Enhancement-Type MOSFETThe transistor is fabricated on a P-type substrate, which is a single-crystalsilicon wafer that provides physical support for the device. Two heavilydoped n-type regions, the source and the drain regions, are created in thesubstrate. A thin (about 0.1um) layer of silicon dioxide(SiO2) is grownon the surface of the substrate, covering the area between the source thedrain regions. Metal is deposited on top of the oxide layer to form the gateelectrode of the device. Metal contacts are also made to the source region,the drain region,and the substrate, also known as the body. Thus, fourterminals are brought out: the Gate(G), the Source(S), the Drain(D), andthe Body(B).Observe that the substrate forms PN junctions with the source and drainregions. In normal operation these PN junctions are kept reverse-biased atall time. Since the drain will be at a positive voltage relative to the source,the two PN junctions can be eectively cut o by simply connecting the sub-strate terminal to the source terminal.Here, the substrate will be consideredas having no eect on device operation, and the MOSFET will be treatedas a 3-terminal device, with the terminals being the gate(G), the source(S),and the drain(D). We applied a voltage to the gate controls current owbetween source and drain. This current will ow in the longitudinal direc-tion from drain to source in the region called channel region. Note thatthis region has a length L and a width W, two important parameters of theMOSFET. Typically, L is in the range 1 to 10 m, and W is in the range 2to 500 m.The operation with VdsWith no bias voltage applied to the gate, two back-to-back diodes existin series between drain and source. They prevent current conduction fromdrain to source when a voltage Vds is applied. In fact, the path betweendrain and source has a very high resistance (of the order of 1012)CHAPTER 1. INTRODUCTION 10With a positive voltage, which exceed the threshold voltage Vt, appliedto the gate, the transistor induced a n-channel. When applying a positivevoltage Vds between drain and source, as shown in the gure below,Figure 1.10: N-Channel Test CircuitThe voltage Vds cause a current iD to ow through the induced N chan-nel. Current is carried by free electrons travelling from source to drain. Themagnitude of iD depends on the density of electrons in the channel, which inturn depends on the magnitude of VGS. As VGS exceeds Vt, more electronsare attracted into the channel. We may visualize the increase in chargecarriers in the channel as an increase in the channel depth. The result is achannel of increased conductance or equivalently reduced resistance.Let VGS be held constant at a value greater than Vt (for example 2V),and increase the VDS from 0 to 3.3V. As VDS is increased, the ID VDScurve is shown inEventually, when VDS is increased to the value that reduces the voltagebetween gate and channel at the drain end to Vt, that is :VGSVDS = VtorVDS = VGSVtthe channel depth at the drain end decreases to almost zero, and the channelis said to be pinched o. Increase VDS beyond this value has little eect(theoretically, no eect) on the channel shape, and the current through thechannel remain constant at the value reached for VDS = VGS Vt. Thedrain current thus saturates at this value, and the MOSFET is said toCHAPTER 1. INTRODUCTION 11Figure 1.11: IDVDS Curvehave entered the saturation region of operation. The voltage VDS at whichsaturation occurs is named VDS,satVDS,sat = VGSVtObviously, for every value of VGS Vt, there is a corresponding value ofVDS,sat. The device operates in the saturation region if VDS VDS,sat. Theregion of the ID VDS characteristic obtained for VDS < VDS,sat is calledthe triode region.The IDVDS CharacteristicsThe Figure above shows a typical set of IDVDS characteristics, whichare a family of curves, each measured at a constant VGS. We can see thatthere are three distinct regions of operation: the cuto region, the trioderegion, and the saturation region. The saturation region is used if the FETis to operate as a amplier. For operation as a switch, the cuto and trioderegions are utilized.1. TriodeIf VGS > Vt and VDS VGS Vt, then the n-channel is continuousall the way from S to D. The S and D are connected by a conductor(or a resistor) of a given resistance. The drain current increases ifthe voltage drop between S and D increases. The channel resistanceCHAPTER 1. INTRODUCTION 12Figure 1.12: IDVDS Curvedepends on how much charge is injected at the S-end, which in turnis controlled by vGS. The Drain current Id depends on both vGS andVGD (or VDS). The ID VDS characteristics can be approximatelydescribed by the relationshipID = K [2(VGSVt)VDSVDS VDS] (1.2)in which K is a device parameter given byK = 0.5Un Cox_WL_ _ AV2_ (1.3)Un physical constant known as the electron mobility(its value inthis case applies for the electrons in the induced n channel)Cox oxide capacitance, the capacitance per unit area of thegate-to-body capacitor for which the oxide layer serves asdielectric.L,W the length and the width of the channel.Since for a given fabrication process the quantity (0.5Un*Cox) is aconstant, approximately 10A/V 2for the standard NMOS processwith a 0.1m oxide thickness. So the aspect ratio of WL determines itsconductivity parameter K.CHAPTER 1. INTRODUCTION 13If VDS is suciently small so that we can neglect the VDS VDS inequation 1.2, then the ID VDS characteristics near the origin therelationshipID = 2K(VGSVt)VDS (1.4)This linear relationship represents the operation of the MOS transistoras a linear resistance RDSRDS = VDSID= 12K(VGSVt) (1.5)2. SaturationIf VGS > Vt and VDS VGSVt, then N-channel is induced at the S-end, but the channel is depleted at the D-end. That is, the N-channelis pinched o at the Drain-end. Increasing Vds beyond Vds(sat), orequivalently decreasing VGD below Vt, creates a fully depleted regionbetween the inversion n-channel and the drain region. An electriceld is set up in this region, pointing from the Drain region towardthe inversion channel. Carrier electrons in the N-channel that reachthe depletion boundary are swept across the depletion region into theDrain. This is similar to PN junction diode where the minority carrierelectrons of the P-side are swept to the n-side by the built-in eldwhenever they reach the depletion boundary. Once the drain-end ofchannel is pinched o, the current no longer depends on the voltageapply between S and D.The boundary between the triode region and the saturation region ischaracterized byVDS = VGSVt (1.6)Substituting it into Equation 1.2 gives the saturation value of thecurrent ID isID = K(VGSVt) (VGSVt) (1.7)Thus in saturation the MOSFET provides a drain current whose valueis independent of the drain voltage VDS and is determined by the gatevoltage VGS according to the square-law relationship.The complete independence of ID on VDS in saturation and the corre-sponding innite output resistance at the drain is an idealization basedon the premise that once the channel is pinched o at the drain end,further increases in VDS have no eect on the channels shape. In prac-tice, increasing VDS beyond vDS,sat does aect the channel somewhat.CHAPTER 1. INTRODUCTION 14Specically, as VDS is increased, the channel pinch-o point is movedslightly away from the drain toward the source. Thus the eectivechannel is reduced, a phenomenon called channel-length modulation.Since the channel resistance is proportional to the channel length, thechannel resistance is decreased. This results in the slight increase ofthe drain current beyond the saturation level. Now since K is in-versely proportional to the channel length (Equation 1.3), so, K and,correspondingly, ID, increases with VDS. Mathematically, the channellength modulation introduces a VDS-dependent term in ID:ID = K(VGSVt)(VGSVt)(1 + VDS) (1.8) the channel-length modulation parameter:0.005 < < 0.03From Fig.nid.ps we extrapolated the straight-line IDVDS character-istics in saturation, intercept the VDS-axis at the point VDS = 1 =VA. So vA is in the range 200 to 30 volts. It should be obvious thatchannel-length modulation makes the output resistance in saturationnite. Let the output resistance Rout asRout = 1 K(VGSVt) (VGSVt) VGS = constant (1.9)approximated byRout = 1 ID(1.10)substituted by = 1VARout = VAID(1.11)Thus the output resistance is inversely proportional to the DC biascurrent ID.3. CutoIf VGS < Vt (and of course, VGD < Vt), then the no n-channel is presentand no current ows.1.4.2 P-channel Enhancement-Type MOSFETA P-channel enhancement-type MOSFET (PMOS transistor) is fabricatedon an N-type substrate with p+ regions for the drain and the source, andholes as charge carriers. The device operates in the same manner as theN-channel device except the VGS and VDS are negative and the thresholdCHAPTER 1. INTRODUCTION 15Figure 1.13: P-Channel Test Circuitvoltage Vt is negative. Also the current iD enters the source terminal andleaves through the drain terminal.To induce a channel we apply a gate voltage that is more negative thanVt, and apply a drain voltage that is more negative than the source voltage(i.e. VDS is negative or, equivalently, vSD is positive). The current iD isgiven by the same equation as for NMOS, and the K is given byK = 0.5 Up Cox_WL_ (1.12)where Up is the mobility of holes in the induced p channel. Typically, Up =0.5Un, with the result that for the same W/L ratio a PMOS transistor hashalf the value of K as the NMOS device.The ID VDS characteristics is shown above. The current ID is givenby the same equation used for NMOS.ID = K(VGSVt)(VGSVt)(1 + VDS)where VGS, Vt, , and VDS are all negative.PMOS technology was originally the dominant one. However, becauseNMOS devices can be made smaller and thus operate faster, and becauseNMOS requires lower supply voltages than PMOS, NMOS technology hasvirtually replaced PMOS. Nevertheless, it is important to develop the PMOSCHAPTER 1. INTRODUCTION 16Figure 1.14: IDVDS Curvetransistor for two reasons: PMOS devices are still available for discrete-circuit design, and more importantly, both PMOS and NMOS transistorsare utilized in CMOS circuits!Chapter 2An Introduction to Op-Amps2.1 Parameters of an Op-AmpThis section will discuss Op-Amp parameters. The designer of an Op-Ampmust have a clear understanding of what Op-Amp parameters mean andtheir impact on circuit design. The selection of any Op-Amp must be basedon an understanding of what particular parameters are most important tothe application. In the next section, we will discuss the method of measure-ment of these dierent parameters2.1.1 Oset VoltageAll Op-Amps require a small voltage between their inverting and noninvert-ing inputs to balance mismatches due to unavoidable process variations. Therequired voltage is known as the input oset voltage and is abbreviated Vos.Vos is normally modelled as a voltage source driving the noninverting input.Generally, Bipolar input Op-Amps typically oer better oset parametersthan JFET or CMOS input Op-Amps. There are two other parameters re-lated to and aect Vos: the average temperature coecient of input osetvoltage, and the input oset voltage long-term drift. The average temper-ature coecient of input oset voltage, a Vos, species the expected inputoset drift over temperature. Its units is _mVoC. Vos is measured at the tem-perature extremes of the part, and a Vos is computed as VosoC . Normal aging insemiconductors causes changes in the characteristics of devices. The inputoset voltage long-term drift species how Vos is expected to change withtime. Its units are mVmonth. Input oset voltage is of concern anytime thatDC accuracy is required of the circuit. One way to null the oset is to useexternal null inputs on a single Op-Amp package (2.1). A potentiometer is17CHAPTER 2. AN INTRODUCTION TO OP-AMPS 18Figure 2.1: Oset Voltage Adjustconnected between the null inputs with the adjustable terminal connectedto the negative supply through a series resistor. The input oset voltageis nulled by shorting the inputs and adjusting the potentiometer until theoutput is zero. However, even if the Vos is nulled at the beginning, it willchange with temperature and some other conditions.2.1.2 Input CurrentThe input circuitry of all Op-Amps requires a certain amount of bias currentfor proper operation. The input bias current, IIB, is computed as the averageof the two inputs:IIB = (IN +IP)2 (2.1)CMOS and JFET inputs oer much lower input current than standard bipo-lar inputs. The dierence between the bias currents at the inverting andnoninverting inputs is called the input oset current, Ios = IN +IP. Osetcurrent is typically an order of magnitude less than bias current.Input bias current is of concern when the source impedance is high. Ifthe Op-Amp has high input bias current, it will load the source and a lowerthan expected voltage is seen. The best solution is to use an Op-Amp witheither CMOS or JFET input. The source impedance can also be lowered byusing a buer stage to drive the Op-Amp that has high input bias current.In the case of bipolar inputs, oset current can be nullied by matchingthe impedance seen at the inputs. In the case of CMOS or JFET inputs,the oset current is usually not an issue and matching the impedance isnot necessary. The average temperature coecient of input oset current,CHAPTER 2. AN INTRODUCTION TO OP-AMPS 19Figure 2.2: Output Voltage SwingIos, species the expected input oset drift over temperature. Its units are_mAoC.2.1.3 Input Common Mode Voltage RangeThe input common voltage is dened as the average voltage at the invertingand noninverting input pins. If the common mode voltage gets too high ortoo low, the inputs will shut down and proper operation ceases. The com-mon mode input voltage range, VICR, species the range over which normaloperation is guaranteed. For instance, Rail to rail input Op-Amps use com-plementary N and P channel devices in the dierential inputs. When thecommon-mode input voltage nears either rail, at least one of the dierentialinputs is still active, and the common-mode input voltage range includesboth power rails.2.1.4 Maximum Output Voltage SwingThe maximum output voltage, VOM, is dened as the maximum positiveor negative peak output voltage that can be obtained without waveformclipping, when quiescent DC output voltage is zero. VOM is limited bythe output impedance of the amplier, the saturation voltage of the outputtransistors, and the power supply voltages. This is shown pictorially in 2.2.CHAPTER 2. AN INTRODUCTION TO OP-AMPS 20This emitter follower structure cannot drive the output voltage to ei-ther rail. Rail-to-rail output Op-Amps use a common emitter (bipolar) orcommon source (CMOS) output stage. With these structures, the outputvoltage swing is only limited by the saturation voltage (bipolar) or the onresistance (CMOS) of the output transistors, and the load being driven.2.1.5 Output ImpedanceDierent data sheets list the output impedance under two dierent condi-tions. Some data sheets list closed-loop output impedance while others listopen-loop output impedance, both designated by Zo. Zo is dened as thesmall signal impedance between the output terminal and ground. Generally,values run from 50 to 200 .Common emitter (bipolar) and common source (CMOS) output stagesused in rail-to-rail output Op-Amps have higher output impedance thanemitter follower output stages. Output impedance is a design issue whenusing rail-to-rail output Op-Amps to drive small resistive or large capacitiveloads. If the load is mainly resistive, the output impedance will limit howclose to the rails the output can go. If the load is capacitive, the extra phaseshift will erode phase margin. 2.3 shows how output impedance aects theoutput signal assuming Zo is mostly resistive.Figure 2.3: Eect of Output Impedance2.1.6 Common-Mode Rejection RatioCommon-mode rejection ratio, CMRR, is dened as the ratio of the dif-ferential voltage amplication to the common-mode voltage amplication,AdifAcom. Ideally this ratio would be innite with common mode voltages beingtotally rejected.The common-mode input voltage aects the bias point of the input dif-ferential pair. Because of the inherent mismatches in the input circuitry,CHAPTER 2. AN INTRODUCTION TO OP-AMPS 21changing the bias point changes the oset voltage, which, in turn, changesthe output voltage.2.1.7 Supply Voltage Rejection RatioSupply voltage rejection ratio, kSVR (AKA power supply rejection ratio,PSRR), is the ratio of power supply voltage change to output voltage change.The power voltage aects the bias point of the input dierential pair.Because of the inherent mismatches in the input circuitry, changing the biaspoint changes the oset voltage, which, in turn, changes the output voltage.For a dual supply Op-Amp, KSV R = V CCV OS or KSV R = VDDV OS. The termVCC means that the plus and minus power supplies are changed symmetri-cally. For a single supply Op-Amp, KSV R = V CCV OS or KSV R = VDDV OS. Alsonote that the mechanism that produces kSVR is the same as for CMRR.Therefore kSVR as published in the data sheet is a DC parameter likeCMRR. When kSVR is graphed vs. frequency, it falls o as the frequencyincreases.2.1.8 Slew RateSlew rate, SR, is the rate of change in the output voltage caused by a stepinput. Its units are V/ms or V/ms. 2.4 shows slew rate graphically.Figure 2.4: Slew RateThe primary factor controlling slew rate in most amps is an internalcompensation capacitor CC, which is added to make the Op-Amp unitygain stable. Referring to 2.5, voltage change in the second stage is lim-ited by the charging and discharging of the compensation capacitor CC.The maximum rate of change is when either side of the dierential pair isconducting 2IE. Essentially SR = 2IECC . However, that not all Op-Ampshave compensation capacitors. In Op-Amps without internal compensationcapacitors, the slew rate is determined by internal Op-Amp parasitic capac-itances. Uncompensated Op-Amps have greater bandwidth and slew rate,but the designer must ensure the stability of the circuit.CHAPTER 2. AN INTRODUCTION TO OP-AMPS 22Figure 2.5: Op amp schematic simpliedIn Op-Amps, power consumption is traded for noise and speed. In orderto increase slew rate, the bias currents within the Op-Amp are increased.2.1.9 Unity Gain Bandwidth and Phase MarginUnity-gain bandwidth (B1) and gain bandwidth product (GBW) are verysimilar. B1 species the frequency at which AV D of the Op-Amp is 1.GBW species the gain-bandwidth product of the Op-Amp in an open loopconguration and the output loaded:GBW = AV D f (2.2)Phase margin at unity gain (fm) is the dierence between the amount ofphase shift a signal experiences through the Op-Amp at unity gain and180o:fm = 180of@B1 (2.3)Gain margin is the dierence between unity gain and the gain at 180ophaseshift:Gain margin = 1 Gain@180ophase shift (2.4)In order to make the Op-Amp stable, a capacitor, CC, is purposely fabricatedon chip in the second stage (2.5). This type of frequency compensation isCHAPTER 2. AN INTRODUCTION TO OP-AMPS 23termed dominant pole compensation. The idea is to cause the open-loopgain of the Op-Amp to roll o to unity before the output phase shifts by180o. 2.5 is very simplied, and there are other frequency shaping elementswithin a real Op-Amp. 2.6 shows a typical gain vs. frequency plot for aninternally compensated Op-Amp.Figure 2.6: Voltage Amplication and Phase Shift vs. FrequencyPhase margin and gain margin are dierent ways of specifying the sta-bility of the circuit. Since rail-to-rail output Op-Amps have higher outputimpedance, a signicant phase shift is seen when driving capacitive loads.This extra phase shift erodes the phase margin, and for this reason mostCMOS Op-Amps with rail-to-rail outputs have limited ability to drive ca-pacitive loads.CHAPTER 2. AN INTRODUCTION TO OP-AMPS 242.1.10 Settling TimeIt takes a nite time for a signal to propagate through the internal circuitryof an Op-Amp. Therefore, it takes a period of time for the output to reactto a step change in the input. In addition, the output normally overshootsthe target value, experiences damped oscillation, and settles to a nal value.Settling time, ts, is the time required for the output voltage to settle towithin a specied percentage of the nal value given a step input. Settlingtime is a design issue in data acquisition circuits when signals are changingrapidly.Figure 2.7: Settling Time2.2 Methodology of Choosing Op-Amp Parame-tersThe methodology of choosing the parameters of the transistors, and theirrelationships, then it will be possible to get the desired quiescent point toensure the ideal wave output.Here we will to present a method of choosing the parameter in an Op-CHAPTER 2. AN INTRODUCTION TO OP-AMPS 25Amp circuit, and in the same way we can get a very ecient optimizationmethod. Further more in this way we can learn how to combine dierentparts of a circuit together, and deal with more complex circuits. First of allwe must clarify the relationship among dierent parameters, then we cannish our job orderly. The quiescent point is very important for our design.2.3 How to Adjust the ParametersTo simplify the discussion, we will concentrate on the simplest OTA Op-Amp 2.8 and demonstrate how to adjust its parameters to get the proper DCgain. At the same time we try to extend the method to other sophisticatedarchitectures.2.3.1 SpecicationHere we are asked to design an Op-Amp, whose VDD = 3.3 V , VSS =0 V , input bias voltage = 1.65V (Input V0 = 1.65 V ). Swing of output(Considering the current source VDD will occupy some voltage, the swingshould be 0 3 V .)Figure 2.8: Circuit with Default Parameters2.3.2 Procedure of Optimization1. Draw a circuit with default parameters.(See Figure 2.8).2. Adjust the current source value I0. The current value takes highestpriority of all of the parameters, all of the other parameters will bechosen to match the current value.CHAPTER 2. AN INTRODUCTION TO OP-AMPS 26From the circuit, we know that when the Op-Amp is working in thecommon mode (which means the V1 = V0 = 1.65 V ), then the currentthrough the two (2) dierential ampliers is symmetric, so the valueof I1 = 12 I0. Vout = 1.65 V , Vref = 1.65 V , from here we candecide what is the maximum and minimum value we can get througha PMOS. We design a very simple circuit to test the current valuefrom the drain of a PMOS (Figure 2.9). When changing the width ofthe channel of the PMOS, we can get a set of values of the currentvalue of the drain(Figure 2.10). Considering the width of the activeload should not to be too large so we can get better gain. The rangeof the length should be 400nm 2000 nm, then I1 should be from86.4366A 800.00A. So the I0 should be double I1 it should befrom 170A 1700A.Figure 2.9: Simple Test Circuit for Drain CurrentWe can choose any value inside the range, so we regard the 400m asthe initial value of our design.3. Decide the width of the channel of the active load. From Figure 2.9 weperform a parametric analysis. The value of the width of the channel,through which we can get the proper value for the quiescent point. Itis about 1.25m.4. We can assign an arbitrary big value to the width of the dierentialCHAPTER 2. AN INTRODUCTION TO OP-AMPS 27Figure 2.10: Simple Test Circuit - Parametric Analysis of Channel Widthamplier, suppose we choose a value 5 times bigger than the width ofthe active load.5. Do the simulation and compare the gain we get with the gain we want.Figure 2.11: Simple Test Circuit - DC Response/Gain2.3.3 Optimize the Parameters of the Op-Amp1. According to the gain of the specication, decide the width of thedierential amplier.Gm =_2K

nI0_WL__12Rout = VeL1I0CHAPTER 2. AN INTRODUCTION TO OP-AMPS 28AV = GmRout = Ve_2K

nW1L1I0_frac12There are three (3) variables that will aect AV , W, L and I0.If there is small dierence between the two (2) gains, then what weneed to do is just to adjust the value of the length and the width ofthe channel of dierential amplier, otherwise we must reduce the I0.2. Reduce I0; according to the fabricating technology, the width of thechannel of the transistor cannot be less than 350 m, which means wecannot reduce the I0 less than 170A. As mentioned above, otherwisethe quiescent point cannot be at the middle of the curve. (See Figure2.12), this will distort the input waveform. Each time I0 is adjustedthe width of the active load should be changed accordingly. Thusanother way to adjust I0 must be devised.Figure 2.12: Waveform Distortion3. Further reducing I0. First, we can cascade active loads together, be-cause the voltage is on the cascade active load, there is less voltageacross each transistor, so the I0 can be reduced dramatically. However,it becomes more complex to further optimize the circuit. See gure2.13CHAPTER 2. AN INTRODUCTION TO OP-AMPS 29Figure 2.13: Active Loads Cascaded TogetherFigure 2.14: Cascaded Active Loads - DC Response/GainCHAPTER 2. AN INTRODUCTION TO OP-AMPS 304. Cascade Op-Amp - adjusting the quiescent point: If after all of theabove eort, we still cannot get the proper gain, we have to use acascade Op-Amp. The key to optimizing the cascade Op-Amp is thequiescent point, which guarantees the proper operation of the circuit.Please refer the Figure 2.15 (Output curve of rst the stage).The output of the rst stage is linear in the area of (0.5 V 2.15 V ).So we should adjust the quiescent point of the input of the secondstage.Figure 2.15: Output Curve of the First StageChecking the 2 stage Op-Amp, as in Figure 2.16Figure 2.16: Two Stage Op-Amp CircuitIn the second stage amplier, we get the waveform as shown in Figure2.17 and Figure 2.18: We notice that the operating point of the am-plier begins to work is about 0V, actually at this point the output ofCHAPTER 2. AN INTRODUCTION TO OP-AMPS 31Figure 2.17: Second Stage Waveformthe rst stage is in the non-linear area. That means the wave we getisnt the best.Figure 2.18: Second Stage CircuitWe can change the parameters of the two (2) transistors, however,it will have little aect on the non-linear problem. (See Figure 2.19Non-Linear Problem). Thus we must use another topology. (Figure2.20).CHAPTER 2. AN INTRODUCTION TO OP-AMPS 32Figure 2.19: Non-Linear ProblemFigure 2.20: Dierent Topology to overcome Non-Linear ProblemCHAPTER 2. AN INTRODUCTION TO OP-AMPS 33We then get the resulting waveform shown in Figure 2.21.Figure 2.21: Resulting WaveformWe can adjust the circuit in another way, to change the input lineararea of the second stage. To simplify the problem we can change theoutput stage.Figure 2.22: Circuit with Modied Output Stage2.3.4 How to get the Quiescent point in a complex circuitKeeping a good quiescent point is very important and can be easily forgottenas the circuits become more complex. There are certain ways to design withthe help of the computer, and establish models for dierent stages.CHAPTER 2. AN INTRODUCTION TO OP-AMPS 342.4 Target Op-Amp SpecicationsThe table below denes the best and worst cases for several key Op-Ampparameters, in addition the target Op-Amp parameters for this design arelisted. These values are based upon textbook values, fabricated Op-Ampdatasheets and from other research. During its design these key parameterswere always kept at close hand.Specication Worst Case Target Case Best CaseGain 100 1, 000 1, 000 100, 000 1,000,000+Frequency Range (Hz) 10-20,000 10-200,000 5-500,000Bandwidth 5.0 KHz 20.0 KHz 50.0 KHzInput Voltage 1 mV 1 V 0.1 VOutput Resistance 500 K 1 M 10 MPower Consumption mW W nWCMRR > 40 dB > 50dB > 60dBSlew Rate 3 V/sec 2 V/sec 0.5 V/secTHD 1% 0.1% 0.01%Parasitic Capacitance 1.0 F 1.0 nF 1.0 fFRise Time 1 sec 0.1 sec 0.001 secSettling Time 10 sec 1 sec 0.1 secChapter 3Current Mirrors and BiasingNetworksOne of the most important parts of an analog design is the biasing circuity.The purpose of the bias circuity is establish an appropriate DC operatingpoint for the transistor. With the correct DC operating point established astable and predictable DC drain current ID and a DC drain-source voltageensures operation in the saturation region for all input signals that may beencountered. This component forms the basis for an operational amplierwhereby various circuits like the dierential pair, gain stage and outputstage rely on its awless stable operation.For the Operational Amplier design ve dierent types of current mir-rors were examined; Basic Current Mirror, Cascade/Cascode Current Mir-ror, Wilson Current Mirror, Modied Wilson Current Mirror and ReducedCascade/Cascode Current Mirror. The advantages and disadvantages ofeach type of current mirror will be outlined later.The ve current mirrors which were examined were designed in Cadenceand were placed into a standard test circuit consisting of a basic dieren-tial pair with active load and basic common-source amplier output stagewith a 10K load. These current mirrors were then subjected to severaltests including; DC Sweep, current mirror output impedance and stabilityof current supplied across dynamic voltage range.The ability of a current mirror to hold current constant, the number oftransistors used and their sizes are the general dening factors on whethera current mirror is Good or not. These factors were considered when de-ciding on the current mirror to be used in the Op-Amp Design.35CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 363.1 Ideal Characteristics of a Current Mirror1. Output current linearly related to the input current. Iout = A Iin.2. Input Resistance is zero.3. Output resistance is innity.3.2 Basic Current Mirror DerivationBelow is the derivation of the simple current mirror.Q1 is operating in the saturation region since its drain is shorted to itsgate.Thus,ID1 = 12Kn

_WL_1(VGSVt)2(3.1)Note we neglect channel-length modulation and assume = 0.The drain current of Q1 is supplied by VDD through a resistor, R.Assuming gate currents to be approximately 0.ID1 = Iref = VDDVGSR (3.2)Now looking at Q2,It has the same Vgs as Q1, and assuming it is operating in saturation, itsdrain current, which is the output current Io of the current source will be,IO = ID2 = 12Kn

_WL_2(VGSVt)2(3.3)Again neglecting channel-length modulation.Using equations 1,2 and 3 we are able to relate the output current Io tothe reference current Iref.Rearranging equation 1 and substituting Iref = Id1Iref_WL_1= 12Kn

_WL_1(VGSVt))2(3.4)CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 37We know,IO =_12Kn (VGSVt)2_ _WL_ (3.5)So substituting into equation 3.5,IO = Iref_WL_1_WL_2IOIref=_WL_2_WL_1(3.6)Thus we have a relationship whereby modifying the width and length wecan change the output current.Thus if the transistors were matched, i.e. width and lengths equal andother parameters the same we have,IOIref= 1 (3.7)IO = Iref (3.8)This is called a current mirror since the reference current is mirroredor held constant at the output.CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 383.3 Benchmark Test CircuitThe purpose of the test circuit is to establish a benchmark which could beused to evaluate the performance and design of each of the dierent typesof biasing circuits. This test circuit was kept the same for all tests and thetransistor sizes were set to the smallest possible optimum values. The testcircuit itself consists of a basic dierential pair (W=1900nm, L=350nm), abasic two transistor active load (W=800nm, L=350nm) and common sourceamplier (W=800nm, L=350nm).Figure 3.1: Benchmark Test Circuit SchematicThe widths of the transistors were adjusted so that the current suppliedto the dierential pair was between 6.50A and 7.00A. Then the outputimpedance was measured, as well as, the overall size of the transistors oncethe desired current was achieved. These results were recorded out wouldhelp to choose which current mirror would be the Winner.CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 393.4 Examined Current Mirrors3.4.1 Basic Current MirrorWe will now examine the most fundamental and simple type of currentmirror, the Basic Current mirror (See Figure 3.2). This type of currentmirror uses a minimum of (3) three transistors. The derivation shown earliershows the general operation of a current mirror whereby current is heldconstant regardless of the voltage being supplied.Figure 3.2: Basic Current Mirror SchematicThis circuit is very simple and does a very good job of supplying constantcurrent, however, it does not supply absolutely stable current. See gure 3.3,the output current supplied to the active load and the output impedance.Figure 3.3: Basic Current Mirror Simulation ResultsCHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 40The main advantage of this current mirror is its simplicity and easeof implementation, however, the major disadvantage is that the currentsupplied is not completely stable.CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 413.4.2 Cascade/Cascode Current MirrorThe second current mirror examined was the Cascade/Cascode Current Mir-ror. This current mirror uses a minimum of (5) ve transistors, these tran-sistors can be seen in the Figure 3.4.Figure 3.4: Cascade/Cascode Current Mirror SchematicThis circuit is a little bit more complex than the simple current mirrorwith (2) two extra transistors and would be more than enough for any design.The main disadvantage to this current mirror is that it is not very good atsupplying higher amounts of current, in particular to the output stages. Itwas given very high consideration when deciding which current mirror touse for the Op-Amp design.Figure 3.5: Cascade/Cascode Current Mirror Simulation ResultsCHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 42The main advantage to this design is that it provides stable currentand it has relatively small transistor sizes. In addition to this we have ahigher output resistance compared to the basic current mirror. The maindisadvantage to this type of current mirror is a reduced dynamic range.Thus, it scored high in our choice for current mirrors when testing.CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 433.4.3 Wilson Current MirrorThe third current mirror examined was the Wilson current mirror. Thiscurrent mirror uses a minimum of (4) four transistors. In the Figure 3.6 youcan see the circuit layout.Figure 3.6: Wilson Current Mirror SchematicThis circuit is not as complex as the cascade current mirror and doesprovide good stable current, however, to provide the benchmark 6.50 7.00A very large transistors (200m) had to be used, and thus, given thatthe current best, cascade current mirror provided similar qualities butwith much smaller transistor sizes this current mirror was ranked very low.Figure 3.7: Wilson Current Mirror Simulation ResultsAs stated above this design was not considered for the Op-Amp designand the cascade current mirror was the current best.CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 443.4.4 Modied Wilson Current MirrorThe fourth current mirror examined was the Modied Wilson current mirror.This current mirror uses a minimum of (5) ve transistors and has a similarlayout as the cascade current mirror. This current mirror was expected toperform similar to the regular Wilson current mirror. You can see the circuitschematic in Figure 3.8.Figure 3.8: Modied Wilson Current Mirror SchematicUpon testing the results revealed that the initial idea that it would per-form similarly to the regular Wilson current mirror were conrmed. It hadsimilar results with the output current as output resistance and the transis-tor sizes needed to attain the benchmark current we also large (200u).Figure 3.9: Modied Wilson Current Mirror Simulation ResultsUpon seeing these results, the Modied Wilson current mirror was notto be chosen as the current mirror for the Op-Amp design.CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 453.4.5 Reduced Cascade Current MirrorThe fth and nal current mirror examined was the Reduced Cascade cur-rent mirror. This current mirror used a minimum of (6) six transistors andhad a similar layout to that of the basic cascade current mirror. The wordReduced in the name refers to the reduced voltage at which the currentreaches a stable output, it is usually about (1/2) one-half of the usual volt-age.Figure 3.10: Reduced Cascade Current Mirror SchematicThis current mirror is a bit more complex and the transistor sizes arecomparable to the basic cascade current mirror. However, the reduced cas-cade current mirror oers a reduced voltage and is able to provide higheramounts of current. This is very useful in the output stages were higheramounts of current are needed to bias the output stages.Figure 3.11: Reduced Cascade Current Mirror Simulation ResultsCHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 46The results of this current mirror appeared to be the most promisingfor the Op-Amp design, it provided stable current, it was able to providehigher amounts of output current if necessary, as well as, it reduced the volt-age at which the current was stable compared to the other current mirrorsexamined.CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 473.5 ConclusionThe decision to use the Reduced Cascade/Cascode Current Mirror in the de-sign of this Op-Amp are now shown here. First, the reduced cascade/cascodecurrent mirror provided stable and linear current in all test situations. Sec-ondly, it provided very high output resistance and a very low input resis-tance. Third, it was able to supply larger amounts of current which wereneeded to drive the output stage. Lastly, given it had a few extra transistorstheir sizes were small compared to other current mirror setups looked at. Inthe table below you can see the current mirrors ranked from best to worst(top to bottom) as well as a few of the ranking criterion and their evaluation.The Basic Cascade/Cascode current mirror would have also done a verygood job in the design, however with the reduced cascades reduced voltageit oered a bit of an advantage over the basic cascade current mirror.Current Mirrors Min # of FETs Current Output Input Complexity Transistor SizesRanked: (Best to Worst) including Iref Stability Resistance Resistance needed to achieveTransistors Ref 7.0A CurrentReduced Cascade/Cascode 6+2N Excellent Very High Very Low Very High SmallBasic Cascade/Cascode 3+2N Very Good Very High Very Low Very High Very SmallBasic Wilson 2+2N Good High Very Low Moderate Very LargeModied Wilson 3+2N Good High Very Low Moderate Very LargeBasic 2+N Poor Low Very Low Simple SmallN = Number of times current is mirrored. (In these designs N = 2,dierential Pair Biasing and Output Stage)Chapter 4Dierential Input Stage4.1 The Unbuered Op-AmpFigure 4.1: Two Stage Op-AmpThe amplier shown in gure 4.1 can be segregated into:1. Biasing block.2. Dierential input stage.3. Output stage.48CHAPTER 4. DIFFERENTIAL INPUT STAGE 49The biasing block, consists of M8, M9, and M5. The bias current greatlyaects the performance of the amplier. The dierential input stage iscomposed of M1, M2, M3, M4 with: M1 matching M2, M3 matching M4.The output stage consists of M6 and M7.4.2 Small Signal Equivalent CircuitsFigure 4.2: NFET and Its Small Signal ModelIn the analysis of a FET amplier circuits, the FET can be replaced bythe equivalent circuit model, 4.2. Where:ro = |V A|IDWhere V A = 1gm is the transconductance parameter = Kn

WL (VGSVt)Therefore, the small signal model parameters:gm and ro depends on the DC bias of the FET.Ideal constant DC voltage sources are replaced by short circuits, this is aresult of the fact that the voltage across an ideal constant DC voltage sourcedoes not change and thus there will always be a zero voltage signal acrossa constant DC voltage source. The signal current of an ideal constant DCcurrent source will always be zero thus an ideal constant DC current sourcecan be replaced by an open circuit.For the gate drain connected FET device, the model is as shown in gure4.3.Since vds = vgs (the eective resistance = vgsvgsgm= 1gm)Figure 4.4 shows only the dierential input stage of the circuit. In gure4.1 M5 are replaced by current source Iss. The small signal analysis of theCHAPTER 4. DIFFERENTIAL INPUT STAGE 50Figure 4.3: MOSFET Resistor and Its Small Signal Modeldierential input stage can be accomplished with the assistance of the modelshown in gure 4.5 which is only appropriate for dierential analysis whenboth sides of the amplier are assumed to be perfectly matched. If thiscondition is satised, then the point where the two sources of M1 and M2are connected can be considered at AC ground. The body eect is neglected.Figure 4.4: CMOS Dierential Amplier using n-channel Input DevicesThe model in gure 4.6 is the simplied to the model shown in gure4.5. Since: M1 matches M2, M3 matches M4 (The point where S1, S2 ofM1, M2 are connected can be considered at AC ground.) Since S3, S4 areCHAPTER 4. DIFFERENTIAL INPUT STAGE 51Figure 4.5: The Exact Model for the CMOS Dierential AmplierAC ground, therefore S1, S2, S3, S4 can be joined up in a node.Figure 4.6: The Simplied Equivalent ModelReferring to gure 4.6:C1 = cgd1 +cgs3 +cgs4C2 = cgd2C3 = cgd4Any small signal on gate of M1 will result in a small signal current id1, whichwill ow from drain to source of M1.id1 = gm1 vgs1CHAPTER 4. DIFFERENTIAL INPUT STAGE 52and also be mirrored from M3 to M4gm4 vgs4 = id1Now since S1, S2, S3, S4 have the same potential (one node)id1 will also ow from the source to drain of M2. gm2 vgs2 = id1iout = id1(id1) = 2id1 (4.1)rout = ro2 ro4 (4.2)id1 = gm1 vgs1Since vgs1 = vgs2vid = vgs1 +vgs2Therefore, vid = 2vgs1id1vid= gm1vgs12vgs= gm12vid = 2id1gm1(4.3)Now the small signal output voltage is simply:vout = ioutrout (Substitute 4.1 and 4.2)vout = 2id1 (ro2ro4) (4.4)Now dividing 4.4 over 4.3 :voutvid= 2id1(ro2ro4)2id1gm1voutvid = gm1,2(ro2ro4) (4.5)Now:gm1,2 = (21,2ID1,2)12(ro2ro4)= 12ID,2(since r = 1I)Therefore,voutvid= (21,2ID1,2)12_ 12ID1,2_CHAPTER 4. DIFFERENTIAL INPUT STAGE 53voutvid= K _ W1,2L1,2ID1,2_12_1_K is a constant, uncontrollable by the designer. The eect of on thegain diminishes as L increases, such that 1 is directly proportional to thechannel length.Then a proportionality can be established between W1,2L1,2and the draincurrent versus the small signal gain such that:voutvid_W1,2L1,2ID1,2_12Therefore,small signal gain _W1,2L1,2ID1,2_12(4.6)The constant was not included since the value is not dependent on anythingthe designer can adjust.Conclusions:1. Increasing W1,2 , L1,2 or both increases the gain.2. Decreasing the drain current through M1, M2 which is also 12ID6 ,increases the gain.4.3 The Frequency ResponseReferring back to the model of the input stage: gure 4.6. We will work toeliminate all low impedance nodes (having high RC time):If,1c1 1gm3

1[c2 (ro2 ro4)]Then the node (D1=D2=G3=G4) is a low impedance node (with large RCtime) Now: c3 is assumed to be zero. In most applications of dierentialampliers, this assumption turns out to be valid. Then the model to beconsidered for the high frequency response analysis is turned to be as shownin gure 4.7.In the conguration where the small signal is applied to the gate of M4while the gate of M2 is grounded, vgs2 = 0, vid = vgs1. Now:gm4vgs4 = id1 = gm1vgs1 = gm1vidCHAPTER 4. DIFFERENTIAL INPUT STAGE 54Figure 4.7: High Frequency Small Signal Model with Parasitic CapacitorsNow redrawing the model in Figure 4.7 with the new parameters willresult in the model shown in Figure 4.8.Figure 4.8: Model of the Input Stage used to Determine the Frequency ResponseThe high frequency output can be given by:vo1 = gm1vid (ro2 ro4) 1_1 +S 1c2(ro2ro4)_The freq. Response = vo1vid = gm1 (ro2 ro4) 1_1 +S 1c2(ro2ro4_Now let us consider the input and the output stage shown in gure 4.9.The capacitor Cc in Figure 4.8 is removed for the purpose of the rstanalysis. C1, C2 represent the total lumped capacitance from each ground.Since the output nodes associated with each output is a high impedance,these nodes will be the dominant frequency dependent nodes in the circuit.Since each node in a circuit contributes a high frequency pole, the frequencyresponse will be dominated by the high impedance nodes.Figure 4.10 is the model derived for Figure 4.9 making use of Figure 4.8to determine the frequency response of the two-stage Op-Amp.To determine the exact value for c1, c2, Figure 4.11 shows the parasiticcapacitors explicitly for the input and the output stage which include thebulk depletion capacitors (cgb, csb, cdb) and the overlap capacitors (cgs, cgd).CHAPTER 4. DIFFERENTIAL INPUT STAGE 55Figure 4.9: Two Stage Op-Amp with Lumped Parasitic CapacitorsFigure 4.10: Model Used to Determine the Frequency Response of the Two-StageOp-AmpMiller theorem was used to determine the eect of the bridging capacitorcgd6 connected from the gate to drain of M6. Miller theorem approximatesthe eects of gate-drain capacitor by replacing the bridging capacitor withan equivalent input capacitor of value cgd(1+A2) and the equivalent outputcapacitor with a value of cgd(1 + 1A2). Where:CHAPTER 4. DIFFERENTIAL INPUT STAGE 56Figure 4.11: Two Stage Op-Amp with Parasitic Capacitors Shown ExplicitlyA2: gain across the original bridging capacitor and is, from gure 4.10:A2 = vovo1= gm6 vo1ro6ro7vo1A2 = gm6(ro6ro7) (4.7)Thus c1, c2 for g(10) can be determined by examining gure 4.11.c1 = cdb4 +cgd4 +cdb2 +cgd2 +cgs6 +cgd6 (1 +A2)c2 = cdb6 +cdb7 +cgd7 +cgd6_1 + 1A2_+cLNow assume c1 < c2 (the pole associated with the di-amp output_ 1c1(ro2ro4)_will be lower in frequency than the pole associated with the output of theoutput stage_ 1c2(ro6ro7)_.Also from the high frequency model gure 4.10:vovid=_ vovo1__vo1vid__ 11 + Sc2(ro6ro7)__ 11 + Sc1(ro2ro4)_CHAPTER 4. DIFFERENTIAL INPUT STAGE 57vovo1= gm6 (ro6 ro7) 1_1 + Sc2(ro6ro7)_vo1vid= gm1 (ro2ro4) _ 11 + Sc1(ro2ro4)_Therefore, the frequency responsevovid= [gm6 (ro6ro7)] [gm1 (ro2ro4)]_ 11 + Sc1(ro2ro4)__ 1(1 + Sc2(ro6ro7)_ (4.8)And the poles are:P1 = 1c1 (ro2ro4) (4.9)P2 = 1c2 (ro6ro7) (4.10)4.4 Phase MarginThe phase margin is the dierence between the phase at the frequency atwhich the magnitude plot reaches 0dB and the phase at the frequency atwhich the phase has shifted 180o. It is recommended for stability reasonsthat the phase margin of any amplier be at least 45o(60ois recommended).A phase margin below 45owill result in long settling time and increasedpropagation delay. The Op-Amp system can also be thought of as a simplesecond order linear control system with the phase margin directly aectingthe transient response of the system.Phase margin measurement procedure with the Cadence design tool, thephase margin can be measured by applying the following steps:1. Obtain the AC response simulation2. Delete all the outputs in the Arma window3. Select the AC response curve (it will turn to yellow).4. From the Arma window: Result direct plot AC magnitude andphaseCHAPTER 4. DIFFERENTIAL INPUT STAGE 585. Follow the prompt at the bottom of the schematic window and selectthe output node6. From the Arma window : output to be plotted7. You will get the magnitude and the phase frequency response. Splitthe graphs.Figure 4.12: Miller Phase Margin Measurement4.5 CompensationThe goal of the compensation task is to achieve a phase margin greater than45o. Now we will include Cc and the model will be as in Figure 4.13Keeping in mind that the two poles of the system without compensationas determined previously are:P1 = 1c1 (ro2ro4)CHAPTER 4. DIFFERENTIAL INPUT STAGE 59Figure 4.13: Model Used to Determine the Frequency Response of the Two-StageOp-AmpP2 = 1c2 (ro6ro7)Two results come from adding the compensation capacitor Cc:1. The eective capacitance shunting ro2ro4 is increased by the additiveamount of approximately gm1 ro2ro4 Cc. This moves P1 down bya signicant amount. Cc will dominate the value of c1 and will causethe pole P1 to roll o much earlier than without Cc to a new location.2. P2 is moved to a higher frequency.Let r1 = ro2ro4, r2 = ro6ro7,vovid=gm1gm6r1r2_1 S Ccgm6_1 +S [r1(c1 +Cc) +r2(c2 +Cc) +gm6r1r2] +S2r1r2 [c1c2 +Cc(c1 +c2)](4.11)A general second order polynomial can be written as:P(S) = 1 +aS +bS2=_1 SP1__1 SP2_ = 1 S_ 1P1+ 1P2_+ S2P1P2If | P2 || P1 | then:P(S) = 1 SP1+ S2P1P2CHAPTER 4. DIFFERENTIAL INPUT STAGE 60Therefore, P1, P2 may be written in terms of a, b as:P1 = 1aP2 = abThe key in this technique is the assumption that the magnitude of the rootP2 is greater than the magnitude of the root P1P1 = 1r1(c1 +Cc) +r2(c2 +Cc) +gm6r1r2CcP1 = 1gm6r1r2CcP2 = r1(c1 +Cc) +r2(c2 +Cc) +gm6r1r2Ccr1r2(c1c2 +Cc(c1 +c2))P2 = gm6Ccc1c2 +c2Cc +c1CcP2 = gm6c2(4.12)The second pole should not begin to aect the frequency response until afterthe magnitude response is below 0dB.It is of interest to note that a zero occurs in the right-hand-plane (RHP)due to the feed forward path through Cc. The RHP zero is located at:Z1 = gm6Cc(4.13)This RHP zero has negative consequences on our phase margin, causing thephase plot to shift 180omore quickly. To avoid the eect of RHP zero, onemust try to move the zero well beyond the point at which the magnitudeplot reaches 0dB (suggested rule of thumb: factor of 10 greater)4.6 Adding Rz in series with CcOne remedy to the zero problem is to add a resistor Rz in series with CcZ1 = 1_Cc_ 1gm6Rz__ (4.14)CHAPTER 4. DIFFERENTIAL INPUT STAGE 61And the zero can be pushed into the LHP where it adds phase shifts andincreases phase margin if:Rz > 1gm6(4.15)The zero location is in the RHP, when Rz = 0. As Rz increases invalue, the zero gets pushed to innity at the point at which Rz = 1gm6.Once Rz > 1gm6, the zero appears in the LHP where its phase shifts adds tothe overall phase response. Thus improving the phase margin. This type ofcompensation is referred to as lead compensation and is commonly used as asimple method for improving the phase margin. One should be careful aboutusing Rz, since the absolute values of the resistors are not well predicted.The value of the resistor should be simulated over its max and min values toensure that no matter if the zero is pushed into the LHP or RHP, that valueof the zero is always 10 times greater than the gain bandwidth product.4.7 Gain Bandwidth ProductGBW for the compensated Op-Amp is the open loop gain multiplied by thebandwidth of the amplier (as set by P2).GBW = gm1r1gm6r2_ 1gm6r1Ccr2_GBW = gm1Cc(4.16)GBW _ID1,2 W1,2L1,2_12CcTherefore, the most ecient way to increase GBW is to decrease Cc.The value of Cc must be large enough to aect the initial roll-o frequencyas larger Cc improves phase margin. Therefore, to know the value of Cc:1. We need to know the GBW specication.2. Iteratively choosing the values for W1,2L1,2and ID1,2 and then solving forCc.Conclusions:P2 should be > GBW Therefore, gm6c2> gm1,2CcCc > C2_gm1,2gm6_ (4.17)CHAPTER 4. DIFFERENTIAL INPUT STAGE 62Practically speaking, the load capacitor usually dominates the value of c2,so c2 = cLCc > cL_gm1,2gm6_ (4.18)Therefore, the eect of cL on phase margin is as follows: Minimum size ofCc directly depend on the size of cL. For example if the zero is 10 timeslarger than GBW, then in order to achieve a 45ophase margin, P2 must beleast 1.22 times higher than GBW. And to get a phase margin of 60oP2must be 2.2 times greater than GBW.4.8 Large Signal ConsiderationAnalysis and design can be greatly simplied by separating DC or biascalculations from small signal calculations. That is once a stable operatingpoint has been established and all DC quantities are calculated, we maythen perform AC analysis. Figure 4.14 shows the large signal equivalentcircuit model for n-channel MOSFET in saturation. The model for p-channelCMOS is similar except for K

p instead of K

n.Figure 4.14: Large-Signal Equivalent Circuit Model in SaturationFor N-channel MOSFET to be in saturation:1. VGS Vt2. VDS (VGSVt)And the drain saturation current is given by:ID = 12 Kn WL (VGSVt)2CHAPTER 4. DIFFERENTIAL INPUT STAGE 63If = K

n WL Then,ID = 12 (VGSVt)2(4.19)For P-channel MOSFET to be in saturation:1. VGS Vt2. VDS (VGSVt)Equation 4.19 can be written as:VGS =_2ID_12+Vt (4.20)For the N-channel:1. VDS (VGSVt). Now by substituting VGS:2. VDS _2ID_12The large signal characteristics that are important include the Common-mode range, slew rate, and output signal swing4.9 Slew RateThe slew rate is dened as the maximum rate of change of the output volt-age due to change in the input voltage. For this particular amplier, themaximum output voltage is ultimately limited by how fast the tail currentdevice M5 can charge and discharge the compensation capacitor, the slewrate can then be approximated as:SR = dVodtSR ID5CcTypically, the di-amp is the major limitation when considering slewrate. However, the tradeo issues again come into play. If ID5 is increasedtoo much, the gain of the di-amp may decrease below a satisfactory amount.If Cc is made too small then the phase margin may decrease below anacceptable amount.CHAPTER 4. DIFFERENTIAL INPUT STAGE 644.10 The Common-Mode RangeCommon-mode range is dened as the range between the maximum andminimum common-mode voltages for which the amplier behaves linearly.Referring to 4.15, suppose that the common mode voltage is DC value andthat the dierential signal is also shown. If the common mode voltage isswept from ground to VDD, there will be a range for which the amplierwill behave normally and where the gain of the amplier is relatively con-stant. Above or below that range, the gain drops considerably because thecommon-mode voltage forces one or more devices into the triode region.The maximum common-mode voltage is limited by both M1 and M2going into triode. This point can be dened by a borderline equation inwhich(For M1, M2 to stay in saturation)VD1,2 (VG1,2Vt1)Now:VD1 = VDDVSG3Therefore,VG1 VDDVG3 +Vt1Substitute the value of VGS from equation 4.20 and Vt3 = ve value becauseit is p type CMOS:VG1 VDD_2ID33_12Vt3 +Vt1Now since ID3 = 12ID5:VG1 VDD_ID53_12Vt3 +Vt1 (4.21)VG1 VDD_L3ID5W3K3_12Vt3 +Vt1 (4.22)The minimum voltage is limited by M5 being driven into non-saturationby the common-mode voltage source.VD5 VSS +VG5Vt5VD5 = VG1,2VGS1,2CHAPTER 4. DIFFERENTIAL INPUT STAGE 65Therefore,VG1,2VGS1,2 VSS +VG5Vt5VG1,2 VSS +VG5Vt5 +VGS1,2Since, VGS =_2ID_12+Vt (From 4.20)Therefore,VG1,2 VSS +_2ID55_12+_ID51_12+Vt5V t5 +Vt1VG1,2 VSS +_2ID55_12+_ID51_12+Vt1VG1,2 VSS +_2L5ID5W5K5_12+_L1ID5W1K1_12+Vt1 (4.23)Determining the CMR for the two-stage Op-Amp (Figure 4.15).Figure 4.15: Determining the CMR for the Two-Stage Op-AmpCHAPTER 4. DIFFERENTIAL INPUT STAGE 664.11 Important Relationships for The DesignRelate W3, W4 to W5 M3, M4 carry half of Itail , then the widths of M3 andM4 can be determined by assuming that vsg3 = Vsg4 = Vgs5. Using 16:Id3,4Id5= 0.5KP_WL_3,4_Vgs3,4V2t_0.5Kn_WL_5 (Vgs5Vt) KP_WL_3,4Kn_WL_5And since L3 = L5 and Kn = 3Kp, then that leads to the conclusionthat:W3,4 = 1.5W5 (4.24)Therefore, the width of M3, M4 can be determined in terms of W5.Relate W6, W7 to W5. The values for M6 and M7 are determined by theamount of load capacitance attached to the output. If a large capacitance ispresent, the width of M6 and M7 will need to be large so as to provide enoughsinking and sourcing current to and from the load capacitor. Suppose it wasdecided that the current needed for M6 and M7 was twice that of M5. Then:W7 = 2W5 (4.25)W6 = 6W5(Because W6 is P-Type so to account for the dierence K values)4.12 Tradeos for Increasing the Gain of the TwoStage Op-Amp.Using the equations in the summary above, the tradeo issues for increasingthe gain of the two stage Op-Amp are summarized in the following table.We wish to... Thus we could... Some Secondary eects are...Increase DC gain Increase WL1,2 Decrease phase marginIncrease GBWIncrease CMRDecrease ID5 Decrease SRIncrease CMRIncrease CMRRIncrease phase marginIncrease WL6 Increase phase marginIncrease output swingDecrease ID6 Decrease output currents driveDecrease phase marginCHAPTER 4. DIFFERENTIAL INPUT STAGE 674.13 Design Methodology for the Two Stage Op-AmpDesign methodology is a topology dependent subject and it is highly depen-dent on the analysis of the circuit. The purpose on the design tool is notto replace the analysis completely. The analysis rather guides the designersthoughts and while doing the design and helps to make the results of thedesign tool make sense.The following design methodology is developed for the two stage Op-Ampanalyzed above.1. To dene the requirements, set the specications, and dene the bound-ary conditions. Boundary conditions The TSMC 0.35 CMOS Technol-ogy is used. Process specications: Vt , K

, Cox, ..etc. Because thereare 12 models for N-FET and 12 models for P-FET automaticallyselected within Cadence tool so the process parameters cannot be de-termined at this stage.Supply voltage: 0 3.3 V Operating temperature: 0 to 70oC,Requirements, Gain, GBW, CMRR Slew rate, Input common moderange: Vin(min), Vin(max), Output voltage swing: Vout(max), Vout(min),PSRR, Oset, Output Load.2. Choose the smallest length that will keep the channel modulation pa-rameter ( constant and give good matching for current mirrors. Thevalue used is 350nm3. Design the two stages without Cc, Rz, or CL, for the best dc response.Design the devices sizes for proper dc performance. It is importantthat before any AC analysis is performed, the values of the DC pointsin the circuit be checked to ensure that every device is in saturation.Failure to do so will result in very wrong answers. This step is accom-plished as follows:(a) Calculate the minimum value for the compensation capacitor Cc.From 40: Cc 0.22 CL. Get CL from the requirements(b) Get the slew rate from the requirement and then calculate theminimum value for the tail current ID5 from: ID5 = SR. CcCHAPTER 4. DIFFERENTIAL INPUT STAGE 68(c) Using cadence design tool, simulate the two stage amplier withstarting widths of: 800nm for n type devices, 1.9m for p typedevices. Get the circuit to work and test the DC response.(d) Measure ID5. Now try to optimize the Op-Amp for maximumgain by:i. Measure the existing ID5. To get the desired value of ID5calculated in B, simultaneously change W5 and the width ofthe related devices:W3,4 = 1.5W5W6 = 6W5W7 = 2W5ii. Check the operating points of all the devices (M1, M2, M3,M4, M5, M6, and M7) to make sure that the devices are insaturation. All design parameters can be known from Ca-dence by doing the following:Arma Window: Results Print DC Operating Pointsiii. Increase the gain by increasing the size of W1,2. You mayperform parametric analysis for dierent width size. Youcan not decide on the nal value of W1,2 at this point evenyou may get high gain, because of the trade o issues andthe secondary eect, particularly on the phase margin whichcan not be measured till the ac analysis is performed.iv. At this point you can extract the process parameters: Vt, K, Cox...etc. Knowing K for the devices is now important to calcu-late VG(min) and VG1(max) to make sure that M1, M2, M3,M4 and M5 are not operating near the boundary, 4.22,4.23causing one of the devices to operate outside the saturationregion.v. If any of the devices are brought out of saturation or areworking at the minimum condition required for saturation,then it should be brought back to saturation.vi. Repeat 1-4 until all the transistors are in saturation whilethe dc gain is increased.CHAPTER 4. DIFFERENTIAL INPUT STAGE 69(e) Measure the CMR and the gain. Compare with the requiredspecications.4. (a) Add up Cc and CL to the amplier. The value of CL is fromthe specications while the value of Cc is previously calculated inStep3-A(b) Check the phase margin condition (4.18), as now you can knowall the process parameter from cadence.(c) Verify that the phase margin is > 45oby measuring it using theprocedure in 4-4.(d) If the phase margin is not > 45othen it should be correctedby changing the value of Cc or R2, referring to (4.15, 4.18). Aparametric analysis may be preformed for dierent Cc sizes.(e) Calculate the slew rate according to the new Cc value that makesthe phase margin > 45o. If it is less than the specication thenperform the following steps:i. Calculate the required ID5 from (22). Substitute the lastvalue of Cc and the required SR.ii. Perform DC analysis only and return back to Step3-D, withthe desired value of ID5 as calculated above.5. (a) Calculate the required Rz using (4.14)(b) Add Rz to the circuit and perform an AC analysis. Check thedierence in the phase response.6. Measure the slew rate, GBW, P2 and the phase margin. Comparewith the specications.4.14 Design ExampleFigure 4.16 shows a two stage op-amp designed using the above designmethodology and optimized for maximum gain. Figure 4.17 shows the gainfor the large signal consideration(DC response). Figure 4.18 shows the fre-quency response. Figure 4.19 shows the phase margin measurements.CHAPTER 4. DIFFERENTIAL INPUT STAGE 70Figure 4.16: Two-Stage Op-Amp using design MethodologyFigure 4.17: Gain for the Large Signal AnalysisCHAPTER 4. DIFFERENTIAL INPUT STAGE 71Figure 4.18: Frequency ResponseFigure 4.19: Phase MarginCHAPTER 4. DIFFERENTIAL INPUT STAGE 724.15 Limitations of the Two Stage Op-Amp1. Insucient gain2. Limited stable bandwidth caused by the instability to control thehigher order poles of the op-amp.3. Poor power supply rejection ratio.4.16 The Cascode Op-AmpThe motivation for using the cascode conguration to increase the gain canbe seen by examining how the gain of the two-stage op-amp could be in-creased. There are three ways in which the gain of the two stage op-ampcould be increased:1. Add additional gain stage2. Increase the transconductance of the rst or the second stage.3. Increase the output resistance seen by the rst or second stage.Due to possible instability, the rst approach is not attractive. Of thelatter two approaches, the third is the more attractive way because the out-put resistance increases in proportion to a decrease current [ ro = 1/ ],whereas the transconductance increases as the square root of the increase inbias current [ gm = (2 B ID)1/2]. Thus it is generally more ecient toincrease ro rather than gm.Figure 4.20 shows a cascode dierential stage. Figure 4.21 shows theDC response for an unoptimized conguration to serve as indication forthe whole project and to help in deciding about the best input stage to beconsidered in the nal op-amp design. The transistors Mc1 and Mc2 performthe resistance multiplication, while Mc3 is used to keep the drain voltage ofthe input transistor matched, which helps to reduce the voltage oset.Rout ( [gmc2 . roc2 . ro4 ] [ gmc1. roc1. ro2 ]. A = gm1.RoutOne of the disadvantages of this design is the requirement for the addi-tional bias voltages VB1, VB2. Further more, the common mode input rangeis reduced due to the extra voltage drop required by the two cascode devices,Mc1, Mc2. In many cases, the CMR limitation is not important since thenon-inverting input of the op-amp will be connected to ground.CHAPTER 4. DIFFERENTIAL INPUT STAGE 73Figure 4.20: Cascode Dierential StageFolded Cascode Op-Amp Figure 4.22 shows a folded cascode dierentialstage. Figure 4.23 shows the DC response for an unoptimized congur