Trends and Updates
Greg Rocco, MIT Lincoln Laboratory
14 January 2020
This work is sponsored by the Department of the Air Force under Air Force Contract #FA8702-15-D-0001. Opinions, interpretations, conclusions and recommendations are those of the author and are not necessarily endorsed by the United States Government.
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
Trends in OpenVPX – Slide 214 January, 2020
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
Outline
• OpenVPX and associated standards
• Relationship of OpenVPX with other standardization efforts
• OpenVPX plans and trends
• Improving interoperability by reducing number of voltages used– Slot Profiles added by ANSI/VITA 65.0-2019 only use 12 VDC, 3.3V_AUX,
and VBAT
• Improving interoperability by minimizing User Defined pins– Of the five 6U and six 3U Slot Profiles added by ANSI/VITA 65.0-2019, only
one 6U and one 3U has User Defined pins
J3
J4
J5
J6
J1
J2
J0
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DiffP6/J6
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DiffP5/J5
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DiffP4/J4
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DiffP3/J3
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DiffP2/J2
SE Diff
P1/J1
SEP0/J0
Key
Key
Key
Backplane picture courtesy of Elma
Some of these slides were taken from the OpenVPX Tutorial. The full Tutorial as well as some others is available at: http://www.vita.com/Tutorials
Trends in OpenVPX – Slide 314 January, 2020
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
OpenVPX and Associated Standards
• These standards define interfaces between Plug-In Modules and chassis for products intended to be deployed in harsh environments
Pictures courtesy of Elma
Chassis front panel
Channels for cooling air
Mechanical/cooling interface between Plug-In and Chassis interface specified by VITA 48
Electrical interface between Plug-In Module and backplane specified by OpenVPX (VITA 65)
3U x 160 mm (3.9 x 6.3”) Plug-In Module
Conduction cooled chassis
Trends in OpenVPX – Slide 414 January, 2020
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
Relationship of OpenVPX to Other Standardization Efforts
• For what goes into OpenVPX, continuing to get input from:– SOSA (Sensor Open Systems Architecture) Hardware Working Group– HOST (Hardware Open Systems Technology) community of both those working
on it and those using it– Army C5ISR Center’s CMOSS (C4ISR/EW Modular Open Suite of Standards)
Community thru their influence of SOSA
• Also taking input from VITA 65 Working Group back to SOSA– Several of us participate in both VITA and SOSA
• In SOSA we have discussions, which are ITAR controlled, to come up with best solutions in relation to target applications – The VITA Standards Organization is international, so we cannot have discussions
involving ITAR controlled and other sensitive information
• Working to align SOSA, HOST, CMOSS and OpenVPX– In terms of Slot and Module Profiles, expect SOSA, HOST, and CMOSS to
continue to point at a subset of OpenVPX
Trends in OpenVPX – Slide 514 January, 2020
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
OpenVPX Plans and Trends
• New version of OpenVPX™ Published November 2019– ANSI/VITA 65.0-2019, OpenVPX™ System Standard; November 2019– ANSI/VITA 65.1-2019, OpenVPX™ System Standard – Profile Tables; November 2019
• Working to further improve interoperability– Moving ecosystem toward Plug-In Modules only using 12 VDC, 3.3V_AUX and VBAT– Most of the new Slot Profiles have no UD (User Defined) pins
• Of the five 6U and six 3U Slot Profiles added by ANSI/VITA 65.0-2019, only one 6U and one 3U has UD pins
– Intended that where User Defined pins needed, restrict them to a few specific slots
• The VITA 65 Working Group is working on the next version, expect:– To add higher density optical and coax blind mate (backplane) connector– Additional Module Profiles using 100 Gbit Ethernet (both optical and copper)
• ANSI/VITA 65.1-2019 only has a few using 100 Gbit Ethernet over optical and none over copper
– Continue trend of avoiding User Defined pins with most new Slot Profiles– To be published in 2020 or early 2021
Trends in OpenVPX – Slide 614 January, 2020
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
Recommend 12 VDC Only for Plug-In Module Power
• Plug-In Modules using multiple supplies makes it more difficult to interchange boards– If have chassis full of Plug-In Modules using primarily 5 VDC and then change to
ones using primarily 12 VDC, will probably need to change power supply also.
• With ANSI/VITA 65.0-2019 have Recommendations for Plug-In Modules to only use 12 VDC, 3.3V_AUX, and VBAT– In ANSI/VITA 65.0-2019 see Sections 3.2.1 and Section 8.8
• Backplanes still required to have distribution busses for all supplies– Up to system integrators as to how much power to make available on each buss
• Slot Profiles added to ANSI/VITA 65.0-2019 decide on a Slot Profile by Slot Profile basis whether a given Slot Profile’s Module Profiles will be 12 VDC, 3.3V_AUX, and VBAT only– All the ones added only use 12 VDC, 3.3V_AUX, and VBAT
• Intent of recommendations is to gradually migrate the ecosystem to 12 VDC, 3.3V_AUX, and VBAT only – Some end customers might require this for all Slot Profiles used in their system.
6U Plug-In Module Power Supplies
Pin name 2017 usageRecommended starting in 2019
VS1VS2VS3 +5 VDC Not used+12V_AUX +12 VDC Not used-12V_AUX -12 VDC Not used3.3V_AUX +3.3 VDC +3.3 VDCVBAT +3 VDC +3 VDC
3U Plug-In Module Power Supplies
Pin name 2017 usageRecommended starting in 2019
VS1 +12 VDC +12 VDCVS2 +3.3 VDC Not usedVS3 +5 VDC Not used+12V_AUX +12 VDC Not used-12V_AUX -12 VDC Not used3.3V_AUX +3.3 VDC +3.3 VDCVBAT +3 VDC +3 VDC
+12 VDC +12 VDC
Trends in OpenVPX – Slide 714 January, 2020
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
6U Slot Profiles Added by ANSI/VITA 65.0-2019
• Module Profiles for these Slot Profiles only use the following for power from the backplane:– 12 VDC (VS1 and VS2)– 3.3V_AUX– VBAT
• SLT6-PAY-4U2U-10.2.8 is the only one of these with UD (User Defined) pins
SE
DiffP2/J2
SE Diff
P1/J1
SEP0/J0
P6/J667.3C
P3/J367.3C
SE
DiffP5/J5
DiffP4/J4
SE
SLT6-PAY-. . .-10.6.3-n
SEP0/J0
DiffP1/J1
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SLT6-PAY-4U2U-10.2.8
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P1/J1
SEP0/J0
P6/J667.3C
P3/J367.3C
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DiffP4/J4
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SLT6-PAY-. . .-10.6.4-n
DiffP2/J2
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P1/J1
SEP0/J0
P6/J667.3C
P3/J367.3C
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DiffP4/J4
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P5/J567.3C
SLT6-PAY-. . .-10.6.5-n
SE Diff
P1/J1
SEP0/J0
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DiffP4/J4
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P6B/J6B
DiffP5/J5
DiffP6A/J6A
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SLT6-SWH-. . .-10.8.1
Trends in OpenVPX – Slide 814 January, 2020
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
3U Slot Profiles Added by ANSI/VITA 65.0-2019
• Module Profiles for these Slot Profiles only use the following for power from the backplane:– 12 VDC (VS1)– 3.3V_AUX– VBAT
• SLT3-PAY-2U2U-14.2.17 is the only one of these with UD (User Defined) pins
SESE Diff
P2/J2
SEP0/J0
DiffP1/J1
SE
SLT3-PAY-. . .-14.2.16
SE
SEP0/J0
DiffP1/J1
67.3D
SLT3-PAY-. . .-14.6.13
SEP0/J0
67.3E
SE
DiffP1A/J1A
SLT3-PAY-. . .-14.6.14
SEP0/J0
67.3C
DiffP1/J1S
E
SLT3-PAY-. . .-14.9.2
SEP0/J0
DiffP1/J1
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DiffP2/J2
SLT3-PAY-2U2U-14.2.17
SE
SE
SEP0/J0
Diff
P1/J1
DiffP2/J2
SLT3-SWH-6F8U-14.4.15
Trends in OpenVPX – Slide 914 January, 2020
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
Isolating User Defined Pins to a Small Number of Slots
• Use network interfaces forcontrol when practical– Avoid using discretes
(individual signals) asmuch as practical
• Many applications will requireuse of discretes
• These Slot Profiles are intended forSBCs (Single Board Computers) with XMC sites– 6U also intended for other applications such as RF input/output
• Drive system specific pins, such as discretes, using XMC– XMC can be system specific and stay with the platform as SBC upgraded– Use XMC for driving legacy signals
• If all the needed system specific pins do not fit available XMC sites use Slot Profiles with lots of UD pins
Maint. Port1 GPIO
1 GPIO
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DiffP2/J2
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P1/J1
SEP0/J0
Control Plane — 2 TPControl Plane — 2 UTPs
Utility Plane
Utility Plane
P6/J667.3C
VITA 65 Aperture Pattern H for optical/coax
Key
Expansion Plane — 32 pairs
Data Plane — 4 FPs
Key
Key
P3/J367.3C
SE
6 GPIO
DiffP5/J5
DiffP4/J4
Video lanes & clock — 1 TPStorage — 4 UTPs
VITA 65 Aperture Pattern H for optical/coax
X8d XMC mapX24s XMC map
P5w1-X24s+X8d+X12d
2 of USB — 1 TUTP
Serial Port(s)
Serial Port(s)
Video Aux & GP LVDS — 1 SP, 1 SPSE
X12d XMC map
Vid PWR,HPDUSB PWR
Maint. Port
2 GPIO
2 AXresets
2 GP LVDS
SESE
Control Plane — 2 UTPs
Expansion Plane — 1 FPUtility Plane
Key
DiffP2/J2
SEP0/J0
DiffP1/J1
3 of GPIO
Utility PlaneGPIO
Maint. Port
Key
X16s XMC mapX8d XMC map
Data Plane — 1 FP
P1w9-X12d XMC mapUSB PWRSE
Serial ports1 of USB 3 and 1 of USB 2 — 1 TP
USB PWR
Video — 1 TUTP
Storage — 1 UTPControl Plane – 1 TP
SLT6-PAY-4F1Q1H4U1T1S1S1TU2U2T1H-10.6.3-n SLT3-PAY-1F1F2U1TU1T1U1T-14.2.16
Trends in OpenVPX – Slide 1014 January, 2020
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
Slot Profiles with Lots of User Defined Pins
• If cannot fit the required system specific pins on XMCs use theseSlot Profiles– SOSA refers to these Slot Profiles as being for system specific interfaces
• Get all the User Defined pins driven by a few slots
• Intended for one of two use models:1. Subservient to other Plug-In Module(s) via Expansion Plane2. Able to receive commands from many Plug-In Modules via Control Plane
SEP0/J0
Expansion Plane —2 Ultra-Thin Pipes
User Defined
User Defined
DiffP1/J1
Control Plane —2 Ultra-Thin Pipes
Utility Plane
Utility PlaneUser Defined
Maint. PortUser Defined
SE
SE
DiffP2/J2User Defined
Key
KeySLT6-PAY-4U2U-10.2.8 SLT3-PAY-2U2U-14.2.17
Key
Control Plane —2 Ultra-Thin Pipes
Key
KeySE
P0/J0Expansion Plane — 4 Ultra-Thin Pipes
User Defined
DiffP1/J1
Utility Plane
Utility PlaneUser Defined
Maint. PortUser Defined
SE
SE
DiffP2/J2
User Defined
User Defined
User Defined
SE
DiffP6/J6
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DiffP5/J5
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DiffP4/J4
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DiffP3/J3
Trends in OpenVPX – Slide 1114 January, 2020
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
Summary
• ANSI/VITA 65.0-2019 and 65.1-2019 were published November 2017– All the new Slot Profile have Module Profiles requiring only 12 VDC, 3.3V_AUX, and
VBAT be used
• User Defined pins can inhibit interoperability– Most of the new Slot Profiles have no User Defined pins
• SOSA, HOST, and CMOSS communities being used to get input for next revision of OpenVPX standards
• The VITA 65 Working Group is working on the next version
J3
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J0
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DiffP4/J4
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DiffP3/J3
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DiffP2/J2
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P1/J1
SEP0/J0
Key
Key
Key
Backplane pictures courtesy of Elma
