External I2C
User Guide
01/2013
Capital Microelectronics, Inc.
China
User Guide of External I2C
http://www.capital-micro.com 2
Contents
Contents ............................................................................................................................................... 2
1 Introduction ................................................................................................................................... 3
2 External I2C Overview .................................................................................................................. 4
2.1 Pin Description ........................................................................................................................ 4
2.2 Block Diagram ......................................................................................................................... 5
2.3 I2C internal registers ............................................................................................................... 5
3 External I2C IP Usage................................................................................................................. 11
3.1 Serial clock generator ............................................................................................................ 11
3.2 Master Transmitter mode ....................................................................................................... 11
3.3 Master Receiver mode .......................................................................................................... 12
3.4 Slave Receiver mode ............................................................................................................ 12
3.5 Slave Transmitter mode ........................................................................................................ 12
3.6 Interrupt generation .............................................................................................................. 13
3.7 External memory interface (EMIF) operation ....................................................................... 13
3.8 Interrupt operation................................................................................................................. 15
3.9 Resource usage and performance analysis ......................................................................... 16
4 Generate File Directory Structure ............................................................................................. 17
Revision History ................................................................................................................................ 19
User Guide of External I2C
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1 Introduction
This document mainly describes the usage of the External I2C IP. This External I2C IP basically has
the same behavior like 8051’s internal I2C. The IP provides the interface to EMIF (External Memory
Interface) of 8051 core in CME FPGA and can be programmed to work as master or as slave. The
External I2C IP supports the following features:
Comply to Philips I2C bus specification
Support multiple bit rate
—standard mode, up to 100kbit/s
—fast mode, up to 400kbit/s
—user-defined bit rate
Operating modes
—Master Transmitter Mode
—Master Receiver Mode
—Slave Transmitter Mode
—Slave Receiver Mode
Support 7-bit slave address
Device family support:
CME-M5, CME-HR3
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2 External I2C Overview
2.1 Pin Description
Table 2-1 External I2C Interface
Interface Name Direction Width Description
System clk Input 1 Clock input
bclk Input 1 Baudrate clock input
rst_n Input 1 Reset input, low active
User
interface
scli Input 1 Receive clock input
sdai Input 1 Receive data input
sclo Output 1 Transmit clock output
sdao Output 1 Transmit data output
Memory
interface
with
MCU
memaddr Input 23 8051 ext-memory address
memdatai Input 8 8051 ext-memory data input
memdatao Output 8 8051 ext-memory data output
memwr Input 1 8051 ext-memory write enable
memrd Input 1 8051 ext-memory read enable
memack Output 1 8051 ext-memory acknowledge
Interupt irq Output 1 Interupt to 8051
intack Input 1 Interupt acknowledge(optional)
Note: to dessert the “irq” signal, user could set I2CCON.3 to 0 or assert “intack” to high level. For 8051 io
resources saving, it is recommended to set I2CCON.3 to 0 leaving “intack” low-level.
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2.2 Block Diagram
Addr Register
Addr Comparator
Shift Register
Arbitration &
Synchronization Logic
Serial Clock Generator
Control Register
Status Register
sfrwe
sfraddr
sfrdatai
sfrdatao
i2cadr
i2cdat
i2ccon
i2csta
Address
Mapping
memwr
memrd
memaddr
memdatai
memack
memdatao
irq
bclk
sdai
sdao
scli
sclo
i2c_core
Figure 2-1 External I2C IP block diagram
The I2C IP includes 2 sub modules: addr_mapping and i2c_core.
addr_mapping:
This module is used to map memory address to I2C IP internal register address. The base address of
I2C IP can be set by user. But each internal register’s offset address can’t be changed.
i2c_core:
This module the core control module of I2C, which includes: baud rate generator, internal registers,
control logic, transmit shift register, receive shift register, output logic and input logic.
2.3 I2C internal registers
The I2C contains totally 4 internal registers: Data Register(I2CDAT), Address Register(I2CADR),
Control Register (I2CCON), Status Register I2CSTA (I2CSTA). All these registers are shown below:
Table 2-2 All Internal Registers
memaddr[22:0] Registers Comment Access Type
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Base+0 I2CDAT I2C Data Register R/W
Base+1 I2CADR I2C Address Register R/W
Base+2 I2CCON I2C Control Register R/W
Base+3 I2CSTA I2C Status Register R/W
External I2C IP internal register base address requirements
The base address of the I2C IP is a parameter (BASE_ADDR), it can be set through IP wizard. The
BASE_ADDR width is 23 bits.
Requirements:
1、 BASE_ADDR >= 23’h02_0000 (128KB), since CME-M5 has 128KB on-chip SRAM
2、 To save address decoder logic resource usage, the lower 4 bits of the BASE_ADDR is used for
internal register’s offset, So BASE_ADDR[3:0] should always keep as 4’b0000
I2C Data Register – I2CDAT
Reset value: 00h
The I2CDAT register contains a byte to be transmitted through I2C bus or a byte which has just been
received through I2C bus. The CPU can read from and write to this 8-bit, directly addressable EMIF
Register while it is not in the process of byte shifting. The I2CDAT register is not shadowed or double
buffered so the user should only read I2CDAT when an I2C interrupt occurs.
I2C Address Register –I2CADR
The I2CADR register holds the own address of external I2C slave interface. This address is used to
recognize if a device is attempting to access the external I2C as slave via I2C bus. I2CADR register is
allocated in the EMIF memory space when external I2C is selected during IP core configuration.
Table 2-3 I2CADR Register
Reset value: 00h
Bit Symbol Description Access Type
i2cadr.7 adr Own I2C slave address (7 bit)
R/W
i2cadr.6
i2cadr.5
i2cadr.4
i2cadr.3
i2cadr.2
i2cadr.1
i2cadr.0 gc General Call Address Acknowledge
If this bit is set, the general call address is
recognized; otherwise it is ignored.
R/W
I2C Control Register –I2CCON
The I2CCON register controls the operation of I2C interface. The CPU can read from and write to this
8-bit, directly addressable EMIF Register. Two bits of this register are affected by the I2C hardware:
the si bit is set when serial interrupt is requested, and the ―sto‖ bit is cleared when STOP condition is
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present on the I2C bus.
Table 2-4 I2CCON Register
Reset value: 00h
Bit Symbol Description Type
i2ccon.7 cr2 Clock rate bit 2 R/W
i2ccon.6 ens1
I2C enable bit
When ens1=’0’ the “sdao” and “sclo” outputs are set to 1, that drives the
output pads of the chip in high impedance, and “sdai” and “scli” input
signals are ignored.
When ens1=’1’ I2C component is enabled.
R/W
i2ccon.5 sta
START Flag
When sta=’1’, the I2C component checks the I2C bus status and if the bus
is free a START condition is generated.
R/W
i2ccon.4 sto
STOP Flag
When sto=’1’ and I2C interface is in master mode, a STOP condition is
transmitted to the I2C bus.
R/W
i2ccon.3 si
Serialn Iterrupt Flag
The “si “is set by hardware when one of 25 out of 26 possible I2C states is
entered (2.4.46 ). The only state that does not set the “si” is state F8h,
which indicates that no relevant state information is available. The “si” flag
must be cleared by software. In order to clear the “si” bit, ‘0’ must be
written to this bit. Writing a ‘1’ to si bit does not change value of the “si”.
R/W
i2ccon.2 aa
Assert Acknowledge Flag
When aa=’1’, an “acknowledge” will be returned when:
- the “own slave address” has been received
- the general call address has been received while gc bit in i2caddr register
was set
- a data byte has been received while I2C was in master receiver mode
- a data byte has been received while I2C was in slave receiver mode
When aa=’0’, an “not acknowledge” will be returned when:
- a data byte has been received while I2C was in master receiver mode
- a data byte has been received while I2C was in slave receiver mode
R/W
i2ccon.1 cr1 Clock rate bit 1 R/W
i2ccon.0 cr0 Clock rate bit 0 R/W
I2C Status Register –I2CSTA
The contents of this register reflect the actual state of external I2C interface. The I2CSTA register is
allocated in the EMIF memory space when external I2C is selected during IP core configuration.
Table 2-5 I2CSTA Register
Reset value: F8h
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Bit Symbol Description Type
i2ccon.7
i2ccon.6
i2ccon.5
i2ccon.4
i2ccon.3
-
I2C Status Code
R
i2ccon.2
i2ccon.1
i2ccon.0
-
Not implemented, read as 0
R
The ―i2csta‖ register reflects the state of the main FSM of the I2C component. The three least
significant bits of this register are always zero. There are 26 possible status codes, which are
presented in Table 2.5 … Table 2.9. When one of the 25 out of 26 possible I2C FSM states is entered,
an interrupt is requested. The only state that does not generate an interrupt is the F8h state.
In the table below, referring to ―SLA‖ means slave address, ―R‖ means R/W bit=1 transferred together
with the slave address, ―W‖ means R/W bit=0 transferred together with the slave address.
Table 2-5 I2C Status in Master Transmitter Mode
Status Code Status of the I2C
08H A START condition has been transmitted
10H A repeated START condition has been transmitted
18H SLA+W has been transmitted; ACK has been received
20H SLA+W has been transmitted; not ACK has been received
28H Data byte in i2cdat has been transmitted; ACK has been received
30H Data byte in i2cdat has been transmitted; not ACK has been received
Table 2-6 I2C Status in Master Receiver Mode
Status Code Status of the I2C
08H A START condition has been transmitted
10H A repeated START condition has been transmitted
40H SLA+W has been transmitted; ACK has been received
48H SLA+W has been transmitted; not ACK has been received
50H Data byte has been received; ACK has been returned
58H Data byte has been received; not ACK has been returned
Table 2-7 I2C Status in Slave Receiver Mode
Status Code Status of the I2C
60H Own SLA+W has been received; ACK has been returned
68H Arbitration lost in SLA+R/W as master; own SLA+W has been received, ACK returned
70H General call address (00H) has been received; ACK has been returned
78H Arbitration lost in SLA+R/W as master; general call address has been received, ACK returned
80H Previously addressed with own SLV address; DATA has been received; ACK returned
88H Previously addressed with own SLA; DATA byte has been received; not ACK returned
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90H Previously addressed with general call address; DATA has been received; ACK returned
98H Previously addressed with general call address; DATA has been received; not ACK returned
A0H A STOP condition or repeated START condition has been received while still addressed as
SLV/REC or SLV/TRX
Table 2-8 I2C Status in Slave Transmitter Mode
Status Code Status of the I2C
A8H Own SLA+R has been received; ACK has been returned
B0H Arbitration lost in SLA+R/W as master; own SLA+R has been received; ACK has been returned
B8H Data byte has been transmitted; ACK has been received
C0H Data byte has been transmitted; not ACK has been received
C8H Last data byte has been transmitted; ACK has been received
Table 2-9 I2C Status-Miscellaneous States
Status Code Status of the I2C
38H Arbitration lost
F8H No relevant state information available; si=0
00H Bus error during MST or selected slave modes
I2CSTA register value indicates what happen on the i2c bus. The next operation depends on status
register value. The list of operations for various states:
For master:
0x8 and 0x10 – slave address with write flag will be transmitted
0x18 and 0x28 – one byte will be transmitted from sending buffer
0x20 and 0x48 – slave address with write flag has been transmitted, no ACK was received.
Error number will be saved and transmission will be stopped.
0x30 – data byte has been transmitted, no ACK was received. Error number will be saved
and transmission will be stopped.
0x38 – arbitration lost. START condition will be transmitted when bus is free.
0x40 – when only one byte data is to be received, ACK will be returned otherwise NOT ACK
will be returned.
0x50 – one data byte will be received. If data to receive is more than one, ACK will be
returned otherwise NOT ACK will be returned.
0x58 – all data was sent, STOP condition will be transmitted
For slave:
0x60 and 0x70 – Own slave address or general call address with write flag is received, ACK
will be send.
0x80 and 0x90 – byte data is received. ACK will be is returned. Byte data will be saved in
global receive buffer.
0x88 and 0x98 – data is received, NOT ACK is returned. Received data will be saved in
global receive buffer. The variable flag is set to 0, what means I2C interrupt will stay inactive.
0xA - STOP condition or repeated START condition is received. The variable flag is set to 0,
what means I2C interrupt will stay inactive.
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0xA8 – Own slave address or general call address with read flag is received , ACK will be
returned
0xB8 – One data byte transmitted, ACK will be is received.
0xC0 – One data byte transmitted, NOT ACK will be received.
0xC8 – All data transmitted, ACK will be received.
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3 External I2C IP Usage
3.1 Serial clock generator
This programmable clock pulse generator provides the ―sclo‖ clock pulses when the I2C is in the
master mode. The clock generator is suppressed when the I2C is in the slave mode. The function of
the clock generator is controlled by bits ―cr0‖, ―cr1‖ and ―cr2‖ of ―i2ccon‖ register. The table below
shows the possible rates of ―clko‖ in the master mode. The ―bclk‖ input referenced in the table is the
input pin of the IP core. That means the baud rate of the I2C can be controlled by the user logic.
Table 3.1 I2C Clock Rate Bit Settings
cr2 cr1 cr0 Bit Frequency(kbps)
Clock divided by 6MHz 12MHz 16MHz 24MHz
0 0 0 23 47 63 92 256
0 0 1 27 54 71 108 224
0 1 0 31 63 83 124 192
0 1 1 37 75 100 148 160
1 0 0 6.25 12.5 17 25 960
1 0 1 50 100 133 200 120
1 1 0 100 200 266 400 60
1 1 1 “bclk” input divided by 8
3.2 Master Transmitter mode
Working as a master transmitter, the external I2C first sends a start flag(SDA falling edge while SCL
high level), then gets an interrupt(start flag be sent). Second, sends 7-bit address and 1-bit low
level(indicating data transfer direction); if the slave with the address is hit, it pulls down SDA.
Meanwhile, the master gets an interrupt(indicating slave ready) and sends 8-bit data. After that, if the
slave receives the data successfully, it pulls down SDA . The master gets another interrupt(data be
received successfully) and sends the next data until all the data-transfer is finished; then, sends a
stop flag(SDA rising edge while SCL high level).
Figure 3-1 Timing in Master Transmitter mode
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3.3 Master Receiver mode
Working as a master receiver, it behaviors the same as master transmitter when sending start flag
and slave address. In data transfer period, the master drives SCL, but leaves SDA driven by slave.
After 8-bit data is received, it generates an interrupt and pulls down SDA. If in protocol, every time
only one byte needs transfer, then the master sends stop flag; otherwise, multiple-bytes data is
transferred one by one.
Figure 3-2 Timing in Master Receiver mode
3.4 Slave Receiver mode
Working as a slave receiver, it receives start flag and address. If the address received unmatches its
own address, it sends no ack signal; otherwise sends ack by pull down SDA, and then receives data
from the master. Every 8 bits are received, there is an interrupt to MCU. If the receiver could not
handle with the data as soon as possible(for example, it has to spend time on data store), pull down
SCL to insert wait state. When receives stop flag, the IP core generates an interrupt to MCU
indicating data-transfer over.
Figure 3-3 Timing in Slave Receiver mode
3.5 Slave Transmitter mode
Working as a slave transmitter, it behaviors the same as slave receiver during receiving start flag and
slave address. If the address received unmatches its own address, it sends no ack signal; otherwise
sends ack by pull down SDA, and then sends data to the master. Every 8 bits are sent, there is an
interrupt. If ack signal from master is valid, the slave sends another 8 bits until stop flag is received.
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Figure 3-4 Timing in Slave Transmitter mode
3.6 Interrupt generation
The External I2C provides the Interrupt output ―irq‖. the interrupt generator source is detailed in
2.3 I2C Internal Register, I2CSTA. There are 26 possible status codes, which are presented in Table
2.3.5 … Table 2.3.9. When one of the 25 out of 26 possible I2C FSM states is entered, an interrupt is
requested. The only state that does not generate an interrupt is the F8h state. When irq is asserted,
8051 should read I2CSTA register, the value indicates what happens on I2C bus. After that, for I2C
bus to enter into the next operation, 8051 should set I2CCON.3(si) to 0 which simultaneously dessert
the ―irq‖(become low level).
3.7 External memory interface (EMIF) operation
EMIF Interface timing
EMIF is used to extend the MSS (MCU sub-system) memory, address 20000~7FFFFF, can be
implemented with Fabric.
The CME-M5 family provides synchronous and asynchronous EMIF for Fabric extended memory
which has the same data/address and control ports but have different timing waveforms. The
synchronous or asynchronous EMIF mode is selected by the parameter sync_mode_en.
Figure 3-5 EMIF read waveform
When reading, Fabric places the read data to memdatai bus and not outputs a valid ―memack‖
after one or several cycles until the fabric data is ready after the memrd is asserted.
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Figure 3-6 EMIF write waveform
In write cycle, Fabric writes the memdatao to extended memory when the memwr is asserted
and send a valid ―memack‖ to MSS on the next cycle
EMIF data bank operation
Figure 3-7 CME 8051 memory map
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Figure 3-8 CME 8051 bank arrangement
As is shown in figure up, the common area starts at 0x0000H address and ends at 0x7FFFH.
Bank 0 is not available, it is physically the same memory spaces at the common area. While
code/xdata memory banking feature is enabled, the code/xdata memory address is composed of two
parts:
15 bit address
8bits from a bank switching register SW_REGISTER:
PAGESEL for code memory
D_PAGESEL for xdata memory
Figure 3-9 code/xdata memory address with banking
For more information of EMIF interface, please refer to:
http://www.agatelogic.com.cn/PDF/CME-M5_Family_FPGA_Simplified_Data_Sheet_EN.pdf
3.8 Interrupt operation
For this External I2C IP, When one of the 25 out of 26 possible I2C FSM states(I2CSTA, refer to
Section 2.3) is entered, interrupt request (irq) is generated. The IP can connect this interrupt request
to any 8051’s external interrupt input. And 8051 will follow the normal interrupt handle procedure to
handle I2C’s interrupt request.
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8051’s external interrupt sources:
Table 3-2 8051 external interrupt sources
Vector
Number
Type Polarity Alternate Port Description
0 I Low/Fall Port3i[2] External interrupt 0
2 I Low/Fall Port3i[3] External interrupt 1
9 I Fall/Rise Port1i[4] External interrupt 2
10 I Fall/Rise Port1i[0] External interrupt 3
11 I Rise Port1i[1] External interrupt 4
12 I Rise Port1i[2] External interrupt 5
13 I Rise Port1i[3] External interrupt 6
8 I Rise Port1i[6] External interrupt 7
3.9 Resource usage and performance analysis
Resource usage and performance of the External I2C IP on Primace 4.1.2
Table 3-3 External I2C IP resource usage and performance
Resource LUTs Regs Performance
879 275 109M
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4 Generate File Directory Structure
The I2C IP wizard generated file includes: source files (src), simulation files(sim) and example
design files and related domument. The detailed design directory structure is as below.
Project
src outputs ip_core
ip_top.v
(define by user)
ext_i2c_top.v
addr_mapping.v
i2c_core.v
simsrc doc example
ext_i2c_top_tb.v
ext_i2c_top
_modelsim.f
ext_i2c_tb.do
*.vp
(Protected RTL)
CME_i2c_
user_guide.pdf
ext_i2c_master
ext_i2c_slave
CME_i2c_exampl
e_user_guide.pdf
= directory
= source RTL code
= simulation related files
= documentation
i2c_v1
src_vp
Figure 4-1 IP wizard generated file directory structure
Table 4-1 Generated File Directory structure
Directory Description
src\ Directory for project source code, including
IP wizard generate code.
ip_core\ The directory specially for all IPs
\i2c_v1 Directory for I2C IP
\doc\CME_i2c_user_guide_EN01.doc User guide for I2C IP
\src IP Design RTL
\src\ext_i2c_top.v The top of I2C IP (Encrypted)
\src\addr_mapping.v The bridge of EMIF and SFR (Encrypted)
\src\i2c_core.v The main function of I2C (Encrypted)
\sim
\ext_i2c_top_tb.v Testbench of I2C IP
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\ext_i2c_tb_modelsim.f Modelsim simulation related files
\ext_i2c_tb.do Do script for Modelsim simulation
\src_vp Protected design RTL for Modelsim
simulation
\*.vp Encrypted I2C IP related design RTL
\example
ext_i2c_master.zip use the I2C IP to work as master
ext_i2c_slave.zip use the I2C IP to work as slave
CME_i2c_example_user_guide.pdf The guide of two I2C IP to communicate with
each other
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Revision History
Revision Date Comments
1.0 2013-01-16 Initial release