The new H4CPlus Series arrays feature new 3.3V, 5V and mixed-voltagecapability, high-speed interfaces, and analog PLLs for chip-to-chip clock skewmanagement. The gate length has been reduced to 0.65 µm Leff to provideimproved 5V performance and competitive performance at 3.3V.
The low- and mixed-voltage capability lets designers customize the H4CPlusarrays to fit power and performance needs. All H4CPlus arrays have dual VDD railswith custom power/ground bus tying to power input and output buffers for full 3.3V,full 5V or a mix of system voltage levels. Additionally, the core of the arrays may bepowered by either 3.3V or 5V.
New, high-speed CMTL, GTL, and PECL macros offer enhanced chip-to-chipcommunication. CMTL (Current Mode Transceiver Logic™), a Motorola innovationwith optional active termination, offers a high speed communication interface at200+ MHz and can interface to differential and single-ended PECL (Pseudo EmitterCoupled Logic). Differential and single-ended GTL (industry standard GunningTransceiver Logic™) offers high performance data bus and point to pointcommunications up to 250 MHz. Differential and single-ended PECL inputs offerECL compatible clock rates up to 400 MHz worst case. Also, new PCI (PeripheralComponent Interface) compliant I/O buffers are available in 5V and 3.3V versions.
(cont’d. page 2)
H4CPlus Series Features• 0.65 µm Leff, channelless, triple-layer metal gate arrays• Typical gate delay of 280 ps at 5V and 420 ps at 3.3V (NAN2, FO=2)• Low power, 1µW/gate/MHz (3.3V), 3µW/gate/MHz (5V)• 3.3V, 5V or mixed system and core voltage levels• Custom power bus tying and ground bus isolation for special power needs• Configurable I/O cell supports 2 to 24 mA, up to 48mA using dual I/O cells• PCI compliant 5V and 3.3V I/O buffers with 5V I/O tolerant, 3V I/O input and
output macros, and 5V I/O fail-safe macros• Differential and single-ended GTL I/O and PECL input macros• Analog PLL with 70 to 250 MHz worst case VCO frequency• Pseudo-Random and comparator BIST macros• Single-, dual-, and quad-port metal SRAMs• Single- and dual-port diffused SRAMs• Powerful design environment using Mentor Graphics, Cadence Design
Systems, Synopsys, Quad Design Technology, and Motorola design tools• OMPAC ball-grid array, MicroCool, and PQFP packaging
Order this Data Sheet by H4CP/D
H4CPlusSERIES
HIGH PERFORMANCETRIPLE LAYER METAL
SUB-MICRONCMOS ARRAYS
(insert photo ofH4CPlus SERIES
Packages)
QFPMicroCoolOMPAC
TYPICAL H4CPlus SERIES PACKAGES
MOTOROLA H4CPlus_Series
2
(cont’d from page 1)Each array can have two APLL (Analog Phase Lock Loop)
macros, placed in the adjacent corners of the die, havingseparate APLL power pins for obtaining low noise and phasejitter. External components are not required since the VCOfilter is contained in the APLL. The APLL can be used inapplications such as clock synthesis with a worst case VCOfrequency of 70 to 250 MHz (30 to 415 MHz typical).
Other design features include Fail-Safe macros, metal anddiffused RAMs, ESSD/LSSD scan macros, JTAG boundaryscan, and Built-In Self Test macros.
HIGH-PERFORMANCE TECHNOLOGYThe H4CPlus Series uses a self-aligned twin tub process
in which n-type and p-type well implants are driven togetherto form deep, balanced wells to improve short n-channel tran-sistor performance, see Figure 1. A lightly doped drain (LDD)diffusion is used to reduce hot carrier injection effects causedby a high electric field in the short channel transistors. A high-ly-reliable multi-layer metal structure is achieved by a pla-narization technique using tapered contacts and vias.
The combination of a small feature size and a thin gate ox-ide coating provides both high gate density and low powerdissipation. The typical power dissipation for internal gates isonly 1µW/gate/MHz at 3.3V and 3µW/gate/MHz at 5.0V witha load of 0.05 pF (fanout = 1).
Figure 1. H4CPlus Series CMOS Device Cross-Section
M3
M2
M1
PTO
PTO
BPSG
p-Welln-Well
p-Fieldp-MOSFETn-MOSFET
p-Substrate
PolysiliconGate
Gate Oxide
PSGPassivation
(Plasma Teos Oxide)
(Plasma Teos Oxide)
Field Oxide
Plasma Nitride
The H4CPlus Primary CellThe primary cell consists of four pairs of n- and p-type
transistors. The transistors are the same size to optimizeboth gate density and routability. The primary cell is used toconfigure all H4CPlus Series macrocells. Figure 2 shows half
of a primary cell (two p-type and two n-type transistors) con-figured in a 2-input NAND gate (NAN2). The typical gatedelay for a 2-input NAND with a fanout of 2 is 280 ps at 5Vand 420 ps at 3.3V.
Figure 2. 2-Input NAND Gate Implemented Within Half of a Primary Cell
P-ChannelTransistors
N-ChannelTransistors
A
B
A
X
B
A
B
VDD VSS
PolysiliconGate
N-Well P-Well
X
A
B
VDD
VSS
PRODUCT DESCRIPTION
H4CPlus_Series MOTOROLA
3
Triple-Layer Metal RoutingA triple-layer metal (TLM) structure provides superior
routing access to configure and connect macrocells as wellas distribute power and ground, see Figure 3.
Figure 3. Triple-Layer Metallization (SEM Photo)
One important benefit of TLM routing is improvedroutability for higher gate utilization. TLM also providesimproved clock distribution by moving the clock signals to thetop metal layer where the capacitance per unit length is 30%less than the lower metal layers due to a thicker dielectriclayer. In addition, TLM reduces interconnect delays typicallyby 10% with shorter interconnect lengths and improvespower distribution.
• Gate Ensemble Place and RouteThe design of the routing layers is accomplished with
Cadence’s Gate Ensemble place and route system. Some ofGate Ensemble's capabilities include soft/firm grouping ofmacros, clock-tree synthesis, incremental layout changes,and highly accurate distributed RC calculations. In addition,the power-bus router automatically uses single-, double-, orquadruple-width power tracks to optimize performance whileminimizing spent routing channels where needed.
• PrediX FloorplanningPrediX is Motorola’s powerful floorplanning and routabil-
ity analysis tool that enables designers to predict andimprove routing congestion especially in complex circuits.PrediX is easy to use and interfaces with Gate Ensemble toassure the desired results in layout and timing.
PRODUCT DESCRIPTION (continued)
THE H4CPlus SERIES LIBRARYThe H4CPlus Series library is an optimized set of macros
containing a complete suite of I/O functions, combinatorialand sequential functions. Many basic logic functions come inseveral versions including standard/high-drive capacity andscan/non-scan to provide the widest choice of functions.
I/O Macrocell LibraryThe H4CPlus Series I/O cells, see Figure 4, are config-
urable into inputs, outputs, bidirectionals, oscillators, JTAG I/O, CMTL, GTL, and PECL interfaces. The standard CMOS,TTL, slew control, 3-state, open-drain and Schmitt-trigger I/Ofunctions are available as well. The I/O cell also providespull-up and pull-down resistors, active terminations forCMTL, voltage translation between 3.3V and 5V levels, andpower and ground connections.
• 3.3V, 5V, and Mixed-Voltage I/OThe I/O cell can support any combination of 3.3V and 5V
in system and core voltage requirements. This is accom-plished with a voltage translator to translate between logiclevels based on the system and core voltages, see Figure 4.
Low-voltage interfaces are important in systems requiringlow-power since most of the power dissipated in ICs occursin the outputs. However, performance is usually sacrificed forlower power. The H4CPlus Series I/O offers all combinationsof system and core voltage levels to meet power and perfor-mance goals. For example, the ONL8 is a 12mA output for a3.3V/3.3V (3.3V Input/Output with 3.3V core. Its power dissi-pation is about 56% less than the 5V/5V ON8 output, but it is41% slower at 100pF, see Figure 5. The ONLX8 (3.3V/5V)and the ONX8 (5V/3.3V) is moderately slower than the ON8.
Figure 4. H4CPlus Series I/O Cell
• Selectable Output DriveUp to 24 mA is available from a single I/O cell, two cells
may be paralleled for up to 48 mA drive from a single outputpin. (All JTAG outputs and bidirectionals are not parallelable,but have higher current capacity versions available.) Unusedoutput drivers may also be used to drive highly loaded inter-nal signals such as clock networks.
• Slew Rate ControlSlew rate control outputs are available to reduce system
SSO noise as well as over-shoot and undershoot of outputsignals caused by fast rise and fall times. All 4 and 8 mA out-put buffers have a moderate (10%) and slow (30%) slewcontrol version.
JTAGLogic
T InPad
Pad
I/O Cell
I/O Cell
Pull Resistors
Active TerminationsESD Diodes
Configurable Output
Configurable Input
Vol
t. T
rans
.Out
I/O Cell
Arr
ay C
ore
SPECIAL DESIGN FEATURES
MOTOROLA H4CPlus_Series
4
• PCI I/O BuffersPCI (Peripheral Component Interface) is emerging as a
high-performance local bus architecture. It is a highly flexi-ble, processor independent architecture that has applicationsin low- to high-end desktop, server and low-power, mobilesystems. Motorola offers PCI compliant 3.3V and 5V I/Obuffers to allow connection of H4CPlus arrays to any PCIlocal bus “speedway”.
• GTL InterfaceGTL is able to drive system backplanes while still occu-
pying only a single I/O site for 50Ω and two sites for 25Ω.This licensed implementation provides a high performancebus driver for system I/O data rates exceeding 200 Mbits/secdepending on the bus fanout loading. Differential GTL is alsoavailable for providing the clock signals to Fast StaticBiCMOS RAMs and for point to point applications providingworst case clock rates of greater than 200 MHz.
• PECL InterfaceStandard positive ECL voltage levels can be received
with differential and single-ended PECL receiver macros atworst case clock rates up to 400 MHz. The H4CPlus arrayscan also drive Standard PECL inputs by using CMTL or GTLoutput macros as described in application note AN1521.
Figure 6. Typical CMTL Applications
m-bits
n-Bit Shift Register
FIFO
ECLinPS™ Logic H4CPlus Series with CMTL I/O
High-SpeedData
400 MHzClock
400 Mb/secDataOut
H4CPlus Series with CMTL I/O PECL I/O RAMor RAMDAC
GraphicsEngine
or
CPU
or
SignalProcessor
Data Out
Address
Enable
n-bits
n-BITS
High-SpeedOutput
ASIC #1 ASIC #2
High-SpeedOutput
High-SpeedInput
High-SpeedInput
Self-TerminatingDifferential
Data In
Control
m-bits
FIFOControl
n-BITS
Data Out
Enable
Data In
Data Out
Enable
Data In
Self-TerminatingSingle-Ended
Vref
Vref
Figure 5. Performance Comparison of 12mA Output Buffers
• Fail-Safe I/O Macros5 Volt Fail-Safe I/O macros are provided for bus applica-
tions that will not load the active bus when power isremoved. These macros can be designed in applicationsrequiring "hot plug" operation where a card is inserted whilethe system is running.
• Extended Voltage Range I/O MacrosExtended Voltage Range I/O macros, or 5V tolerant 3.3V
I/Os provide a flexible design solution for designers imple-menting 3 volt systems in a 5 volt world. These macros des-ignated by an "E" in their name require only a 3 volt supply,but can tolerate the reception of a 5 volt signal on the pad.
• CMTL InterfaceMotorola’s new Current Mode Transceiver Logic (CMTL)
buffers provide a low-power alternative to high-speed inter-faces. On-chip active termination allows for the lowest possi-ble power dissipation while enhancing the performance.They may also be configured with external 50Ω terminationsin bidirectional or PECL applications.
The drivers have been engineered to operate withoutexternal reference or termination voltages and over a widerange of common-mode voltages. The flexibility of thisdesign allows simple, direct interfaces to ECLinPS or otherECL-level chips operating in a PECL environment with stan-dard terminations.
Applications for CMTL range from video to telecommuni-cations to tightly-coupled processor/cache interfaces. I/Opair delay is less than 2ns worst-case. Systems are nolonger limited by slow buffers for critical chip-to-chip paths.
ONL8 3.3V/3.3V Core
ONX8 5V/3.3V Core
ONLX8 3.3V/5V Core
ON8 5V/5V Core
System
t PLH
4
3
2
1
00 20 40
Load (pF)
60 80 100
SPECIAL DESIGN FEATURES (continued)
H4CPlus_Series MOTOROLA
5
• OscillatorsThree different oscillator I/O macros are available on the
H4CPlus Series arrays: non-inverting buffer, clock buffer,and Schmitt trigger versions. These macros can be config-ured for ceramic resonators from 32 KHz to above 60 MHzwith quartz crystals.
• JTAG Boundary Scan I/OThe H4CPlus Series I/O cell has JTAG logic built-in to
minimize the impact on performance and gate overhead.Also, the JTAG control and scan data signals between I/Osare connected automatically by design.
Internal Macrocell LibraryThe mature H4C Series library has been optimized to a set
of the most popular and efficient functions, including severalnew scan macros, for the H4CPlus library. All H4CPlus mac-rocells have been characterized at typical operating condi-tions for 3.3V and 5.0V operation for the highest modellingaccuracy. A summary of available macrocell types is shown inTable 2.
Table 2. Summary of Macrocells
Library Functions Macros
AND 7
NAND 11
OR 7
NOR 11
EXOR, EXNOR 5
A/N, A/O, O/N, O/A 22
Inverting Buffer 9
Non-Inverting Buffer 8
3-State Buffer 8
D Flip-Flop 23
Latch 11
Multiplexer 13
Decoder 4
Arithmetic 9
Misc. 6
Table 3. Summary of Special Functions
Special Function Macros
Metallized SRAMs 24
BIST 5
Analog PLL 10
Internal JTAG 6
Figure 7. Performance of NAN2 Macros
Several types of macrocells come in high-drive, balancedslew-rate, or complementary output versions. High-drive ver-sions provide improved performance on nets with highfanouts. Balanced slew rate versions of macrocells providemore symmetrical rise and fall slew rates with slightly betterperformance than standard macros. For example, Figure 7shows the NAN2H at 3.3V and 5V to have better performancethan the balanced and standard-drive NAN2.
Metallized SRAMsThe metal SRAMs are a family of asynchronous single, du-
al, and quad-port blocks up to 2304 bits. These RAMs aregate array based (not diffused), and are an excellent choicefor small memory block applications such as “scratch-pads”or FIFOs.
Table 4. Sizes of Metallized SRAMs
H4CPlus Series Metallized SRAM Sizes
Single-Port Dual-Port Quad-Port
8x8 8x9 16x18
8x18 8x18 16x36
16x8 8x36 32x18
16x18 8x72 32x36
16x36 16x9
32x8 16x18
32x18 16x36
32x36 16x72
64x18 32x9
64x36 32x18
32x36
32x72
8765432100.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
NAN2 (3.3V)
NAN2H (3.3V)NAN2B (3.3V)
NAN2 (5V)
NAN2H (5V)NAN2B (5V)
Fanout
Ave
. Pro
p. D
elay
(n
s)
SPECIAL DESIGN FEATURES (continued)
MOTOROLA H4CPlus_Series
6
• Clock DistributionMotorola offers clock tree synthesis during layout to build
balanced clock distribution networks or clock trees. Clocktrees are load-balanced networks that synchronizes clocksignals for all on-chip sequential elements. Clock trees havea minimal effect on design routability, critical data paths, tim-ing driven layout and floorplanning.
• Analog Phase Locked LoopAPLL (Analog Phase Lock Loop) macros can be used in
applications such as clock synthesis with a worst case VCOfrequency of 70 to 250 MHz (30 to 415 MHz typical). TheAPLL is an embedded function and requires 6 (CMOS) or 7(PECL) pins for VCO control, reference frequency, test, andpower signals. No external filters are needed.
An APLL is diffused into two opposite corners of allH4CPlus arrays. No area within the core of the array is usedso the APLL does not contribute to the total gate count.
• Diffused SRAMSUser definable SRAM configurations are available using
Motorola’s Felix SRAM compiler. Felix generates several ver-sions of a given SRAM size, each with different performance,gate counts, and physical configurations.
Table 5. Analog PLL Features
Features Analog PLLOutput Frequency (Vco/2) 35MHz - 125MHzFrequency multiplication Yes
Phase Error +Jitter ±250psMax. Clock Tree Delay @ 50MHz 20ns
ARCHITECTURAL FEATURESThe H4CPlus Series offers solutions to many of today's de-
sign problems. Increasing application complexities placehigher demands on performance, clock skew management,testability, I/O capability and workstation based design envi-ronments. This section describes some of the special fea-tures of the H4CPlus Series that provide solutions to theseproblems.
Design for TestabilityThe time and cost to test an ASIC increases exponentially
as the complexity and size of the ASIC grows. Using a designfor test (DFT) methodology allows large, complex ASICs to beefficiently and economically tested.
Motorola supports several DFT methodologies, includingESSD/LSSD scan, JTAG boundary scan, and BIST for mem-ories. To take full advantage of these DFT methodologies,Motorola has supported the development of a low-cost, high-speed scan tester.
• ESSD/LSSD ScanMotorola offers Edge Sensitive Scan Design and Level
Sensitive Scan Design (ESSD/LSSD) versions of flip-flops,latches and other functions in the H4CPlus Series library. Au-tomatic Test Pattern Generation (ATPG) can be performedusing Mentor Graphics’ FastScan ATPG tool.
• JTAG Boundary ScanMotorola’s JTAG I/O and JTAG control macrocells are de-
signed to conform to the IEEE 1149.1 JTAG boundary scanspecification. The JTAG I/O macrocells are designed to opti-mize performance and minimize silicon overhead by embed-ding all sequential and multiplexing logic within the I/O sitesof the array.
• Built-In Self TestTwo versions of Built-in-Self-Test (BIST) are available for
memories: “Pseudo-Random” BIST is relatively easy to im-plement, requires few gates, and can achieve fault coverageup to 99%. “Comparator” BIST, on the other hand, is morecomplicated to design and requires more gate overhead, butcan achieve 100% fault coverage.
Clock Distribution and ManagementASICs are becoming an integral part of system design and
are regularly found interfacing with multiple chips includingother ASICs, microprocessors and memories. Optimizingperformance of such systems rests on maximizing communi-cation between chips using synchronous interfaces. Clockskew control and distribution, both on-chip and betweenchips, is of critical importance.The Motorola solution to clockmanagement is to use the clock tree to control skew on-chipand an analog PLL to control clock skew between ASICs.
SPECIAL DESIGN FEATURES (continued)
H4CPlus_Series MOTOROLA
7
THE OPEN ARCHITECTURE CAD SYSTEMThe Open Architecture CAD System (OACS) offers a
highly versatile and powerful design environment for thedesign of Motorola’s H4CPlus Series CMOS arrays. TheOACS integrates several of the industry's most powerfuldesign tools with selected Motorola high-productivity toolsinto standard verilog and EDIF netlist based CAD environ-ments. The information in this data sheet reflects two majorversions of OACS: OACS 4.0 and OACS 3.2M.
OACS 4.0 is Motorola’s point tool CAE solution based onCadence Design System’s Concept schematic editor, Syn-opsys’ synthesis tools, and Cadence’s Verilog XL logic sim-ulator.
OACS 3.2M is Motorola’s framework based CAE solutionusing Mentor Graphic’s Falcon Framework. This solutionprovides support of Mentor’s design entry tools and Quick-Sim II logic simulation.
OACS 4.0 and 3.2M Features Supported Third-Party Design Tools:
Supported Systems Capabilities:• Verilog (OACS 4.0) and EDIF 2.0.0 (OACS 3.2M)
backplanes to provide open design environments• Testability support: ESSD/LSSD scan, JTAG boundary
scan, BIST, and scan synthesis• Sophisticated delay and timing limits calculations for
accurate simulation and timing analysis• Estimated and actual (back-annotated) wire
capacitances• Includes intrinsic, rise/fall time, output pin loading and
distributed RC delays• Continuous process, temperature, and voltage
variation• Clock skew management: clock-tree synthesis and
PLL
• Supports multiple technologies: HDC Series, H4CSeries, H4CPlus Series, and M5C Series
• Supported on HP9000/7XX and SUN 4 SPARC
workstations
The OACS Design FlowFrom the conception of your design to its fabrication, you
will see that the OACS design flow is accurate, efficient, andflexible. The design flow has three basic phases (see Figure8) design capture and verification, physical design, and post-layout design verification.
• Design Capture and VerificationPre-layout design is performed by the customer using
OACS tools to develop and simulate the ASIC product. Inaddition to schematic capture, designs can be synthesizedusing a hardware description language (HDL or VHDL),equations, or truth tables. The design may be floorplanned tooptimize for density or performance. PrediX, Motorola’s floor-planning tool, allows experimentation with various floorplansto achieve desired gate density and performance goals. Inaddition, PrediX provides to the designer routability informa-tion to guide the designer in the floorplanning phase. At thispoint in the design phase, delay and timing calculations,netlist verification, automatic test pattern generation, or statictiming analysis can be performed. Pre-layout simulations useestimated best/typical/worst-case delays based on gate,load, slew rate, and floorplan driven estimated RC delays.Prior to the release of the design to layout, the test vectorscreated by the customer must pass specific rules to take fulladvantage of Motorola’s production test equipment.
• Physical DesignPhysical design, place and route, is performed by Motor-
ola’s Option Development Engineers (ODE). An ODE is dedi-cated to each option and works directly with the customer tosatisfy their layout requirements. Options such as timingdriven layout and clock tree synthesis are available to opti-mize silicon performance. Optionally, the user may choose touse PrediX IPS (Integrated Placement Solution) to performmacro placement on the target die and leave only the routingto the ODE. PrediX IPS not only enables the customer tocontrol the actual placement of the critical paths within thecircuit, but also improve the accuracy of the estimated para-sitics and resulting estimated timing over that provided by astandard PrediX floorplan. Upon completion of the physicaldesign, back-annotation data of actual wire routing lengthsand RC parasitics is provided to the customer for post-layoutverification.
• Post-Layout Design VerificationThe post-layout design verification is performed by the
customer to assure that the physical layout of the design sat-isfies all performance and timing requirements. Post-layoutsimulations use the actual parasitics obtained from the physi-cal layout to provide simulations that represent the circuit’sbehavior in silicon. Following a successful post-layout designverification and customer sign-off, Motorola begins manufac-turing of the ASIC design.
Functional Test Patterns Functional Test PatternsScan Test Patterns
Verified Test Patterns
EDIF Netlist, Layout & Test Vector Data
Actual Metal Lengths and Capacitances
Actual Timing Data
ASIC_MOTIVE - Timing Analysis
Mentor EDDM Database
Test Compiler / DFTAdvisor - Test Synthesis
Verilog Netlists
ASIC_CONFIG - Design File Creation
Pinout - I/O Ring Definition
EDIF Netlists
Invokes Timebase
QuickSim II - Post Layout Timing SimulationInvokes Timebase
Invokes Timebase
QuickPath - Timing AnalysisInvokes Timebase
H4CPlus_Series MOTOROLA
9
Beyond standard QFPs, Motorola offers two styles ofhigh performance, surface mounted packages to comple-ment the H4CPlus Series arrays.
OMPAC (Over-Molded Pad Array Carrier)Motorola has developed a unique plastic pad array carrier
package (OMPAC) to support trends toward PC board spacesavings, improved manufacturing yields and better electricaland thermal performance. OMPAC’s low profile is ideal forportable products. Its ability to handle large die and pin countswithout coplanarity and skew problems makes it well suited toCMOS gate arrays.
The OMPAC package primarily consists of a thin, doublemetal printed circuit board that is overmolded with plastic. Theintegrated circuit is attached to a gold plated die flag on thesubstrate with a silver filled epoxy. Electrical connections tothe integrated circuit are made using conventional gold ballbonding techniques. Etched copper traces extend from thebond finger connections to plated thruhole vias near the edgeof the package, which connect to an array of solder ball termi-nals (lands) on the bottom of the substrate (see Figure 10).
PACKAGING
Figure 10. Simplified Cross-Sectional View of OMPAC
DIE
BT RESIN EPOXYCOPPER FOIL
SOLDER BALL
THERMAL VIA:COPPER PLATED THROUGH-HOLE
SOLDER MASKCOVERING THERMAL VIA
MOLDING COMPOUND
GOLD PLATED DIE ATTACH
SOLDER MASK
DIE ATTACH EPOXY
Figure 9. Over-Molded Pad Array Carrier (OMPAC)saves board space and improves manufacturing yields
MicroCool QUAD FLAT PACKThe MicroCool QFP is a new QFP compatible plastic
package with higher heat dissipation capacity. It has a heatslug attached to a printed circuit board which supports a cop-per lead frame. The package is supported within an MCR tomaintain pin coplanarity. The MicroCool is a high pin densitypackage that is capable of meeting the higher power dissipa-tion (up to 3 W, depending on temperature and ambient con-ditions) and higher performance requirements of the H4CPSeries.
DrypackQFPs, MicroCools and the OMPAC packages will be
shipped by Motorola baked and drypacked. The trend to-wards Surface Mount Technology (SMT) with high density,thinner packages (which are more sensitive to thermal stressfailure during board mounting) has led Motorola to conductnumerous studies. The resultant action is a slow bake ofmoisture from the SMT package and shipping in drypackbags to shield the unit from moisture absorption. Units arebaked at 125oC for 24* hours, cooled and placed in a vacuumsealed drypack with desiccant bags, humidity indicator card,and lot identification stickers.
*Note: Varies by package type, please consult factory.
169 OMPAC (CU) Q A A A225 OMPAC (CU) Q A A A A A256 OMPAC (CU) Q P A P P313 OMPAC (CU) A A A324 CBGA (CU) P P P
*Numbers indicate wirebond pads availabilityQFP: Plastic Quad Flat Pack (CU) denotes Cavity Up (CD) denotes Cavity DownMicroCool: QFP-type package with heat slugOMPAC: Over-Molded Pad Array Carrier, a PGA type package with solder balls instead of pins, Prototypes for the 169 and 225 OMPAC are supplied in a GTPAC packageCBGA: Ceramic Ball Grid Array, a small footprint hermetic package with superior electrical and excellent thermal performanceA = Available.F = Flexible power pin assignment.P = Planned.Q = Qualified. (Consult factory for qualification status)Note: The 225 OMPAC package has a number of (System/Core) power combinations, see individual pad to pin tables forspecific power features.
PACKAGING (Continued)
H4CPlus_Series MOTOROLA
11
The following tables detail the elements which make up theH4CPlus Series library. The elements are organized into thefollowing categories: Input/Output, Bidirectional Input andOutput Macros, System Interface Macros, Power/GroundMacrocells, Internal Macrocells, Memory Blocks (RAM Mac-rocells).
Gates = equivalent gate count (Internal Macrocells)System/Core I/O Voltage definition:5/5 V = 5 Volt System and 5 Volt Core5/3.3 V = 5 Volt System and 3.3 Volt Core3.3/5 V = 3.3 Volt System and 5 Volt Core3.3/3.3 V = 3.3 Volt System and 3.3 Volt Core
1. See electrical specifications for additional informa-tion. 2. For Bidirectional JTAG Macro the O is removed inthe name. i.e.: BON2T = BN2TJ x = Suffix such as S2, T, and OD. * = 3-State with Slew Rate Control
6 FMC_TAPCBTAP Controller (FIRM Macro) FixedPlacement which effects Routing
276
# INTERNAL MACROS Gates
THE MACROCELL LIBRARY (Continued)
MOTOROLA H4CPlus_Series
16
Miscellaneous JTAG Macro1 CKDRMID B-S Register Clock Driver 02 CKDRCC1 B-S Register Clock Driver 03 CKDRCC2 B-S Register Clock Driver 04 ENSCANJ B-S Register Enable Scan Macro 05 IMCDR B-S Reg. input Mode Control Driver 06 OMCDR B-S Reg. Output Mode Control Driver 07 ISOR Clock Net ISO and Test Data Resync 08 SHDR B-S Register Shift Driverr 09 TDBUF B-S Register Test Data Buffer 0
10 UDDR B-S Register Update Driver 0
MEMORY BLOCKS
# Name Ram SizeGate
Count
Single-Port RAM’s (Low Power)1 RSB8X8 8 word X 8bit 1982 RSB8X18 8 word X 18bit 4403 RSB16X8 16 word X 8bit 3424 RSB16X18 16 word X 18bit 7605 RSB16X36 16 word X 36 bit 14406 RSB32X8 32 word X 8bit 6307 RSB32X18 32 word X 18 bit 1400
# INTERNAL MACROS Gates
Single-Port RAM’s (Low Power) (Cont’)8 RSB32X36 32 word X 36 bit 26609 RSB64X18 64 word X 18 bit 268010 RSB64X36 64 word X 36 bit 5092
Dual-Port RAM’s (High Speed)1 RDB8X9 8 word X 9 bit 3562 RDB8X18 8 word X 18 bit 6083 RDB8X36 8 word X 36 bit 11124 RDB8X72 8 word X 72 bit 21565 RDB16X9 16 word X 9 bit 7256 RDB16X18 16 word X 18 bit 11937 RDB16X36 16 word X 36 bit 21298 RDB16X72 16 word X 72 bit 40509 RDB32X9 32 word X 9 bit 140010 RDB32X18 32 word X 18 bit 230011 RDB32X36 32 word X 36 bit 410012 RDB32X72 32 word X 72 bit 7798
Quad-Port RAM’s1 RQB16X18 16 word X 18 bit 22002 RQB16X36 16 word X 36 bit 37663 RQB32X18 32 word X 18 bit 47624 RQB32X36 32 word X 36 bit 7738
MEMORY BLOCKS
# Name Ram SizeGate
Count
THE MACROCELL LIBRARY (Continued)
MACROCELL EXAMPLES
INPUT MACROCELLS
Inverting CMOS Inputs and Bidirectional Input(3.3 V and 5 V System/Core Voltages)
ICI/BICIILCI
MACRO SECTIONS USED
ICI/ILCI 1/0BICI 1/0
Rev. 1.09
MACRO OUTPUTS/INPUTS
ICI/ILCI DI / PAD,ICBICI DI / BC
MACRO INPUT CAP.
ICI/ILCI PAD: 5.29pFBICI BC: 0.39pF
Function TablePAD DI
L HH L
CMOS SWITCHING CHARACTERISTICS(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns. Rev. 1.09
tPHL 1.68 1.76 2.01 0.82 2.57 2.69 3.03 1.16tr Output Rise Time, Q 0.29 0.35 0.52 0.57 0.38 0.46 0.71 0.82tf Output Fall Time, Q 0.44 0.49 0.67 0.59 0.59 0.66 0.89 0.75tr Output Rise Time, QB 0.26 0.32 0.49 0.56 0.32 0.40 0.64 0.79tf Output Fall Time, QB 0.31 0.36 0.53 0.55 0.36 0.43 0.63 0.68tr Output Rise Time, SQ 0.20 0.44 1.17 2.44 0.25 0.60 1.63 3.44tf Output Fall Time, SQ 0.18 0.30 0.65 1.17 0.24 0.39 0.81 1.40
Capacitance per fanout = 0.05 pF (metal capacitance is not included).
INTERNAL MACROCELLS (SEQUENTIAL)
D Flip-Flop with Scan Latch 2X Drive(3.3 V and 5 V Core Voltages)
DFFSCH
MACRO EQUIV. GATES
DFFSCH 18
Rev. 1.09
MACRO OUTPUTS/INPUTS
DFFSCHQ,QB,SQ /
D,CK,SDI,BCLK,ACLK,EN
MACRO INPUT CAP.
DFFSCH
ACLK,BCLK,EN: 0.10pF CK: 0.05pF D: 0.16pF
SDI: 0.20pF
FUNCTIONAL DESCRIPTION:This macro consists of a D type Flip-Flop with Q feedback
(hold) capability. It allows scan data to be muxed into the slavestage and contains a separate scan latch for storing scan dataindependent of Q. CK clocks the Flip-Flop, BCLK controls latch-ing scan data into the slave stage and ACLK controls the finalscan data latch.
FUNCTION TABLED EN CK SDI BCLK ACLK Q QB SQ Notes
X X L X L L Q QB SQ 1
X L / X L L Q QB SQ 2
L H / X L L L H SQ 3
H H / X L L H L SQ 3
X X L X L H Q QB QB 4
X X L L H L H L SQ 5
X X L H H L L H SQ 5
X X L L H H H L L 6
X X L H H H L H H 6
1. No Clock 2. Active Clock, disabled 3. Active Clock, enabled
CMOS TIMING REQUIREMENTS(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns. Rev. 1.09
Sym Parameter
5 V 3.3 V
Minimum Requirement Minimum Requirement
DFFSCH
tsu Set Up Time, BCLK to ACLK 1.70 2.59
tsu Set Up Time, CK to ACLK 1.84 2.74
tsu Set Up Time, SDI to ACLK 1.67 2.50
tsu Set Up Time, SDI to BCLK 1.33 1.93
tsu Set Up Time, D to CK 0.15 0.34
tsu Set Up Time, EN to CK 0.43 0.66
th Hold Time, ACLK to BCLK -1.21 -1.71
th Hold Time, ACLK to CK -1.21 -1.87
th Hold Time, ACLK to SDI -1.08 -1.58
th Hold Time, BCLK to CK -1.07 -1.65
th Hold Time, BCLK to SDI 0.00 -0.01
th Hold Time, CK to BCLK -1.05 -1.51
th Hold Time, CK to D 0.43 0.57
th Hold Time, CK to EN 0.23 0.31
trec Recovery Time, CK to ACLK 1.97 2.93
trec Recovery Time, ACLK to CK -1.49 -2.20
tw Pulse Width, ACLK(H) 0.43 0.65
tw Pulse Width, BCLK(H) 1.28 1.89
tw Pulse Width, CK(L) 0.59 0.94
tw Pulse Width, CK(H) 1.52 2.20
CK C
CKB
*2X for DFFSCH
EN
SDI
BC
BCKB
*
*ACKB
AC AC
ACKB
SQ
QB
QC
CKBCKB
C
C C
CKB
CKB
ACLK ACKB
AC
D
BCKB
BC
BCLK
*
BC
Note: Outputs have balanced drive.
MACROCELL EXAMPLES (Continued)
H4CPlus_Series MOTOROLA
21
• Random Access MemoriesMotorola offers 26 different building blocks that can be
used to construct Single-, Dual-, and Four-Port memories. Acomprehensive guide to using these blocks and their perfor-mance is shown in the H4CPlus Series Design ReferenceGuide. (H4CPDM/D)
• Multiple Memory BlocksIt is possible to combine two or more memory blocks to
create larger memory blocks. When multiple blocks are used,
the user is responsible for creating the external decoder logicneeded. The maximum number of SRAM blocks on an arrayis restricted to 16, depending on array/SRAM sizes.
• Array SizingTo choose an array into which a design with SRAM will fit,
two considerations must be evaluated: the physical size/lay-out of the SRAM or SRAMs, and the gate utilization.
MACROCELL EXAMPLES (Continued)
METALLIZED SRAM BLOCKS
RDBXXxXX -High Speed Dual-Port SRAMEquivalent Gates: see belowPin names:
A_A(0-m) - address bus for Port AA_B(0-m) - address bus for Port BDIN_A(0-n) -input dataWB_A - Write enable bus for Port ADO_B(0-n) - data output determined by address bus, Port B
TIMING REQUIREMENTS(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns. Rev. 1.09
Abbr. Parameter8-WORD BLOCK5 V 3.3 V
tDSU
Set Up Time, DINA(n) to WBA (WL = 9) 0.28 0.53DINA(n) to WBA (WL = 18) 0.12 0.27DINA(n) to WBA (WL = 36) -0.05 -0.08DINA(n) to WBA (WL = 72) -0.47 -0.46
tAWB
Set Up Time, AA(n) to WBA (WL = 9) 0.02 -0.16AA(n) to WBA (WL = 18) 0.01 -0.27AA(n) to WBA (WL = 36) -0.23 -0.61AA(n) to WBA (WL = 72) -0.52 -0.94
tASU
Set Up Time, AA(n) to WBA (WL = 9) 4.00 5.01AA(n) to WBA (WL = 18) 4.22 5.28AA(n) to WBA (WL = 36) 4.65 5.90AA(n) to WBA (WL = 72) 5.06 6.56
tDH
Hold Time, WBA to DINA(n) (WL = 9) 0.87 1.28WBA to DINA(n) (WL = 18) 1.10 1.62WBA to DINA(n) (WL = 36) 1.41 2.14WBA to DINA(n) (WL = 72) 1.98 2.85
tDH
Hold Time, WBA to AA(n) (WL = 9) 0.66 1.10WBA to AA(n) (WL = 18) 0.82 1.35WBA to AA(n) (WL = 36) 1.14 1.87WBA to AA(n) (WL = 72) 1.61 2.44
VDD* DC Supply Voltage, VDD = 5.0V (Nominal) 4.5 5.5 V
VDD* DC Supply Voltage, VDD = 3.0/3.3V (Nominal) 2.7 3.6 V
* For testing, only. VDD range is wider for simulation purposes.
Notes:1. All parameters are characterized for DC conditions after thermal equilibrium has been established.2. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either Vss or VDD).3. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; how-ever, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated volt-ages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to therange VSS≤ (Vin or Vout)≤VDD.
H4CPlus DC ELECTRICAL CHARACTERISTICS
H4CPlus_Series MOTOROLA
25
Table 8. DC Electrical Characteristics for H4CPlus Series Arrays (T a = -40˚C to 85˚C)
Sym. Parameter ConditionVDD=3V/3.3V±0.3V
Guaranteed VDD=5V±10%Guaranteed Unit
Min. Max. Min. Max.
VIH
Input High Voltage,CMOS Inputs (3.3V and 5V core) 2.0 VDD+0.3 0.7 VDD VDD+0.3
VOHmin Output High Voltage Minimum3.3 V: Iout = -12(VDD)mA5.0 V: Iout = -44 mA
0.3VDD - 1.4 - V
VOHmax Output High Voltage Maximum3.3 V: Iout = -32(VDD)mA5.0 V: Iout = -142 mA
- 0.7VDD - 3.1 V
VOLmin Output Low Voltage Minimum3.3 V: Iout = 16(VDD) mA5.0 V: Iout = 95 mA
0.6VDD - 2.2 - V
VOLmax Output Low Voltage Maximum3.3 V: Iout = 38(VDD) mA5.0 V: Iout = 206 mA
- 0.18 VDD - 0.71 V
H4CPlus DC ELECTRICAL CHARACTERISTICS (Continued)
H4CPlus_Series MOTOROLA
29
*For the bidirectional extended voltage range I/O, the bidirectional input macro must be a 3.3V System and 3.3V Core macro.N/A = Not Applicable
Table 13. DC Electrical Characteristics for H4CPlus Series (T a = -40˚C to 85˚C)
Sym. Parameter ConditionVDD= 3.3V±0.3V
Guaranteed VDD=5V±10%Guaranteed Unit
Min. Max. Min. Max.
Leakage Current for Fail-Safe and Extended Voltage Range Bidirectional I/O
Ioff
Leakage Current for bidirectionalFail-Safe I/O,No pull resistor
VDD = OVDD5 = 0 to MAX Vin= VDD or VSSOutput = Off-State
N/A N/A -20 +20
µALeakage Current for bidirectionalFail-Safe I/O,with pulldown resistor
VDD = OVDD5 = 0 to MAX Vin= VDD or VSSOutput = Off-State
N/A N/A -20 +200
Ioff*
Leakage Current for bidirectionalextended voltage range I/O,No pull resistor
VDD = OVDD3 = 0 to MAX Vin= 0 to 5.5 VOutput = Off-State
-20 +20 N/A N/A
µALeakage Current for bidirectionalextended voltage range I/O,with pulldown resistor
VDD = OVDD3 = 0 to MAX Vin= 0 to 5.5 VOutput = Off-State
-20 +200 N/A N/A
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H4CP/D
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