Osu Cadence Notes

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DESIGN FRAMEWORK I I CAD PAGE

EXAMPLE:

DESIGN AND SIMULATION OF AN INVERTING AMPLIFIER

This example will help you familiarize with Design Framework II. You will design a

simple inverting amplifier, and then observe its operating point and frequency

response behavior. This will show the most important commands and steps to use

when working with schematics in DFII.

Before starting with the design example, there are some details that are worth

mentioning:

The appendix contains some notes about using theon-line help feature,andusing the mouse. There's also a table with keyboard shortcuts.

Most of the commands in DFII can be accessed in multiple ways: pull-downmenus,shorcut keys, buttons in toolbars, etc. In the described example, all the

commands are referenced by their position in the pull-down menus.

The most used key in DFII is ESC. It is used to cancel on-going commands.The following picture shows the inverting amplifier circuit, ready for netlisting. The

next section explains how to draw it in DFII.
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Figure 1: Design example.

1. Create a library for your new design:

>From the library manager window:

File->New->Library

Type a new name, such as TEST.

Under the heading "Technology Library", choose "Compile a new techfile".

Then from the dropdown menu choose "TSMC 0.24u CMOS025/DEEP (5M, HV FET).

Click OK

2. Create a new cell, where you will design the inverter:In Library Manager:

Highlight your new library (TEST if that is what you chose).

File->New->Cellview


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Choose library TEST, cell name "inverter", view name "schematic", and Tool

"Composer-Schematic". Click OK.

A schematic window will open.

3. Design your circuit:

3.1 Placing components:

For this inverter, you will need an nmos transistor, a resistor, a capacitor, and power

and ground nodes.

>From Schematic window:

Add->Instance

Add Instance and Component Browserwindows will open.

Make sure the Library in the Component Browseris set

toNCSU_Analog_Parts.

Use the Component Browserwindow and single clickN_Transistors, then

select nmos4 and place it.

Use the same procedure to go under R_L_Cand place a res and cap, from

library NCSU_Analog_Parts.

Also, from the NCSU_Analog_Parts, get the symbols

for vddand gndfrom Supply_Nets (they define the net names for the powerand ground nodes).

If you make any mistake, you can always use:

Edit->Delete or

Edit->Rotate or

Edit->Move or

Edit->Stretch

You need to change the properties of some components:


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Edit->Properties->Objects

Select the transistor, and change the following parameters:

Width: 60u

Length: 1.2u

Make sure you change the Width andLength boxes to these values, not

the Width(grid units) andLength(grid units) boxes.

NOTE: For this design kit you can only set transistor lengths and widths in

multiples of grid units(.06uM). Keep this in mind when making your circuits.

Select the resistor. Edit the properties to set a resistance of 4k Ohms.

By default, the capacitor value should be 1 pF. You can leave it that way.

3.2 Connect components:

Connect the component terminals as shown in figure 1, using:

Add->wire (narrow)

4. Adding Pins:

By adding pins, you can identify the I/O ports of the schematic. At a later stage, you

can also use pins as connection points for hierarchical designs. To learn more about

this, see the section aboutcreating symbols.

Add->Pin

Type the pin name, such as Vin, select the direction as "input", and place it in

the schematic. Do the same for Vout, selecting the direction as "output".

5. Simulate:

This section explains how to simulate using HSPICE. As of updates applied Feb.

2012, you should now be able to simulate with Hspice from within Virtuoso, use theintegrated analysis tools, and everything else you would want to be able to do. (You

can view results by using theResults menu. Explore the Direct Plot, Print, and

Annotate sub-menus. To see DC node voltages, operating conditions, etc, use the

options inRestuls->PrintorResults->Annotate. For waveforms, look inResults-

>Direct Plot.) If you know how to use these tools or would like to play with them,

please feel free to try. If the integrated simulation environment works for you, then
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great - you will not need to do the steps in this section or the following one (View

Results). However, as a backup, you should try be comfortable with exporting the

netlist manually, simulating with hspice from the command line, and viewing the

results in an external viewer. This procedure is explained in this section and the next...

It's possible to generate a complete netlist from the schematic and to simulate itoutside the Cadence tools environment.

Invoke the Analog Environment simulation window from:

Tools->Analog Environment

Then, in Analog Environment Simulation Window:

Setup->Simulator/Directory/Host

Set the simulator to hspiceS.

Generate netlist:

Simulation->Netlist->Create Final

The netlist is displayed in a special window. Use the menu File->Save

As to save it in your work directory. Let's name it 'inverter.sp'.

Note that this will save the netlist in the Cadence directory that you

created in the Starting Design Framework II step. If you wish to save it

to a different location, you must enter the complete target path

(beginning from root).

You can now simulate this netlist file with HSPICE. But before you do, it's necessary

to add some more things. With your favorite editor, open the file and add the

following components:

Vdd vdd! 0 DC 5V

Vin vin 0 DC 0.75 AC 1

Also, define a dc operating point and an ac analysis with the following:

.AC DEC 10 1e3 1e9

Finally, you need to remove the following line:
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.OPTION INGOLD=2 ARTIST=2 PSF=2 PROBE=0

... and to replace it with:

.OPTION POST

Now you can start the simulation:

hspice inverter.sp >! inverter.lis

If everything goes well, you will get the message 'hspice job concluded'. Otherwise, if

something goes wrong, you will get 'hspice job aborted'.

6. View Results:

You can see the DC operating point by opening the file inverter.lis with a text editor,

and searching for the keyword 'mosfets'. The node voltages can be found if you

search for the keyword 'operating'.

To see the frequency response, you will have to use a graphic postprocessor, such as

CosmosScope:

Start CosmosScope from the unix prompt (just type 'scope'). In CosmosScope window, select File->Open->Plotfiles, and under the 'Files of

type' menu select HSPICE. Navigate to the correct directory and select the

file inverter.ac0.

In the window that opens, you will see a list of nodes to plot. Double-click onthe node Vout.

To zoom, click and drag on either axis. The Tools->Measurement Toolis alsovery useful and intuitive. You may print the plot withFile->Print.

Before you print, change the the background of your plots from black towhite. This is done by Graph->Color Map->Mono.

====================================================

WORKING WITH SYMBOLS

If you want to use your design in other schematics, you need to create a symbol for

it.

This is equivalent to the use of subcircuits in HSPICE. It gives a hierarchy to your

project, making it easier to organize.


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Creating a new symbol

First, in your schematic, remove any superfluous components that you have used in

the previous example for the simulation (vdc for the power supply and for the input

signal). These components will be defined again later.

Assign input and output pins (if you have not already done so):

Add->Pins

Type the pin name, such as Vin, select the direction as "input", and place it in

the schematic. Do the same for Vout, selecting the direction as "output".

The schematic will look like this:

Figure 1: Inverter schematic with pins.

As a side comment, note that the net names changed and have now the same name

as the pins. There are other ways to name the nets. You can find more about it intheFAQ.

Next, create the symbol:
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Design->Check and Save

Design->Create cellview->From cellview, click OK.

A new window will open with the symbol view. By default, the symbol shape is a

rectangle, but we can change it. Since this design is an inverter, we will draw atriangle and put a small circle at the output. To do this, use:

Add->Shape

There are several shapes available: line, rectangle, circle, etc.

You will want to delete the green rectangle, draw the new shape, and move the

terminals to new positions. The editing commands are similar to what you had for

the schematic window.

You will also need to change the Selection box (the red rectangle), which defines the

limits of the symbol. This can be done automatically by:

Add->Selection box

A window appears with only one button: "Automatic". Click it and the

selection box will automatically adjust to the limits of your symbol.

Don't forget to check and save. The symbol may now look like this:

Figure 2: Inverter symbol.

You can now close the Symbol Editing window. It wont be necessary anymore.


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Using the symbol in other schematics

Create a new schematic, using the instructions described inCreate a new cell.Give a

name such as test_inverter.

You place this symbol in the new schematic in the same way that you placed any

other components, with:

Add->Instance

This time changing the Library to your library and clicking on Uncategorized.

Your symbol should be here.

Now, you can define power supplies in the new schematic. If you place new vdd and

gnd components, they will be implicitly connected to the correspondent vdd and gnd

components that are inside the inverter.

For simulation, you can connect a 'vdc' to the input terminal of the inverter, and acapacitor at the output terminal.

Here is an example of a possible setup:

Figure 3: Using the inverter symbol in a new schematic.

To move in the hierarchy, select the inverter, and then:
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Design->Hierarchy->Descend Edit

You can choose the schematic or the symbol for editing.

To return to the previous schematic, use:

Design->Hierarchy->Return

========================================================================

LAYOUT AND VERIFICATION

Layout Design

To open a new design, select the following from the Library Manager:

File->New->Cell View:

Choose the desired library and cell name, and type `layout' for the View Nameand 'Virtuoso' for the Tool.

A layout window opens. Also, the Layer Selection Window (LSW) opens at the

lefthand side of the screen.

Designing the layout of a circuit consists on selecting the desired layers from the

Layer Selection Window and using commands from the following list (keyboard

shortcut keys are in brackets):

Creating shapesCreate->Rectangle [r]

Create->Path [p]

Editing shapes

Edit->Move [m]

Edit->Stretch [s]

Edit->Copy [c]

Edit->Delete [del]

Edit->Properties [q]

Edit->Undo [u]Edit->Redo [U]

Measuring distancesMisc->Ruler [k]

Misc->Clear Rulers [K]

Window commands Zoom In [z]


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Zoom In by 2 [^z]

Zoom Out By 2 [Z]

Fit All [f]

Redraw [^r]

Other commandsGravity On/Off[g]

Display levels (0-20) [F]

Display levels (0-0) [^f]

Design Rule Checking (DRC)

At any time during your design, you can verify if any dimensions are being violated.

In the layout window, select:

Verify->DRC...

Set the rules libraryto: your library (TEST if you are continuing the examplefrom earlier).

The DRC will now run, and if everything is okay, it should finish with the message:

********* Summary of rule violation for cell "inverter layout" *********

Total errors found: 0

If there are errors, the message will contains statistics about which rules were

violated. To see where and why, you can use one of the following:

Verify->Markers->Explain:

Click on one of the errors in the layout window. A text window will open with

a description.

Verify->Markers->Find:

A dialog window will open. You can use the

buttons Apply, Previous and Next to go through the list of errors. If you select

the 'Zoom To Markers' button, the layout window will zoom in the respective

error.

Extracting the layout:

The extraction tool identifies devices and nodes in the layout. It creates a special

view, named extracted', which contains this information. Later, this view is required

for netlist generation, and can be used by a simulator or by the LVS tool.


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Verify->Extract...

Again set the rules libraryto: your library (TEST for example). If you want to

include paracitic capacitance in the extraction press the set switches' button

and select "PARASITIC_C". Press OK.

The extraction should finish with the message:

********* Summary of rule violation for cell "inverter layout" *********

Total errors found: 0

If there are any mistakes, you can find about them in the same way that is described

above for the DRC. First you have to go to the Library Manager and open the view

`extracted' of the cell that you want to simulate.

The rest of the procedure is identical to what was described for schematic

simulation. Open the Analog Artist Simulation Window from the Tools menu, andthen refer to the section aboutsimulation.

Layout Versus Schematic (LVS)

The LVS tool is used to compare the layout with the schematic, identifying any circuit

related differences that might exist between these two views. It reports about circuit

nodes and device sizes. You can call the LVS tool from the window containing the

layout view or the extracted view. First however we need to setup some LVS

parameters.

NCSU->Modify LVS Rules...

Set all the boxes except theIgnore FET Body Terminal.

Now we can run LVS.

Verify->LVS...

The LVS dialog window opens.

Most of the fields should be automatically filled out. Make sure that everything is

consistent (view schematic is for schematic netlist and view extracted is for theextracted netlist).

In the Rules File field, type `divaLVS.rul' and the rules library is again your library.

Make sure Rewiring, Device Fixing, and Terminals are all selected.

Press the Run button to start the LVS job. Wait until it finishes. A message window
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will pop-up on the screen when finished.

To see the results of the LVS job, press the Output button. A text window containing

the file './LVS/si.out' will open. The result of the comparison is stated in one of three

possible sentences:

1. The net-lists match.

2. The net-lists failed to match.

3. The net-lists match logically but

have mismatched parameters.

In the first case, you can go celebrate. In the second case, one or more nodes in your

layout or in your schematic have a mistake. In the third case, all the nodes are

correct, but one or more devices have the wrong size.The output file also contains a list of devices, nodes and terminals for the layout and

for the schematic. From this list, you can find how many errors exist, and in which

view.

For both of the last two cases, it is necessary to track down the problem.

Unfortunately, this is not a straightforward procedure, but more of a debugging

process. The following are tools that are available to assist you in this:

In the LVS window, press the Error Display button.Use the buttons on the top of the window (First, Next, etc) to highlight the

errors. You can select which type of error you want to see from the bottom

part of the window. Note that the highlighted errors will appear in the "active

window". You can make the schematic window or the extracted window

active by clicking on one of them. A window is active if the status bar at the

top is green.

In the LVS window, press the Info button.As an example, if you have a merged net in your schematic, you can press

the Merged Nets button in the schematic section, and a text window will open

with a list of merged nets. Another example: if you have mismatched


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parameters in your layout, you can press theAudit button in either extracted

or schematic sections.

In the extracted window, select Verify->Probe.If you select the option 'cross probe matched', you can find correspondences

between the views. For example, click on one of the nets in your schematic

window. The same net will be highlighted in the extracted window.

Simulating the layout:

First you have to go to the Library Manager and open the view `extracted' of the cell

that you want to simulate.

The rest of the procedure is identical to what was described for schematic

simulation. Open the Analog Artist Simulation Window from the Tools menu, and

then refer to the section aboutsimulation.

Instantiating cells:

To make layout design more simple, it's possible to define blocks which are to be

used several times in the same layout. The following example describes how to do

this for a transistor.

Design or copy one of your transistors to a separate place. Select the whole

transistor and choose:

Edit->Hierarchy->Make cell

Fill in a name for the cell, for example, `nmos_10_1', (which stands for w=10u

and l=1u, just to keep track of what it is).

You will see the cell as a red outlined box. The contents of this box are now in a

different hierarchy level, and can only be accessed withhierarchy commands.

This cell exists now in the library manager. To place more copies in your layout,

select:

Create->Instance

Type the name of the library, cell and view, and place it with the mouse.
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You can also create arrays of cells, which can be used, for example, to make

transistors in parallel. When creating an instance, the form gives you options to

change the number of columns or rows, and the distance between the elements.

To return one of the cells to normal layout rectangles, select the cell and use:

Edit->Other->Flatten

Editing hierarchical designs:

When you want to edit a cell, you have to navigate between different hierarchy

levels. This is done by selecting the desired cell and using:

Design->Hierarchy->Descend [X]: Descends to cell.

Design->Hierarchy->Edit in Place [x]: Allows editing while looking at the top

level.

Design->Hierarchy->Return [B]: Returns to top level.

Of course, you can also edit the cell by opening it from the library manager.

To see all the hierarchy levels, you can use the shortcut key F. To see only the top

level, use ^f. This information can be accessed from the menu Design->Options-

>Display. In the dialog box, there is a field with the `from' and `to' display levels.

====================================================================

EXAMPLE:

LAYOUT OF AN INVERTING AMPLIFIER

This example will help you to create a layout for the inverter you designed in the first

example. It will go over how to create mosfets, resistors, and capacitors in our

process. There are many considerations to take into account when deciding how to do

a layout. This is NOT an example on layout techniques, but more of a generalized

example to help get you farmiliar with Virtuoso and laying-out some basic

components.

The following picture shows a layout for the inverting amplifier, ready for extracting.The next section explains how to make each of the separate components in Virtuoso.


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Figure 1: Layout example.

1. Create a new cell, where you will layout the inverter:

In Library Manager:

Highlight your inverter schematic library (TEST if that is what you chose).File->New->Cellview

Choose library TEST, cell name "inverter", view name "layout", and Tool

"Virtuoso". Click OK.

A layout window will open.


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2. Laying-out the components for your circuit:

For this inverter we will need to layout an nmos transistor, a resistor, and a capacitor.

The following sections will describe how to make these components.

2.1 Layout of MOSFETs:When laying-out MOSFETs, we actually have preset cells which we can draw from.

From the Layout window:

Create->Instance

Browse the library name, choose your library name (TEST for example),

choose nmos from the Cell, and layoutfrom the View.

Click back on the Create Instance window to setup some parameters.

When making MOSFETs you can create a single transistor, or use fingering or

multipliers to create multiple transistors at once. Fingering makes transistors which

are connected in series, mulpliers create transistors which are connected in parallel.

For our layout we will be using a multiplier to make multiple transistors which will be

connected to be equivalent to one really wide transistor.

Change the Multiplierbox to 5.

Change the Width box to 12.0u M.

Change theLength box to 1.2u M.

You can now place the nmos layout wherever you would like.

Clicking SHIFT-F will show all levels and allow you to see inside the cell you

just placed (CNTRL-F will change back to just showing the top level).

Now we need to connect together the drains, gates, and sources and place some bulk

connections.

In the LSWwindow change the current layer topoly(dg).

Create->PathNow draw a poly path connecting one gate to another accross the top of the

transistor block. Make the path extend up alittle ways from the top of the

transistor block before going over and down. Repeat this until all gates are

connected together.


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Repeat this process to using metal1 to connect every other drain/source

connection together across the top.

Do the same thing for the opposite every other drain/source along the bottom.

Your finished transistor should look similar to the following:

Figure 2: NMOS example.

Lastly we need to create some bulk connections. We will create these across the left

side of the transistor block.

Create->Instance


chooseptap from the Cell, and layoutfrom the View.

Click back over on the Create Instance window.


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When placing instances you can place multiple instances in a matrix type formation

by specifying the number of rows and columns to place. We will now use this to place

a column of ptaps along the side of the transistor block.

In theRows of contacts box put 15.

Place the block ofptaps to the left of the transistor block.

We now have a transistor with single gate, drain, source, and bulk connections. Make

sure to doDRCbefore continuing on to make sure everything was placed correctly.

2.2 Layout of Resistors:

There are several ways to make a resistor in layout. For a few reasons (issues with

poly resistors using this design kit) we will make our resistors with nwell. Keep in

mind that normally nwell resistors end up being nonlinear resistors, but for the

purposes of this class (since we are simply doing LVS and extracting to HSPICE) wewill use them and consider them linear.

Create->Instance


choose ntap from the Cell, and layoutfrom the View.

Place the cell on the layout.

An nwell transistor will extract at approximately 1.19k Ohms per square for our setup.

The width of the nwell region is set by design rules to be atleast 1.44uM. This means

to get the 4k resistor we want we will need a length of around 4.92uM. Also the nwellsquares at each end of the resistor must be atleast 1.44uM squares, which means they

also add 2.88uM to the length on the ends.

In theLSWwindow change the current layer to nwell(dg).

Window->Create Ruler

Draw in a vertical ruler measuring 7.8uM. Draw in a horizontal ruler off one of

the corners measuring 1.44uM.

Create->RectangleDraw a rectangle of nwell the size of the rules you just made.

Edit->Move

And move the ntap you made previously to the centered end of one side of the

rectangle.
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Edit->Copy

And click on the ntap again to copy it and move the copy down to the other

side of the rectangle.

In theLSWwindow change the current layer to res_id(dg).

Now draw a rectangle of the res_idover the middle of the nwell. You will need

to have it centered (0.24uM away from each NTAP edge) and the width of it

atleast to the edges, if not overlapping them. Your finished product should look

something like the following:


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Figure 3: Resistor example.

We now have a resistor with metal1 connections on each side. Once again, make sure

to doDRCbefore continuing on.

2.3 Layout of Capacitors:The type of capacitor we will be making is called a mimcap. It is made up of two

closely spaced layers of metal. For our setup the capacitor we will be making will

have a capacitance of roughly 1fF per 1uM^2. For this reason most capacitors will be

very large in comparison to some of your other components.

We need a 1pF load capacitor for our inverter. This works out to 1000uM^2. The

square root of this sets each side to 31.6227uM if we decide on a square capacitor.

Since our setup only goes in steps of .06uM, we will round down to 31.5uM.


Set a horizontal and vertical ruler at 31.5uM each.

In theLSWwindow change the current layer to metalcap(dg).

Create->Rectangle

Draw a rectangle ofmetalcap the size of the rules you just made.

Use the same steps to draw a rectangle of the layermetal5 directly ontop of

the metalcap rectangle you just made.

Now we need to make a metal4 layer for the other side of the capacitor. This layer

will need to be larger than the previous 2, by about 1uM on each edge.


Set a 1.02uM ruler (remember the .06uM steps) out from each edge of the

previous rectangles.

Now switch to the metal4 layer and draw a rectangle which is larger than the

previous rectangles on all sides by 1.02uM.

We now need some contacts to connect the metalcap layer to the metal5 layer. This

way we will have one connection of the capacitor frommetal4 and one from metal5.

Create->Contact

Change Contact Type to M5_M4.


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We will place multiple contacts to help fully connect the two layers.

Change the Rows box to 15.

Change the Columnsbox to 15.

Change theDelta Xbox to 2.04.

Change theDelta Ybox to 2.04.

Now place the group of instances in the center of

the metalcap/metal5 rectangle. If you dont get it like you want the first time, no

worries, the whole group will move together when you adjust it's position later.

Your finished capacitor should look something like this:


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Figure 4: Capacitor example.

Now you have a capacitor with two terminals, the top at metal5 and the bottom

at metal4. Remember, make sure to doDRCagain to be sure you aren't violating any

rules.

3. Routing and Adding Pins:

Now that we have all the components we need to make our inverter, we can simply

move them around and route the correct connections. As mentioned earlier, this

example is less focused on the techniques used for layout, and more on how to make

some general components and get the reader familiar with using the tool. However,


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a couple quick pointers will be given here.

When putting together your layout, place large metal rectangles(metal2 works well) along the top and botttom for your Vdd and Gnd rails. Try

to place all of your layout within these rails. Also, when connecting to these

(or any routing connection really) its always a good idea to put as many via

connections as possible. You can use the same multiple contact placement as

was used with the capacitor to make this fast and neat.

Although it's not really obvious from this example, it is also good practice totry and make your layout as symetrical as possible.

When routing large layouts it's a good idea to try and keep track of what youare routing with. Route withpolyas little as possible since it's resistance is

higher than metal. It also helps to set some general directions for different

layers. For instance, for all horizontal traces use metal2, for all vertical traces

use metal1. This will help keep your layout neat and organized.

After routing all your connections for the inverter (don't forget toDRCoften), you

simply need to add pins for vin, vout, vdd!, and gnd!. Make sure to use vdd! and gnd!

(not uppercase VDD! / GND!), otherwise the extracted view won't netlist properly.

Create->PinType the Terminal Name, such as vin.

Select the I/O Type, such as "input" (although inputOutput is always a safe bet

if unsure).

Check the Display Pin Name box.

Select the Pin Type based on what layer your connection is (Vdd and Gnd

should be metal2 if that is your rail's layer).

Simply place the pin and pin label where you want them.

After doing this for all the nodes your layout is complete!

4. Extraction and LVS:

So now your layout is complete. Now we need to check it to make sure it is the same

as the schematic that we did in the previous example. First,extractthe layout using

the procedure described previously.
http://web.engr.oregonstate.edu/~moon/ece423/cadence/layout.html#drchttp://web.engr.oregonstate.edu/~moon/ece423/cadence/layout.html#drchttp://web.engr.oregonstate.edu/~moon/ece423/cadence/layout.html#drchttp://web.engr.oregonstate.edu/~moon/ece423/cadence/layout.html#extracthttp://web.engr.oregonstate.edu/~moon/ece423/cadence/layout.html#extracthttp://web.engr.oregonstate.edu/~moon/ece423/cadence/layout.html#extracthttp://web.engr.oregonstate.edu/~moon/ece423/cadence/layout.html#extracthttp://web.engr.oregonstate.edu/~moon/ece423/cadence/layout.html#drc


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Now open the newly saved extracted view (placed in the same Cell as your layout),

and go through the procedure forLVSdescribed before. If all goes well your netlists

will match!

============================================================

PRINTING

You can print from the schematic window by doing:

Design->Plot->Submit

In the submit form, uncheck the "Plot With Header" box. I always uncheck it,

because it causes Cadence to print an additional page with information about theplot.

To choose the printer, click the "Plot Options..." button. In this form, you can choose

from nearly any engineering printer, or encapsulated postscript from the drop down

box titled Plotter Name. The encapsulated postscript file generates a .ps image that

can be found in your /usr/tmp directory. You can also choose the size of the plot

from this form. I usually click on "Fit To Page".

After you made all your selections, click OK in both forms.

You can check the status of the printer with:

Design->Plot->Queue Status

==============================================================

FREQUENTLY ASKED QUESTIONS

1. Cadence crashed while I was working on a design. Now Cadence doesn't letme edit my design, saying that it is locked.

Everytime a design is open for editing, Cadence locks it so that no other

process (or somebody else) can change it. It's a security feature.

Whenever Cadence crashes, it may happen that a design is left locked. In that

case, when you try to open it again, Cadence thinks the cell is still being edited
http://web.engr.oregonstate.edu/~moon/ece423/cadence/layout.html#lvshttp://web.engr.oregonstate.edu/~moon/ece423/cadence/layout.html#lvshttp://web.engr.oregonstate.edu/~moon/ece423/cadence/layout.html#lvshttp://web.engr.oregonstate.edu/~moon/ece423/cadence/layout.html#lvs


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and doesn't let you change it. If this happens, here's how you can unlock the

design:

o Find the path to the affected cell. Just try to open it and CIW will reportthe path.

o Build the following expression in the CIW prompt:ddLockFree(ddLockPath("path to affected file"))

The locking service can take a long time to process the request. If you still

have problems opening cells, try the following:

o Exit from Cadence.o At the shell prompt, type: setenv CLS_CDSD_COMPATIBILITY_LOCKING

NO

o Restart Cadence and repeat the above ddLockFree command.

2. If a spectreS simulation is interrupted for some reason (power glitch, crash,etc), is there a way to continue the simulation from the point where it broke?

Yes, there is a way. Here's how:

o Go down to the directory~/simulation/cellname/spectreS/schematic/netlist, where cellname is

the cell schematic that you were simulating.

o Edit the file runSpectre, and add the option +recover to the spectrecommand line.

o Invoke spectreS by typing runSpectre at the shell prompt. Spectre willcontinue the simulation starting from where it was interrupted.

o Once the simulation finishes, the results can be loaded back into AnalogArtist by selecting Results->Selectin the menu.

Important: Spectre will not append to the previous data file. It will create a

new one. Therefore, before restarting the simulation, you should save the

previous data using the Results->Save Results menu option.


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3. In SpectreS, how can I save simulation data points into a file?One way is to use the printvs button in the calculator. However, this method

only allows for a maximum of 1900 points. If you need more, it's better to use

the Ocean command ocnPrint. In the CIW, type the following:ocnPrint( v(out) ?output "./myOutFile" ?from A ?to B ?step step_size )

This will save data points of signal v(out), from point A to point B, in

increments ofstep_size, to the file myOutFile. If you want to import the data

in MATLAB, include the following in the above command:

?numberNotation 'engineering

4. Giving names to the wires:Sometimes a design can have many connections. Connecting terminals that

are far apart or in awkward places can be difficult and can make the schematic

hard to understand.

It's easier to draw small pieces of wire on the terminals and to give them the

same name. Then, Design Framework II will consider that the terminals are

connected to the same net.

To name wires, do the following:

Add->Wire Name

Type the wire name, and click on the net.

5. Looking at transistor parameters: (for spectreS only)If you want to know a specific DC operating point parameter for a transistor(gm, vdsat, etc), follow these instructions:

In the Analog Artist Simulation window, select:

Tools->Results Browser

Click OK in the project directory form.


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The results browser window opens. This window can be used to access any

information related with the simulation. For example, to find the gm of a

transistor, follow this path:

schematic->psf->Run1->opBegin.info->[transistor]->gm

The results marked in yellow can be selected and pasted in the calculator

window (with the left mouse button), or directly in the waveform window

(with the right mouse button), depending on their nature.

6. Changing the number of digits displayed:There is no menu command to do this. You have to use a SKILL command(SKILL is the language on which Cadence is supported).

In the CIW (or log window), type:

ael PushSignifDigits(8)

...and press return. Make sure you type the right capital letters.

This will change the number of significant digits to 8.

===============================================================

APPENDIX

HELP RESOURCES:

The on-line manual can be accessed from Help buttons in any Cadence window.

If invoked from a Cadence window, the opened page will be related with the tool

that is being used.

ABOUT USING THE MOUSE:When no command is issued, the left mouse button is used for selecting

components. You can use SHIFT to add to the selection, ctrl to remove from the

selection. You can also draw a box around the components you wish to select.

It's a good practice to deselect all components (ctrl-d) once you finish each

command, so that there are no unwanted changes.


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When in doubt about the function of the mouse, look at the bottom of the CIW or

schematic window: there's a line indicating the function of each mouse button

(mouse L,M,R):

KEYBOARD SHORTCUTS:

These are for the schematic and symbol editing windows only:

Most important keys:

ESC - Cancel command

^d - Deselect all

Add component: i

Add wire label: l

Add wire: wAdd pin: p

Copy: c

Check and Save: X

Delete: del

Edit properties: q

Fit: f

Hierarchy->Descend:E

Hierarchy->Return: ^e

Move: MRedraw: F6

Redo: U

Rotate: r

Stretch: m

Undo: u

Zoom in: z


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Zoom in by 2: [

Zoom out by 2: ]

These are the default shortcut keys. If you would like to change any of them,

you can do it by editing the file 'schBindKeys.il' in your project directory, andthen loading it into Cadence by typing 'load schBindKeys.il' in the CIW.

================================================================

Date post:	14-Apr-2018
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