OTIC FILE COPY DTIC Ln ELECTE .S JUL 17 1990 Final Report on the Project for Development of New Protocol Hardware and Software for LSI-l1 to Accommodate AUTODIN II ADCCP-HDLC, and X.25 Appendix A RMMMM1:7 STATEM A APPIov d tow puf rel -q I__ Dukhu U eie,.a Sponsored by: Defense Advanced Research Projects Agency (DOD) Order No. 4024 Under Contract No.: MDA903-81-C-0038 Issued by Dept. of Army, Defense Supply Service Washington, Washington, D.C. 20310 Submitted to: Defense Advanced Research Projects Agency Information Processing Techniques Office 1400 Wilson Boulevard, Arlington, VA 22209 Submitted by: Associated Computer Consultants 720 Santa Barbara Street, Santa Barbara, CA 93101 (805) 963-9431 The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the U.S. Government. *1 0-7 16 '41
Transcript
OTIC FILE COPY
DTICLn ELECTE
.S JUL 17 1990
Final Report on the Projectfor Development of New
Protocol Hardware and Softwarefor LSI-l1 to Accommodate
AUTODIN II ADCCP-HDLC, and X.25
Appendix A
RMMMM1:7 STATEM AAPPIov d tow puf rel -q
I__ Dukhu U eie,.a Sponsored by:
Defense Advanced Research Projects Agency (DOD)Order No. 4024
Under Contract No.: MDA903-81-C-0038Issued by Dept. of Army, Defense Supply Service
Washington, Washington, D.C. 20310
Submitted to: Defense Advanced Research Projects AgencyInformation Processing Techniques Office1400 Wilson Boulevard, Arlington, VA 22209
Submitted by: Associated Computer Consultants720 Santa Barbara Street, Santa Barbara, CA 93101(805) 963-9431
The views and conclusions contained in this documentare those of the authors and should not be interpretedas representing the official policies, either expressedor implied, of the Defense Advanced Research ProjectsAgency or the U.S. Government.
*1 0-7 16 '41
XQCP.MM.V004January 1983
xo/cp
MAINTENANCE MANUAL
U~i~jm~u --
JuStii'c';""
By -____
Avio 3111 ofDist Special
Copyright (1983) byAssociated Computer Consultants720 Santa Barbara StreetSanta Barbara, CA 93101(805) 963-9431
5.1 Protocol Processor .................... 5-15.2 Microprocessor Programming ................ 5-15.3 Host Programming .......................... 5-15.4 Communication Registers ................... 5-25.5 Contiguous Block of Addresses ............. 5-2 i5.6 Starting the DMA Transfer ................. 5-25.7 Sense of Read and Write With Respect
to the Communication Register .......... 5-3
Table 5-1 XQ/CP: MDMA RCSR (ReceiveControl and Status Register ............ 5-4
Table 5-2 XQ/CP: MDMA TCSR (TransmitControl and Status Register ............ 5-7
8. PDP-11 Macro-li Language Reference ManualDigital Equipment Corporation
9. Reference Manual for the Microbench Z80Program Development SystemsVirtual Systems, Inc.
10. Z80 CPU Technical ManualZilog, Inc.
11. XQ/CP Software Support Monitor ManualAssociated Computer Consultants, XQCP.SSMM.V001
2-1
E L .....
XQ/CP
MAINTENANCE MANUAL
CHAPTER 3 -GENERAL DESCRIPTION
CHAPTER 3
3.0 GENERAL DESCRIPTION
3.1 Packaging - The XQ/CP is packaged on three LSI-11 QBUS
compatable dual-height printed circuit boards. These boards
plug directly into the QBUS backplane. The serial I/O line
connectors are mounted on a standard 19 inch, rack mountable
panel.
3.2 Alternate XQ/CP Board Arrangement - The three boards may
be connected in the two ways that are shown in Figure 3-1 on
the next page.
3.2.1 External Microprocessor Bus Interconnector - TheExternal Microprocessor Bus has its source on the P-Boardconnector Jl. Both the M-Board and the I-Board have an inputconnector (J2) and output connector (Jl). These boards may beconnected in either order shown. The connectors have beendesigned so that internal cables do not cross external cables(see Figure 1-2).
3.2.2 MDMA Subsystem Interface Bus Interconnection - TheI-Board provides the connection to the MDMA board via J3. MDMASubsystem Interface Bus continuation is taken from J3.
3.2.3 Serial I/0 Connection - Serial I/O connection isprovided by P-Board connectors J2 and J3. J2 is I/O Channel Aand J3 is I/O Channel B. Serial connection supports RS-232,RS-449, or MIL-STD-188-114. The receptacles on the serial I/Oconnector are either 25-pin or 37-pin according to theapplication.
3-1
OBUS aBUSAMOMA MDMA
I J3 3BOARD BOARD
J2 J 2
M I J3BOARD J3BOARD J
J2 J2
SERIAL PAE SERIALPAE
Example 1 Example 2
Figure 3-1 Interconnection Diagram
3-2
3.3 Functional Description - The XQ/CP is a microprocessor
device that communicates via two full duplex serial ports and
via the MDMA Subsystem Interface Bus (see Block Diagram 2700060
sheet 1, in Appendix A). The microprocessor is a Zilog Z80-
CPU. Standard Zilog peripherals have been attached to the
microprocessor bus to achieve the functional requirements of
the XQ/CP. These include a Z80-CTC for counter-timer and
interrupt functions, a DMA controlled Z80-SIO (Serial
Input/Output) for high speed serial communications, and two
additional Z80-DMA's for controlling data transfers in each
direction on the MDMA Subsystem Interface Bus. Other
attachments have been made to the microprocessor bus in order
to support the functional requirements of the XQ/CP. These
include RAM up to 32K X 8, ROM up to 32K X 8, a baud rate
generator, and communications registers that provide data and
control for Direct Memory Access (DMA) block transfers. The
XQ/CP starts operation at memory location 0000 after a reset.
3.4 Processor Module - The P-Board contains the basic Z80
microprocessor components (refer to the P-Board Block Diagram,
Drawing 2700060, sheet 2 in Appendix A). All Z80 components
communicate on a common bus. This bus contains data, address,
and control bits that operate according to rules specified by
Zilog. A separate address decoder recognizes I/O port
addresses and provides the enable signal for the Z80-CTC
(Counter-Timer), Z80-DMA's, Z80-SIO, and an on-board baud rate
generator.
1k.~ 3-31
I
3.4.1 The Z80-CTC - The Z80-CTC provides a four channelcounter/timer. One channel is dedicated to providing amechanism for off-board interrupts. The other three channelsmay be used by the programmer for general applications.
3.4.2 The Z80-SIO - The Z80-SIO provides two full duplexserial I/O channels. The serial line interface will meet theelectrical specifications of one of the following standards: IRS-232, RS-449, or MIL-STD-188-114. There is a Z80-DMA foreach of the serial channels to support high speed applications.The serial channels can be microprogrammed to run under full IDMA control or to be directly controlled by the CPU.
3.4.3 External Microprocessor Bus - The P-Board has driversand receivers for the External Microprocessor Bus in order toprovide a completely buffered external bus for the other boardsof the system.
3.5 Memory Module - The M-Board contains all memory directly
addressed by the XQ/CP's CPU. The External Microprocessor Bus
is completely buffered and decodes according to a memory
mapping ROM. This ROM determines the response addresses of RAM
and ROM. Each of these areas of memory is expandable up to
32K X 8. The RAM is expandable in increments of 16K; the ROM
is expandable in increments of 4K or 8K (refer to the M-Board
Block Diagram, Drawing 2600060, sheet 3 in Appendix A).
II.I
1
3-4 .
3.6 Interface Module - The I-Board provides the data path
between the External Microprocessor Bus and the MDMA Subsystem
Interface Bus (see the I-Board Block Diagram, Drawing 2600060,
sheet 4 in Appendix A).
3.6.1 DMA Paths For External Microprocessor Bus - From thepoint of view of the Z80-CPU, two independent DMA paths exist:one for reading data blocks and one for writing data blocks.Each path is fully controlled by a Z80-DMA, which contains thetransfer count, memory address, status, and control. TheZ80-DMA obtains complete control of the Z80 bus andaccomplishes a block transfer without Z80-CPU intervention.
3.6.2 Data Path for MDMA.Subsystem Interface Bus - Control ofthe Subsystem Interface Bus side of the data paths andmanipulation of the Communication Register is done by the MDMA.The initial parameters are loaded into the Address and CountRegisters by a program residing in the LSI-11.
3.6.3 Block Transfer Process - Data transfer is initiated bysetting the appropriate bit in the Control Register. If theZ80-CPU has also completed the necessary initialization of itsside of the DMA path, then the block transfer will take place.Note that each process provides only the parameters for itsside of the data path and is not cognizant of any otherprocess's parameters. Control information may be passedthrough the corresponding Control Registers. The conversion of16-bit word length to 8-bit word length is accomplished byspecial hardware. The I-board also does MDMA SubsystemInterface Bus decoding and has switch settings to provide anInterrupt Vector and Identification Code.
3.7 Special Features - The XQ/CP has a number of features that
allow for different configurations, component options,
interface options, and expandability. A summary of these
features is provided in subsequent paragraphs.
3-5
3.7.1 Stand Alone Mode - Although the XQ/CP is normallyconfigured as a peripheral on the MDMA Subsystem Interface Bus,it may be used as a stand alone CPU. This is accomplished byjumpering in a clock generator on the P-Board (see Section4-4). Additionally, a reset pulse must be provided so thatprogram control begins from a known state.
3.7.2 Serial Interface Options - The serial interface may bespecified to be one of the following standards: RS-232, RS-449,or MIL-STD-188-114. This is accomplished by componentplatforms on the P-Board. These are installed by the factory,but they may be changed in the field.
3.7.3 Memory Options - Memory options are available thatdetermine the size, configuration, speed, and ROM type. Thespeed and ROM types are established by the factory based on Iavailability of parts. The standard size and configurationoptions are 32K bytes of RAM and 32K bytes of ROM with the ROMoccupying the lower half of the address space (see Figure 3-2).Other configurations are possible. For example, if a system isto be used in a development environment, a minimal amount ofROM might be desired as in Figure 3-3. Large fixedapplications could be configured as in Figure 3-4. RAM isavailable as 16K X 8 or 32K X 8. ROM is available in 4K X 8increments up to 32K X 8 or in 8K X 8 increments up to 64K X 8.
3.7.4 Switch Register and Display Register - A DIP switch maybe used to enter data to the XQ/CP. It is available as an I/Oport on the microprocessor bus. A set of LED's are alsoimplemented as an I/O port to display a byte of information.These facilities may be used in diagnostic, or other specialpurpose software, to obtain manually entered data or to displaystatus information.
3.7.5 External Microprocessor Bus - The XQ/CP provides acompletely buffered set of bus signals that is output on Jl ofany of the boards. This bus provides the XQ/CP with twoappealing characteristics: modularity and expandability. The !modularity that has been achieved in the packaging of the XQ/CPallows it to be either an MDMA Subsystem Interface Busperipheral or a stand alone microprocessor (without the I-Board). If it is desired to interface the XQ/CP to a differentdevice, the I-Board can be replaced by different interfacehardware. Similiarly, a different memory board can be designedand different Z80 peripherals can be added to the Z80 bus.
3-6
FFFF
RAM32Kx8
80007FFF
ROM32Kx8
0000
Figure 3-2 Standard Memory Configuration
8FFF
RAM32Kx8
1000OFFF
ROM4Kx8
0000
Figure 3-3 Developmental Configuration
FFFF
RAM16Kx8
C000BFFF
ROM48KX8
0000
Figure 3-4 Large Fixed Applications
L 3-7
CHAPTER 4
4.0 INSTALLATION
4.1 Physical Requirements - The XQ/CP is physically designed
to be mounted in a standard LSI-11 backplane. Three dual-height
backplane slots are necessary. A fourth slot is necessary for
the MDMA Controller if it is not already in the system. NOTE:
The recommended configuration of the boards is to occupy four
adjacent backplane slots. If this configuration is not
possible, please consult the factory. There are no special
physical requirements for any of the boards; all physical
parameters of the XQ/CP meet LSI-11 standards.
4.2 Electrical Requirements - The XQ/CP uses two voltages:
+5V DC and +12V DC. These are available from the LSI-11
backplane. All other voltages and signals are generated
internally. The current requirements for each of the boards
are listed in Table 4-1. These figures are the sums of the
maximum supply currents of all circuits on each board. All
three XQ/CP boards provide LSI-11 DMA grant continuity and
interrupt grant continuity. There are two I/O paths that are
normally connected to the XQ/CP. The first is a parallel path
to the MDMA; this meets TTL electrical standards. The second
is a serial path that meets one of the following Electronic
Industries Association (EIA) standards: RS-232, RS-449 or
4-1IL _
MIL-STD-188-114. The serial interface is installed by the
factory according to user requirements, but it is field
changeable.
+5V DC +12V DC
P-Board 2.26 A 272 mA IM-Board 3.26 A 960 mA 1I-Board 2.72 A 0
Table 4-1 Current Requirements
4.3 Interconnection - The connection requirements of the XQ/CP Ihave been described in Section 3.2 and have been illustrated in
Figure 3-1. A summary of that description is tabulated in
Table 4-2. Please refer to the previous discussion for more
jumpers, or (4) switch settings. All options are initially
set by the factory to default settings. Most applications will
require no changes to these defaults; most field changes will
only concern switch settings. Items (1) through (4) are listed
in increasing probability and increasing ease to change. Table
4-3 summarizes all options available.
OPTION CONFIGURATION OR SETTING
Memory mapping 1. Standard (default)2. Specified by user
I/O Port Options 1. Standard (default)2. Specified by user
Configuration* 1. With MDMA2. Stand Alone
Serial Interface* 1. MIL-STD-188-1142. RS-2323. RS-4224. RS-423
Subsystem Bus ID 1. 0 (default setting)2. Switch settable
LSI-11 Base Address 1. 776200 (default setting)2. Switch settable
LSI-11 Base Vector 1. 140 (default setting)2. Switch settable
* Must be specified when ordering
Table 4-3 Summary of Options
4-3
I4.4.1 PROM Options - Two functions are implemented by PROMs:Memory Mapping and I/O Mapping. These functions should notnormally be altered since a complete restructuring of all XQ/CPsoftware would be necessary. A detailed description of theoperation of these PROM's is included in Section 6. Figure 4-1and Table 4-4 summarize the memory and I/O addressing schemes.
FFFFI
IRAM
80007FFF I
ROM
0000 1Figure 4-1 Standard Memory Map I
iI
IIII
4-4 !
DEVICE DEVICE CODEOCTAL HEXIDECIMAL
SIO Channel A - Data 000 00
SIO Channel A - Control 001 01
SIO Channel B - Data 002 02
SIO Channel B - Control 003 03
CTC Channel 0 020 10
CTC Channel 1 021 11
CTC Channel 2 022 12
CTC Channel 3 023 13
LEDS/DIP Switch 026 16
DMA Receive (-R) Channel 040 20
DMA Transmit (-T) Channel 042 22
DMA SIO-A Channel 044 24
DMA SIO-B Channel 046 26
DMA-R Data Register 050 28
DMA-T Data Register 052 2A
DMA-R Control Register 054 2C
DMA-T Control Register 056 2E
Baud Rate Generator 060 30
Serial Port 064 34
Table 4-4 Standard I/0 Port Addresses
4-51
I4.4.2 Printed Circuit Board Jumpers - The printed circuit Iboard jumper options depend upon the type of RAMs and ROMs usedand whether the XQ/CP is used with the MDMA or in stand alonemode. The jumpers are PC traces that are fabricated with bothoptions connected. When the boards are assembled, one option Iis selected by cutting a trace. These jumpers are selected bythe factory and do not normally need to be changed in thefield. All jumpers are described in Table 4-5.
Board Pin Signal Description
M X01-1 +5V For 2532 EPROMs, cut trace between 2 and 3. IX01-2 RADR12 For 2564 EPROMs, cut trace between 1 and 3.X01-3 ROMP23
M X02-1 ROMEN For 2532 and 2564 EPROMs, cut trace ibetween 2 and 3.
X02-2 GNDX02-3 ROME
X03-1 RAMEN For all 4116 RAMs, cut trace between 2 and 3.X03-2 GND IX03-3 RAME
M X04-1 VM For standard memory map, cut trace jbetween 1 and 3. 1
X04-2 GND For special memory map, cut tracebetween 2 and 3. i
X04-3 SEL
X01-1 BCKB- For operation with MDMA, leave as isX01-2 BZCLK- For stand alone operation, cut trace
between 1 and 2.
P JMPl-1 CLKD For operation with MDMA, cut trace Ibetween 1 and 2. 1.
JMPl-2 BZCLK- For operation with MDMA, leave as is.
Table 4-5 Printed Circuit Board Jumpers
!!I
4-6
4.4.3 Component Platform Jumpers- Component platforms arelocated on the P-Board. This determines which serial interfaceis available. The interfaces available are: RS-232, RS-449, orMIL-STD-188-114. There are four receive and four transmitplatforms for each. These platforms are intalled by thefactory to support the desired serial interface. If a fieldchange is necessary, new platforms may be ordered from thefactory or they can be fabricated as shown on Drawings2600431-3. If RS-232 is required, U26, U29, U30, and U36 willbe absent and U28 and U38 will be present. For all otherinterfaces, U28 and U38 are absent and U26, U29, U30, and U36will be present.
4.4.4 Switch Settings- Switch settings determine addresses andvectors for the XQ/CP. They are given default settings are setby the factory (refer to Table 4-6). These default values areappropriate for systems where the XQ/CP is the only device onthe Subsystem Interface Bus (SIB). If there are multipledevices on the SIB, the switch settings must be changed so thatno two devices share the same vector or address. Table 4-7will be useful in determining the proper switch settings. Ifthe vector and address of the XQ/CP are changed, all factorysupplied software will have to be recompiled with the correctaddress. The base address and address range of the MDMA may bealtered by wire wrap jumpers on the MDKA board. Tables 4-6 and4-7 reflect options based on the standard MDMA configuration.Refer to the MDMA Maintenance Manual if this type of change isnecessary.
Selectable FactoryOption Digits - X Setting
SIB ID X 0 OctalXXX 000 Binary
LSI-11 Base Vector XX0 140 OctalXXXXX000 01100000 Binary
LSI-11 Base Address 776XX0 776200 Octal111111110OXXXXOOOO 111111110010000000 Binary
Table 4-6 Switch Selectable Values
4-7
.. .. . A
I
Switch Switch FactoryBoard Switch Signal On Off Default Option
I U60-1 ID03 0 1 ON - 0 SIB ID#I U60-2 ID02 0 1 ON - 0I U60-3 ID01 0 1 bN - 0
I U60-4 VCT07 0 1 ON - 0 LSI-11 BASEI U60-5 VCT06 0 1 OFF - 1 VectorI U60-6 VCT05 0 1 OFF - II U60-7 VCT04 0 1 ON - 0I U60-8 VCT03 0 1 ON - 0
I U65-1 AJ7 0 1 ON - 0 LSI-11 BaseI U65-2 AJ6 0 1 ON - 0 AddressI U65-3 AJ5 0 1 ON - 0I U65-4 AJ4 0 1_ON - 0I U65-5 .. 1. Not
I U65-6 ... UsediI U65-5 - -- NoI U65-6 - - -Ue II U65-8
P UIO - to 8 SWO- to SW7- 1 0 N/A N/A
Table 4-7 Switch Positions
iII
II1I1 _'I
1 XQ/CP
MAINTENANCE MANUAL
I CHAPTER 5 -PROGRAM4MING
J CHAPTER 5
5.0 PROGRAMMING
5.1 Protocol Processor - The XQ/CP is a fully programmable
communications processor specifically designed for serial
communication protocols. Protocol data is processed and moved
into and out of LSI-11 "Host" memory via Direct Memory Access
(DMA).
5.2 Microprocessor Programming - The XQ/CP Read-Only Memories
(ROMs) contain an ACC Monitor Program implementing an inter-
and Table 4-4 (I/O Ports Assignments) provide detailed
information concerning the hardware configuration.
5.3 Host Programming - Host-based application programs within
the LSI-11 access the serial paths by means of an ACC supplied
device driver for each Host Operating System.
j: 5-1
5.4 Communication Registers - The Monitor Program in the XQ/CP Iand the Host Device Driver interact via a set of Hardware
Communication Registers (see Figure 5-1). Eight registers are
available to the Host Device Driver: IReceive Control and Status Register (RCSR)Receive Data Register (RDR)Receive Address Register (RAR) IReceive Word Count Register (RWCR)Transmit Control and Status Register (TCSR)Transmit Data Register (TDR)Transmit Address Register (TAR) ITransmit Word Count Register (TWCR)
5.5 Contiguous Block of Addresses - The registers of the
Hardware Communication Register occupy a contiguous block of
addresses on the LSI-11 QBUS, starting at an address determined
by switch settings on the MDMA and XQ/CP circuit boards.
5.6 Starting the DNA Transfer - A DMA transfer is started Iwhen the Device Driver loads the data buffer starting address [into the TAR, loads a 2's complement word count into the TWCR,
and sets the GO bit in the TCSR. If a matching request has Ibeen issued by the XQ/CP based Inter-Processor Manager, the DMA
hardware on the XQ/CP is activated and the transfer takes Iplace. The microprocessor side of the transfer is set up by
programing the appropriate Z80-DMA and by the use of the
corresponding Z80 Control Register. These registers are
detailed in the remainder of this section.
!1ii ,
i .I'
I- 5.7 Sense of Read and Write With Respect to the Communication
Register - The register descriptions in Table 5-1 through 5-4
are written from the point of view of the program using the
registers. For example, sense of read and write of the MDMA
TCSR and RCSR is from an LSI-11 program. The sense of read and
write of the ZBO TCR and RCR is from a Z80 program.
5-3
Table 5-1 XQ/CP: MDMA RCSR (Receive Control and Status Register)
1 151 141 131 121 Ill 101 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 II I I I I II I I I I I I I I II I I I I . . .. . .. . I ' ' " I I I I
JERRINXMIZS31ZS21ZSIIZSOI Z80 IDBFIRDYIIENIADRIADRI IRECIRECI GO(I I I I I IHALTI I I 1 171 161 ISIGIRESI II I I I I II I I I I I I I I I
R R/W R R R R R R R/W R//WI-WR/W R W W
BIT 0 GO The GO bit. Setting this bit clearsRDY and initiates a DMA transfer fromthe XQ/CP to the LSI-11 processor.Clearing this bit has no effect. GOwill always read as zero. I
BIT 1 REC RESET The RECEIVE RESET bit. Setting thisbit resets the receive DMA hardware.The entire XQ/CP to LSI-11 channel is Ireset. Clearing this bit has noeffect. This bit will always read aszero.
BIT 2 REC SIGNAL The RECEIVE SIGNAL bit. This bit isset to one upon completion of areceive DMA data transfer. If IEN is Ipresently set, the LSI-11 isinterrupted. RECEIVE SIGNAL iscleared upon reading the RCSR by the ILSI-1l. This bit is read-only andwriting to this bit has no effect.
BIT 3 UNUSED This bit is undefined and is reservedfor future use. It is cleared uponsystem startup or reset. I
BIT 4 ADR16 This is ADDRESS BIT 16 for extendedaddressing operation. This bit isnever modified by the XQ/CP. It is Icleared upon system startup or reset.
BIT 5 ADR17 This is ADDRESS BIT 17 for extendedaddressing operation. This bit isnever modified by the XQ/CP. It iscleared upon system startup or reset. I
II.
I
~5-4
IBIT 6 IEN The INTERRUPT ENABLE bit. The LSI-11
program sets this bit to allow thechannel to request program interruptsand clears it to disallow interrupts.The channel only responds to interruptpolling cycles when this bit is on.It is cleared upon system startup orreset.
BIT 7 RDY The READY bit. This bit is on whenthe channel is not in DMA mode. Whenthe channel is ready, the MemoryAddress Register, the Word CountRegister, and the Control and StatusRegister may be modified. This bitgoes off when DMA mode is started bysetting the GO bit. When DMA mode isactive, setting this bit causes DMA tobe stopped. Clearing this bit has noeffect. This bit is set upon systemstartup or reset.
BIT 8 DBF The DATA BUFFER FLAG bit. This bitindicates that the Receive Data Buffercontains a word and is ready to beread. This bit is allowed to be ononly when the channel is in DMA mode(RDY - 0). DATA BUFFER FLAG iscleared when the Receive Data Bufferis read.
BIT 9 Z80 HALT The Z80-CPU HALT bit. This bitindicates the halt state of the XQ/CPmicroprocessor. If the XQ/CP ishalted, this bit will read as one.Otherwise, this bit will read as zero.This is a read-only bit and writing tothis bit has no effect.
BIT 10 ZSO This is Z80 STATUS BIT 0. This bitand the following Z80 Status Bits areuser defined status bits passed fromthe XO/CP program to the LSI-11program. These bits are read-only andwriting to these bits has no effect.
BIT 11 ZSl This is Z80 STATUS BIT 1. See ZSO.
BIT 12 ZS2 This is Z80 STATUS BIT 2. See ZSO.
BIT 13 ZS3 This is Z80 STATUS BIT 3. See ZSO.
I I 5-5
BIT 14 NXM The NONEXISTENT MEMORY ERRORbit. This bit being set indicatesthat DMA was attempted to an LSI-11address which did not respond. Thisbit is set by the MDMA and is testedand reset by the LSI-I program.
BIT 15 ERR The COMPOSITE ERROR bit. This bit isthe logical OR of all error bits.Currently the only defined error isNONEXISTENT MEMORY ERROR. The ERRORbit is reset by resetting all othererror bits. This bit is read-only.It is cleared upon system startup orreset. I
IIIiIiiII
II?NI
Table 5-2 XQ/CP: MDMA TCSR (Transmit Control and Status Register)
I 151 141 131 121 111 101 9 1 8 I 7 1 6 I 5 I 4 I 3 1 2 I 1 I 0 II II I I I I I I I I I I I I
IERRINXMIPS31PS21PSI1PSOI IDBFIRDYIIENIADRIADRIZ80XMTIXMTI GOII I I I I I I I I 1 1 171 161RESISIGIRESI I
A 7 I I I I I I I I I I I I ISR/WRWR/WR/WR/W R R R/WR/W R/W R/WR/W R W W
BIT 0 GO The GO bit. Setting this bit causesRDY to be reset to zero and initiatesa DMA transfer from the LSI-11processor to the XQ/CP. Clearing thisbit has no effect. GO will alwaysread as zero.
BIT 1 TRANS RESET The TRANSMIT RESET bit. Setting thisbit resets the transmit DMA hardware.The entire LSI-11 to XQ/CP channel isreset. This bit will always read aszero. Clearing this bit has noeffect.
BIT 2 TRANS SIGNAL The TRANSMIT SIGNAL bit. Setting thisbit interrupts the XQ/CP. This bitwill always read as zero. Clearingthis bit has no effect.
BIT 3 Z80 RESET The Z80 RESET bit. Setting this bitresets the Z80 hardware in the XQ/CPand causes the Z80 CPU to restart atlocation zero. Clearing this bit hasno effect. This bit will always readas zero.
BIT 4 ADR16 This is ADDRESS BIT 16 for extendedaddressing operation. It is clearedupon system startup or reset.
BIT 5 ADR17 This is ADDRESS BIT 17 for extendedaddressing operation. It is clearedupon system startup or reset.
BIT 6 IEN The INTERRUPT ENABLE bit. The LSI-11program sets this bit to allow thechannel to request program interruptsand clears it to disallow interrupts.The channel only responds to interruptpolling cycles when this bit is on.It is cleared upon system startup orreset.
BIT 7 RDY The READY bit. This bit has a valueof one when the channel is not in DMA
--
mode. When the channel is ready theMemory Address Register, the WordCounter Register, and the Control andStatus Register may be modified. This Ibit is cleared when DMA mode isstarted by setting the GO bit. WhenDMA mode is active, setting RDY causes IDMA to be stopped. Clearing this bithas no effect. It is set upon systemstartup or reset.
BIT 8 DBF The DATA BUFFER FLAG bit. This bitindicates that the Transmit DataBuffer is empty and is ready to accept Ia new word.
This bit has a value of one only when Ithe channel is in DMA mode (RDY = 0).DATA BUFFER FLAG is cleared when theTransmit Data Buffer is written.
BIT 9 UNUSED This bit is always read as a zero.
BIT 10 PSO This is PROCESSOR STATUS BIT 0. Thisbit and the following Processor Statusbits are user defined status bits thatare passed from the LSI-11 program tothe XQ/CP program. These bits may be Iset or cleared as required by theLSI-11 program. It is cleared uponsystem startup or reset. [
BIT 11 PSl This is PROCESSOR STATUS BIT 1. SeePSO.
BIT 12 PS2 This is PROCESSOR STATUS BIT 2. SeePSO.
BIT 13 PS2 This is PROCESSOR STATUS BIT 3. SeePS0. f
BIT 14 NXM The NONEXISTENT MEMORY ERROR bit.This bit has a value of one when DMAwas attempted to an LSI-11 addresswhich did not respond. This bit is Iset by the MDMA and is tested andcleared by the LSI-11 program.
BIT 15 ERR The COMPOSITE ERROR bit. This bit isthe logical OR of all error bits.Currently the only defined error isNONEXISTENT MEMORY ERROR. The ERRORbit is reset by resetting all othererror bits. This bit is read-only.It is cleared upon system startup or Ireset.
-II
Table 5-3 XQ/CP: Z80 RCR(Z80 Receiver Control Register)
7 16 15 14 3 2 1 0
IRDYIXMTIODDIDBFIPS3IPS21PSIIPSOII ISIGI I I I I I II - I -I -I ____ I -I I I I
R R R R R R R R
BIT 0 PSO This is PROCESSOR STATUS BIT 0. Thisbit and the following Processor StatusBits are user defined status bitspassed from the LSI-11 program to theXQ/CP program. They are read-only.
BIT 1 PSl This is PROCESSOR STATUS BIT 1. SeePSO.
BIT 2 PS2 This is PROCESSOR STATUS BIT 2. SeePSO.
BIT 3 PS3 This is PROCESSOR STATUS BIT 3. SeePSO.
BIT 4 DBF The DATA BUFFER FLAG bit. This bitbeing set inidicates that the MDMA'sTransmit Data Buffer is empty.
BIT 5 ODD The ODD BYTE bit. This bit being setindicates that an odd number of byteshave been transferred to the Z80Receive Data Buffer. Completedtransfers should always have an evennumber of bytes. This bit is read-only. It is cleared upon systemstartup or reset.
BIT 6 TRANS SIGNAL The MDMA TRANSMIT SIGNAL bit. Whenthe LSI-11 sets this bit channel 3 ofthe Z80-CTC is strobed. If the CTCchannel 3 has been programmed with acount of 1, this will cause aninterrupt of the Z80-CPU. This bitwill remain a one until after theZ80-RCR is read. This bit is read-only.
BIT 7 RDY The READY bit. This bit being seeindicates that the LSI-11 to XQ/CPchannel is ready for a DMA blocktransfer. This bit being clearedindicates that a DMA transfer is inprogress. This bit is read-only.
5
[J 5-,9
ITable 5-4 XQ/CP: Z80 TCR (Z80 Transmit Control Register)
S7 6 5 4 3 2 1 0I
IRDYIRECIODD ZS31ZS21ZS11ZS0
I ISIG I I I I I I II I I I I 1 7 1 1 I I
R W R R/W R/'W -R/W -R7'W IBIT 0 ZSO This is Z80 STATUS BIT 0. This bit
and the following Z80 Status bits areuser defined status bits passed from ithe XQ/CP program to the LSI-11program. These bits are read/write. I
BIT 1 ZSl This is Z80 STATUS BIT 1. See ZSO.
BIT 2 ZS2 This is Z80 STATUS BIT 2. See ZSO.
BIT 3 ZS3 This is Z80 STATUS BIT 3. See ZSO.
BIT 4 DBF The DATA BUFFER FLAG. This Ibit indicates that the Receive DataBuffer contains a word and is ready tobe read. DATA BUFFER STATUS iscleared when the Receive Data Bufferis read.
BIT 5 ODD The ODD BYTE Bit. This bit being set Iindicates that an odd number of byteshave been transferred to the MDMAReceive Data Buffer. Completed Itransfers should always have an evennumber of bytes. This bit is read-only. It is cleared upon systemstartup or reset.
BIT 6 REC SIGNAL The MDMA's RECEIVE SIGNAL bit.Setting this bit interrupts the LSI-11 Iprogram. Clearing this bit has noeffect. This bit is write-only andwill always be read as zero.
BIT 7 RDY The READY bit. This bit being setindicates that the XQ/CP to LSI-11channel is ready for a DMA block Itransfer. This bit being zeroedindicates that the channel is activein DMA mode. This bit is read-only. I
I5-10
.; __-io____
XQ/CP
MAINTENANCE MANUAL
CHAPTER 6-DETAILED DESCRIPTION
CHAPTER 6
6.0 DETAILED DESCRIPTION
6.1 Drawing References for Circuit Descriptions - This chapter
contains circuit descriptions of each XQ/CP board. Each
section in this chapter describes the circuits on a drawing by
drawing basis. Please refer to the drawings as the discussion
proceeds. Coordinate numbers on the drawings are used to help
locate signals or circuits. These are letter number pairs
(e.g. A8) that are marked on the edge of the drawing page.
Signal names indicate polarity: An active low signal is
followed by a minus, otherwise the signal is active high.
Active low signals are drawn with bubble outputs and inputs.
6.2 Processor Board - The logic drawings for the Processor
Board are Pages 1 through 3, Drawing 2600431.
6.2.1 Processor Board Drawing, Page 1 - Page 1 contains themajor Z80 components. The Z80-CPU, both Z80 DMA's, theZ80-SIO, the Z80-CTC, and the baud rate generator are all onthis page. These components connect to the Z80 Bus accordingto Zilog specifications. Consult Zilog technical manuals forcomponent operation and programming. In the XQ/CP, a Z80A-CPUis used. An external reset signal is synchronized to generatethe CPU's reset signal. This signal resets the program counterto zero so that orderly execution will begin after a reset.Each Z80-DMA can control one serial channel of the Z80-SIO.U17 monitors SIORDYA from S10 Channel A; U16 monitors SIORDYBfrom SIO Channel B. When programmed and enabled, the DMAcontrol of the SIO channels will allow higher speed serialtransfers than when the SIO is directly controlled by the CPU.The outputs of the SIO channels go to serial line driverslocated on page 3 for RS-449 and MIL-STD-188-114 and on page 1
6-1
for RS-232. The drivers for the unimplemented serialinterfaces are not mounted on the board. The Z80-CTC providescounter-timer functions. Channel 3 is intended to provide amechanism for external interrupts. CTC Channel 3 is loadedwith a count of 1. When TSIGNAL goes active, it clocks thechannel to zero. This creates an interrupt. A baud rategenerator, the K1135A, is programmable by the CPU for baudrates from 50 baud to 19.2 kilobaud. A component platform,U07, is provided to jumper either output of the baud rategenerator or modem supplied clocks to any of the serial clocks.This provides flexibility in choice of clocks. The lastelements on page 1 are the power converter and regulator for-5V and -12V.
6.2.2 Processor Board Drawing, Page 2 - Page 2 containsoff-board Z80 Bus connections, I/0 Port decoding, and the standalone clock. U24 and U34 are 74LS245 transceivers for the Z80Bus address bits. U33 is the transceiver for the data bits.U23 and U27 buffer control signals. U22 is a 74S471 ROMcontaining a table of ports. These are listed in Table 4-4.These outputs are used to enable various Z80 Bus I/O devices.One of these addresses is a DIP switch register for readinguser supplied data. The same I/O port address is used to writeto a register that drives eight LED's that are mounted on theedge of the P-Board. The final circuit on the page is a 4 mHzclock generator for stand alone operation. At coordinates D5,the jumper is shown that enables the clock selection. Theoutput of this jumper is the source for both the MOS clockdriver, PCLKM, and the TTL driver, PCLKT.
6.2.3 Processor Board Drawing, Page 3 - Page 3 contains thedrivers and receivers for the serial interface. The drawing isorganized top to bottom for Channel 0 to Channel 1 and left toright for receivers and drivers. This organization is clearlymarked on the drawing. The receivers are 3486 RS-422/RS-423Line Receivers. With external components these receivers canreceive RS-232 and MIL-STD-188-114. Component platforms havebeen provided to accomplish this. They are drawn in A5 throughA8. The drivers are 3691 RS-422/RS-423 Line Drivers.Component platforms have been provided to support the differentserial line specifications. When using this drawing it shouldbe observed that the signal names ending in H and L are derivedfrom the + and - inputs or outputs of the receiver and drivers;B and L do not correspond to the A and B sides of the EIAserial signals. Please consult the chart on page 3 of theP-Board drawing for this correspondence.
6
6-2 . .
-
6.3 Memory Board - The logic drawings for the Memory Board are
drawing 2600430, pages 1 and 2.
6.3.1 Memory Board Drawing, Page 1 - Page 1 contains the ROMcircuits. The ROM types may be either 2564 or 2532. The boardis populated with eight 28 pin sockets and will accept eithertype of ROM. If 2532 ROMs are used, pin 1 is plugged into pin3 of the socket. The address blocks that the ROMs respond toare determined by the chip enables, CSO- to CS7-, with CSO- asthe lowest address. This address decoding is done by U13 atA7. The other circuit elements on this page are Z80 Busaddress receivers that buffer address bits for the M-Board.
6.3.2 Memory Board Drawing, Page 2 - Page 2 of 2600430contains 32K bytes of RAM. The memory circuits are 4116Dynamic RAMs. Refresh is provided by the Z80-CPU. Controlcircuitry to generate the proper row (RAS-) and column (CASO-and CASI-) strobe timing is shown on this page. This timing isaccomplished by multiplexing the Z80 Bus address signals in U40and U41 (C8). During a memory cycle, the Z80 devicecontrolling the bus will assert BZMREQ- which will set ADRSEL(see Figure 6-1). This selects BZADR07-13 as the columnaddress bits. This selection occurs after the row address bitshave been asserted for approximately ilOns. RAS- is assertedstarting with MREQ and ending when PCQ2 is asserted. Refer toFigure 6-1 for the timing of PCQI and PCQ2. The column addressstrobes become active after the delays provided by the 74LS04sgenerating MAS2 at C6. Figure 6-1 shows the timing for a CPUMl cycle, an instruction fetch. The circuit at B2-B3 generatesa wait cycle during an instruction fetch. The types of RAMsand ROMs currently available require the generation of thiswait cycle. A jumper disable of this circuit (ROME to GND orRAME to GND at B3) has been provided if faster memory circuitsbecome available. Figure 6-1 shows the generation of this waitcycle.
6
I
T1 T2 TW TT
MCLKT
BZMREQ
MI-
ADRSEL 4A ELI I IBZRFSH I
PCQl______2 ,
CAS 1-
DATA DATA VALID
WAITEN
MEMWAIT -WAITRES-
FIGURE 6-1 RAM ACCESS TIMING DIAGRAMi
6-4
L --
6.4 Interface Board - The I-Board drawings are on 2600429
pages 1-5.
6.4.1 Interface Board, Page 1 - Page 1 contains the Z80receive DMA circuits. The main elements on this page are theZ80-DMA, a buffer for the control register bits (U23 at B5),the data registers that receive 16 bit LSI-Bus data and put 8bit data on the Z80 Bus, and control circuits. The key tounderstanding the receive circuits is in the control circuits.When a word is available to the 16 bit data register, TDBCK- isgenerated. This clocks the data into U02 and U03 and alsoclocks both J-K flip-flops of U39. This sets TDBL and TDBU(see Figure 6-2 on next page). With these signals activeDMARRDY will be set on the next active edge of ICLKT-. SinceTDBLOE- was active for the clock prior to the setting ofDMARRDY, the eight least significant bits of data will beclocked into U01. Additionally, TDBL is reset causing TDBLOE-to go inactive and TDBU to go active. The Z80 DMA will respondto DMARRDY if it has been properly programmed and enabled. Itwill request a Z80 Bus transfer. When granted the bus, the DMAwill read the 8 bit register, causing ZDBOE- to go active (D4).This will toggle DMARRDY on the next clock. Since a byte isstill in the register, TDBU is still active. This will causeDMARRDY to go active on the following clock which strobes theupper byte into the 8 bit register and re-enables the Z80 DMA.The DMA will go through another bus acquisition and datatransfer cycle completing the 16 bit transfer. The finalcircuit on this page is to generate ZRCYL, a single clockversion of ZDBOE. This is done with a D flip-flop, U34 at C7.The Q output is brought to an AND gate with the inverted Dinput to create ZRCYL (see Figure 6-3 on next page). Thisscheme is also used to generate ZTCYL on page 3-C6, RSIGSET onpage 3-D5, and CLRTSIG on page 5-Cl.
III
-1
ICIJKT- T J L ~ J L T
TDECK F 1
TDBL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
TDBU - ._ - .. __ _
imARDYJ
TDBLOE-
ZDBOE-
FIGURE 6-2 LSI-BUS TO Z80-BUS DMA TRANSFERTIMING DIAGRAM
T1 T 2 T w T 3
ICLKT
BZIORQ-
ZDBOE
ZDBOES j
ZRCYLj
FIGURE 6-3 SINGLE CLOCK VERSION OFI/o REQUEST
6-6 "
6.4.2 Interface Board, Page 2 Page 2 of Drawing 2600429contains the si registers. The registers are implementedusing 4x4 Register Files, 74LS670. The clocks, output control,and address bits are generated on page 4 from the SIB controlsignals, and will be discussed below. The other two elementson this page are two 8304B Transceivers which buffer the SIBdata bits from an internal three state bus, DXOO to DXl5. Notethat the SIB bits begin with X; the glossary refers to theSubsystem Interface Bus as the X-Bus. This bus is used by thecommunications registers shown on page 2 and by the data andcontrol registers shown on other pages. Interface Board, Page3 - Page 3 shows the Z80 transmit DMA circuits. A transfersequence would begin by programming the DNA, U53, and enablingit. If the GO bit has been set DMATRDY (at C5) will be activeand the Z80 DMA will request a bus acquisition. When the bushas been granted, it will write a byte into the 8 bit register,U04 at B4. The first clock after the data has been latchedwill cause ZTPULL to go active and turn off DMATRDY (refer toFigure 6.4 on next page). RLFULL will be set on the next clockcausing the data to be latched in the lower 8 bits of the 16bit data register, U05. ZTFULL also changes on this clocksince ZTFULL had been active and RDBF-(D2) is still high. Thisresults in DMATRDY going ready so that another byte is obtainedby the Z80 DMA. This byte will set RUFULL, clocking the datainto the upper 8 bits of the register, U06. When the word isread from the 16 bit register, RDBE- is strobed which willreset the remaining signals that are active. The Z80 DMA willbe free to transfer another byte into U04 as soon as ZTFULLgoes to zero. This may be before the 16 bit transfer isaccomplished and thus block transfers are efficientlypipelined. The remaining circuits on this page include thecontrol register U14 at C4 and its buffer U15, an I/O portdecoder ROM (U54 at B7) and an interrupt mechanism. Aninterrupt to the LSI-11 QBUS is conveyed by the MDMA whenRSIGNAL is set (D4). The control of this signal is critical inorder to prevent a loss of RSIGNAL while the control registeris being read. The timing of all possible cases is given inFigure 6-5 on page 6-9.
6
I
I
6-7 :-
ICILKT-
DMATRDY
ZTCYL
RUFULL -- --
RDBF___________ _
RDBE-
FIGURE 6-4 Z80-BUS TO LSI-BUS DMA TRANSFERTIMING DIAGRAM
6-8
1 1 T 2 TW T 3
ICLKT-
IORQ-
RSIGSET
CASE 1: RCS IS READ PRIOR TO RSIGSET. READ AS 0 THIS READ, 1 NEXT READ.
RCSE-
RSETSIG __ _ _-
I RSIGNAL-- - tCASE 2: RCS IS READ DUPING RSI SET. AS 0 THIS READ, 1 NEST READ.
RCSE-
RSETSIG
RS-IGNAL
CASE 3: RCS IS READ 1 CLK (OR MORE) AFTER RSIGSET, READ AS 1 THIS READ.
RCSE- -
RSETSIG-
RSIGNAL
IFIGURE 6-5 RSIGNAL TIMING DIAGRAM
I
II-
6.4.3 Interface Board, Page 4 - Page 4 of the I-Boarddrawings contains circuits that are used to interface to theSIB. At C8 there is a DIP switch that selects address bits fora 25LS2521 comparator. If the SIB address bits are the same,SEL- goes active. This signal is used as an enable on U51,U19, and U21 (D5 through B5). These decoders generate vectorenables, communication register output enables and strobes.The last decoder, U57, decodes function bits to determine whatkind of operation to perform. The two J-K flip flops in B7 andA7 generate interrupts to the LSI-11 through the SIB. RIRDY-and TIRDY- cause XBRDY-. XBRDY- is the MDMA's pollingcondition that will cause it to generate an interrupt to theLSI-ll. TIRDY- is generated when bit 7 of the control registeris set (READY) after the transmit GO bit is on. This isnormally done at the end of a data block transfer, but may alsobe done under LSI-II program control. RIRDY- is generatedunder similar circumstances and can also be generated bysetting RSIGSET, the Z80 to LSI-11 signal term. The remainingcircuit elements on this page are the buffering of the SIBclock signal, DCKB-, and the generation of the different resetsignals.
6.4.4 Interface Board, Page 5 - Page 5 contains the SIBcontrol and status registers. The bits are latched in 74LS174registers and driven onto the three state DX data lines by74LS244 buffers. Clocking and output controls are from thedecoders on page 4. The control signal that generates a Z80interrupt is TSIGNAL. The timing problems are similar to thosefor RSIGNAL; all cases of a TSIGNAL interrupt are shown inFigure 6-6. Please note that both RSIGNAL and TSIGNAL remainactive until the side that has been interrupted reads thecontrol register. The control register read resets the bit tozero.
I
4.6-10
! - T
I
ICLK'T- Z _ E NL~
CLRTSIG
RDZRCR
CASE 1: Z80 READS BIT AFTZR IT WA SET. R AS 1 THIS READ.
SETTfSIG ____________
TSETA
TSIGALI
CASE 2: Z80 READING BIT AS IT IS ET. READ AS 0 THIS 4 ,1 NEXT READ.
TSIGNAL.. . ,
SETTSIG ! ,D
TSETA i
TSIGNAL
I 6I
STSIGNAL - I - i-I
I FIGURE 6-6 TSIGNAL TIMING DIAGRAM
Ji 6-12.
[.
XQ/CP
MAINTENANCE MANUAL
CHAPTER 7 - GLOSSARY
IiI
Ii
I (-
CHAPTER 7
7.0 GLOSSARY
4MCLK 4 Megahertz Clock8MCLK 8 Megahertz ClockAO RAM Address Bit 0 (Attenuated)AOD RAM Address Bit 0 (Unattenuated)Al RAM Address Bit 1 (Attenuated)AID RAM Address Bit 1 (Unattenuated)A2 RAM Address Bit 2 (Attenuated)AID RAM Address Bit 2 (Unattenuated)A3 RAM Address Bit 3 (Attenuated)A3D RAM Address Bit 3 (Unattenuated)A4 RAM Address Bit 4 (Attenuated)A4D RAM Address Bit 4 (Unattenuated)A5 RAM Address Bit 5 (Attenuated)A5D RAM Address Bit 5 (Unattenuated)A6 RAM Address Bit 6 (Attenuated)A6D RAM Address Bit 6 (Unattenuated)ABI MSIB Address Bit 1AB2 MSIB Address Bit 2AB3 MSIB Address Bit 3ADRSEL MDMA Address SelectAJ4 Address Jumper Bit 4AJ5 Address Jumber Bit 5AJ6 Address Jumper Bit 6AJ7 Address Jumber Bit 7ALl2 Address Latch Bit 12ALl3 Address Latch Bit 13ALl4 Address Latch Bit 14ALl5 Address Latch Bit 15BA0- Bus Acknowledge 0BAl- Bus Acknowledge 1BA2- Bus Acknowledge 2BAO- Bus Acknowledge OutBCKB- MSIB ClockBDMG- LSI-11 Bus DMA GrantBIAK- LSI-11 Bus Interrupt AcknowledgeBINTACK- Z80 Bus Interrupt AcknowledgeBLOCK- Block TSIGNAL from settingBRGEN Baud Rate Generator EnableBZADR00 Suffered Z80 Address Bit 00BZADROO Buffered Z80 Address Bit 01BZADR02 Buffered Z80 Address Bit 02BZADR03 Buffered Z80 Address Bit 03BZADR04 Buffered Z80 Address Bit 04BZADRO5 Buffered Z80 Address Bit 05BZADR06 Buffered ZOO Address Bit 06BZADR07 Buffered Z80 Address Bit 07
I 7-1
BZADR08 Buffered Z80 Address Bit 08BZADR09 Buffered Z80 Address Bit 09BZADRIO Buffered Z80 Address Bit 10BZADRll Buffered Z80 Address Bit 11BZADR12 Buffered Z80 Address Bit 12BZADR13 Buffered Z80 Address Bit 13BZADR14 Buffered Z80 Address Bit 14BZADR15 Buffered Z80 Address Bit 15BZBUSRQ- Buffered Z80 Bus RequestBZCLK Buffered Z80 ClockBZDATO Buffered Z80 Bus Data Bit 0BZDATI Buffered Z80 Bus Data Bit 1BZDAT2 Buffered Z80 Bus Data Bit 2BZDAT3 Buffered Z80 Bus Data Bit 3BZDAT4 Buffered Z80 Bus Data Bit 4BZDAT5 Buffered Z80 Bus Data Bit 5BZDAT6 Buffered Z80 Bus Data Bit 6BZDAT7 Buffered Z80 Bus Data Bit 7BZEN- Buffered Z80 Bus EnableBZENl- Buffered Z80 Bus Enable 1BZEN2- Buffered Z80 Bus Enable 2BZEN3- Buffered Z80 Bus Enable 3BZHALT Buffered Z80 Bus Halt BitBZIN- Buffered Z80 Bus Input EnableBZINT- Buffered Z80 Bus InterruptBZIORQ- Buffered Z80 Bus Input/Output RequestBZM1 Buffered Z80 Bus Machine Cycle 1BZMREQ- Buffered Z80 Bus Memory RequestBZRD- Buffered Z80 Bus Read CycleBZRFSH- Buffered Z80 Bus Refresh CycleBZWR- Buffered Z80 Bus Write CycleCASO- Column Address Strobe 0 (Attenuated)CASI- Column Address Strobe 1 (Attenuated)CASDO- Column Address Strobe 0 (Unattenuated)CASDI- Column Address Strobe 0 (Unattenuated)CLKD D-Input to Clock Flip-flopCLRTSIG Clear Transmit SignalCS0- ROM Chip Select 0CSl- ROM Chip Select 1CS2- ROM Chip Select 2CS3- ROM Chip Select 3CS4- ROM Chip Select 4CS5- ROM Chip Select 5CS6- ROM Chip Select 6CS7- ROM Chip Select 7CTCEN- CTC Chip EnableCTSO- Clear to Send Channel 0, Active LowCTSOH Clear to Send Channel 0, + Term to ReceiveCTSOHI Clear to Send Channel 0, + Term on Input ConnectorCTSOL Clear to Send Channel 0, - Term to ReceiverCTSOLI Clear to Send Channel 0, - Term on Input ConnectorCTSl- Clear to Send Channel 1, Active LowCTS1H Clear to Send Channel 1, - Term to ReceiverCTSlHI Clear to Send Channel 1, - Term on Input ConnectorCTS1L Clear to Send Channel 1, - Term to ReceiverCTSlLI Clear to Send Channel 1, - Term on Input Connector
7-2
DCDO Data Carrier Detect Channel 0DCDOH Data Carrier Detect Channel 0, + Term to ReceiverDCDOHI Data Carrier Detect Channel 0, + Term on Input ConnectorDCDOL Data Carrier Detect Channel 0, - Term to ReceiverDCDl- Data Carrier Detect Channel 1, Active LowDCDIH Data Carrier Detect Channel 1, + Term to ReceiverDCDlHI Data Carrier Detect Channel 1, + Term on Input ConnectorDCDIL Data Carrier Detect Channel 1, - Term to ReceiverDCDlLI Data Carrier Detect Channel 1, - Term on Input ConnectorDIO RAM Data In Bit 0DIlI RAM Data In Bit 1D12 RAM Data In Bit 2D13 RAM Data In Bit 3D14 RAM Data In Bit 4DI5 RAM Data In Bit 5DI6 RAM Data In Bit 6DI7 RAM Data In Bit 7DMAREN- DMA Receive Channel Chip EnableDMARRDY DMA Receive Channel ReadyDMARRDY- DMA Receive Channel Ready, Active LowDMASAEN- DMA for SIO Channel A, Chip EnableDMASBEN- DMA for SIO Channel B, Chip EnableDMATEN- DMA Transmit Channel EnableDMATRDY DMA Transmit Channel ReadyDOG RAM Data Out Bit 0DOi RAM Data Out Bit 1D02 RAM Data Out Bit 2DO3 RAM Data Out Bit 3D04 RAM Data Out Bit 4DO5 RAM Data Out Bit 5D06 RAM Data Out Bit 6D07 RAM Data Out Bit 7DSROH Data Set Ready Channel 0, + Term from DriverDSROHI Data Set Ready Channel 0, + Term on Output ConnectorDSROL Data Set Ready Channel 0, - Term from DriverDSROHI Data Set Ready Channel 0, - Term on Output ConnectorDSR1H Data Set Ready Channel 1, + Term from DriverDSRlBI Data Set Ready Channel 1, + Term on Output ConnectorDSR1L Data Set Ready Channel 1, - Term from DriverDSRILI Data Set Ready Channel 1, - Term on Output ConnectorDTROH Data Terminal Ready Channel 0, + Term from DriverDTROHO Data Terminal Ready Channel 0, + Term on Output ConnectorDTROL Data Terminal Ready Channel 0, - Term from DriverDTROLO Data Terminal Ready Channel 0, - Term on Output ConnectorDTRI- Date Terminal Ready Channel 1, Active LowDTRIH Data Terminal Ready Channel 1, + Term from DriverDTRIHO Data Terminal Ready Channel 1, + Term on Output ConnectorDTRIL Data Terminal Ready Channel 1, - Term from DriverDTRILO Data Terminal Ready Channel 1, - Term on Output ConnectorDXO0 DX Bus Bit 00DX01 DX Bus Bit 01DX02 DX Bus Bit 02DX03 DX Bus Bit 03DX04 DX Bus Bit 04DX05 DX Bus Bit 05DX06 DX Bus Bit 06
7-3
DX07 DX Bus Bit 07DX08 DX Bus Bit 08DX09 DX Bus Bit 09DX10 DX Bus Bit 10DXll DX Bus Bit 11DX12 DX Bus Bit 12DX13 DX Bus Bit 13DX14 DX Bus Bit 14DXl5 DX Bus Bit 15FNBO Function Bit 0FNBl Function Bit 1FNB2 Function Bit 3ICLKM I-Board Clock - MOSICLKT I-Board Clock - TTLICLKT- I-Board Clock - TTL, Active LowID01 Identification Bit 1ID02 Identification Bit 2ID03 Identification Bit 3IE Interrupt EnableIEO Interrupt Enable Priority 0IEI Interrupt Enable Priority 1IE2 Interrupt Enable Priority 2IE3 Interrupt Enable Priority 3IE4I Interrupt Enable Level 4 InputIE40 Interrupt Enable Level 4 OutputIEO Interrupt Enable OutINTACK Interrupt AcknowledgeLEDO Light Emitting Diode 0LED1 Light Emitting Diode 1LED2 Light Emitting Diode 2LED3 Light Emitting Diode 3LED4 Light Emitting Diode 4LED5 Light Emitting Diode 5LED6 Light Emitting Diode 6LED7 Light Emitting Diode 7LEDEN- LED EnableLEDSWEN- LED/DIP Switch I/O Port AddressMASO Memory Address Select Phase 0MASI Memory Address Select Phase 1MAS2 Memory Address Select Phase 2MCLKT M-Board Clock, TTLMDBC Mode Bit CMDBD Mode Bit DMDCA Mode Control AMDCB Mode Control BMENWAIT Memory Wait StateMREQ Memory RequestPCLKM P-Board Clock (MOS)PCLKT P-Board Clock (TTL)PCQI Pre Charge Extender Q-Output 1PCQ2- Pre Charge Extender Q-Output 2PS0 Processor Status Bit 0Psi Processor Status Bit 1PS2 Processor Status Bit 2PS3 Processor Status Bit 3 !RADROO RON Address Bit 00
7-4
RADR01 RON Address Bit 01RADR02 RON Address Bit 02RADR02 RON Address Bit 02RADR03 RON Address Bit 03RADR04 RON Address Bit 04RADR05 ROM Address Bit 05RADR06 ROM Address Bit 06RADR07 ROM Address Bit 07RADR08 ROM Address Bit 08RADR09 ROM Address Bit 09RADR10 ROM Address Bit 10RADRil ROM Address Bit 11RADR12 ROM Address Bit 12RADR13 ROM Address Bit 13RADR14 ROM Address Bit 14RAME RAM Wait EnableRAMEN RAM Wait EnableRAMOEN- RAM Output EnableRAS- Row Address Select (Attenuated)RASD- Row Address Select (Unattenuated)RCO- Serial Receive Clock Channel 0RC1- Serial Receive Clock Channel 1RACACK- Receive Address ClockRCAE- Receive Address Output EnableRCASO RAM Column Address Select 0RCAS1 RAM Column Address Select 1RCSCK Receive Control and Status Register ClockRCSE Receive Control and Status Register Output EnableRCSR03 Receive Control/Status Register Bit 03RD Read Transmit Data BufferRDO Receive Data Channel 0RDI Receive Data Channel 1RDATO ROM Data Bit 0RDATI ROM Data Bit 1RDAT2 ROM Data Bit 2RDAT3 ROM Data Bit 3RDAT4 ROM Data Bit 4RDAT5 ROM Data Bit 5RDAT6 ROM Data Bit 6RDAT7 ROM Data Bit 7RDBE Receive Data Buffer Output EanbleRDBG Receive Data Buffer FlagRDBFA Read Data Buffer Pull, Term ARDQ- Read RequestRDREG- Read 4 X 4 Register FileRDZRCR Read Z80 Receive Control RegisterREADFN- MDMA Read FunctionREM16 Receive Extended Memory Address Bit 16REM17 Receive Extended Memory Address Bit 17RESETA- Reset Term ARESETB- Reset Term BRESETC- Reset Term CRGO Receive Go BitRIEN Receive Interrupt EnableRIRDY- Receive Interrupt ReadyRIRDYG- Receive Interrupt Ready Enabled
7-5
RLFULL Receive Low Byte FullRLFULLJ Receive Low Byte Full, J InputRMERR Receive Memory ErrorRGOH Ring Indicator Channel 0, + Term to Receiver
RNGOHI Ring Indicator Channel 0, + Term on Input ConnectorRNGOL Ring Indicator Channel 0, - Term to ReceiverRNGIH Ring Indicator Channel 1, + Term on Input ConnectorRNGlHI Ring Indicator Channel 1, + Term to ReceiverRNGlL Ring Indicator Channel 1, - Term on Input ConnectorROM- RON Address DecodeROME ROM Wait EnableROMEN RON Wait EnableROMP23 ROM Pin 23RRESET- Receive Channel ResetRSETSIG Receive Set SignalRSIGEN Recieve Signal EnableRSIGENS Receive Signal Enable SynchronizedRSIGJ Receive Signal, J InputRSIGNAL Receive SignalRSIGSET Receive Signal SetRSTOP Receive Channel StopRSTP Receive StopRSVC- Recieve Vector DecodeRTCA Rise Time Control ARTCB Rise Time Control BRTCC Rise Time Control CRTCD Rise Time Control DRTCE Rise Time Control ERTCF Rise Time Control FRTCG Rise Time Control GRTCH Rise Time Control HRTCI Rise Time Control IRTCJ Rise Time Control JRTCK Rise Time Control KRTCL Rise Time Control LRTCM Rise Time Control MRTCN Rise Time Control NRTCO Rise Time Control 0RTCP Rise Time Control PRUFULL Receive Upper Byte FullRVSEL Receive Vector SelectRWCCK- Receive Word Count Register ClockRWCE- Receive Word Count Register Output EnableRX- Baud Rate Generator, Receive ClockRXCO- Receive Clock Channel 0RXCOH Receive Clock Channel 0, + Term to RecieverRXCOBI Receive Clock Channel 0, + Term on Input ConnectorRXCOL Receive Clock Channel 0, - Term to ReceiverRXCOLI Receive Clock Channel 0, - Term on Input ConnectorRXCl- Receive Clock Channel 1RXCIH Receive Clock Channel 1, + Term to ReceiverRXC8II Receive Clock Channel 1, + Term on Input ConnectorRXClL Receive Clock Channel 1, - Term to ReceiverRXC1LI Receive Clock Channel 1, - Term on Input ConnectorRXDOB Receive Data Channel 0, + Term to ReceiverRXDOHI Receive Data Channel 0, + Term on Input Connector
7-6
RXDOL Receive Data Channel 0, - Term to ReceiverRXDOLI Receive Data Channel 0, - Term on Input ConnectorRXD1H Receive Data Channel 1, + Term to ReceiverRXDIHI Receive Data Channel 1, + Term on Input ConnectorRXD1L Receive Data Channel 1, - Term to ReceiverRXDILI Receive Data Channel 1, - Term on Input ConnectorSEL MDMA Device SelectSERIALEN- Serial Port EnableSERRD Serial Port ReadSIOEN- SIO Chip EnableSIORDYA SIO Ready Channel ASIORDYB SIO Ready Channel BSVCR- Send ID VectorSWO- Switch Bit 0SW1- Switch Bit 1SW2- Switch Bit 2SW3- Switch Bit 3SW4- Switch Bit 4SWS- Switch Bit 5SW5- Switch Bit 5SW6- Switch Bit 6SW7- Switch Bit 7
SWEN- DIP Switch EnableTCACK- Transmit Address ClockTCAE- Transmit Address Output EnableTCMOH Transmit. Clock from Modem Channel 0, + Term to ReceiverTCMOHI Transmit Clock from Modem Channel 0,
+ Term on Input ConnectorTCMOL Transmit Clock from Modem Channel 0, - Term to RecieverTCMOLI Transmit Clock from Modem Channel 0,
- Term on Input ConnectorTCM1H Transmit Clock from Modem Channel 1, + Term to ReceiverTCMIHL Transmit Clock fror Modem Channel 1,
+ Term on Input ConnectorTCMIL Transmit Clock from Modem Channel 1, - Term to RecieverTCMILI Transmit Clock from Modem Channel 1,
- Term on Input ConnectorTCSCK Transmit Control and Status Register ClockTCSE- Transmit Control and Status Register Output EnableTSCR09 Transmit Control and Status Register Bit 09TCTOH Transmit Clock from Terminal Channel 0, + Term from DriverTCTOHO Transmit Clock from Terminal Channel 0,
+ Term on Output ConnectorTCTOL Transmit Clock from Terminal Channel 0, - Term from DriverTCTOLO Transmit Clock from Terminal Channel 0,
- Term on Output ConnectorTCT1H Transmit Clock from Terminal Channel 1, + Term from DriverTCTIHO Transmit Clock from Terminal Channel 1,
+ Term on Output ConnectorTCT1L Transmit Clock from Terminal Channel 1, - Term from DriverTCTILO Transmit Clock from Terminal Channel 1,
- Term on Output ConnectorTDO Transmit Data Channel 0TD1 Transmit Data Channel 1TDATO Transmit Data Buffer Bit 0TDATI Transmit Data Buffer Bit 1
H 7-7
TDAT2 Transmit Data Buffer Bit 2TDAT3 Transmit Data Buffer Bit 3TDAT4 Transmit Data Buffer Bit 4TDAT5 Transmit Data Buffer Bit 5TDAT6 Transmit Data Buffer Bit 6TDAT7 Transmit Data Buffer Bit 7TDBCK Transmit Data Buffer ClockTDBFULL Transmit Data Buffer FullTDBL Transmit Data Buffer Low ByteTDBLOE Transmit Data Buffer Low Byte Output EnableTDBU Transmit Data Buffer Upper ByteTDBUOE Transmit Data Buffer Upper Byte Output EnableTEM16 Transmit Extended Memroy Address Bit 16TEM17 Transmit Extended Memroy Address Bit 17TGO Transmit Channel Go BitTIEN Transmit Interrupt EnableTIRDY- Transmit Interrupt ReadyTIRDYG- Transmit Interrupt Ready EnableTM0- Transmit Clock from Modem Channel 0TMl- Transmit Clock from Modem Channel 1TMERR Transmit Memory ErrorTODD Transmit Odd Number of BytesTRESET- Transmit Channel ResetTSETA Transmit Signal Set Term ATSIGJ Transmit Signal J TermTSIGNAL Transmit SignalTSTOP Transmit DMA StopTSVC- Transmit Send VectorTTO- Terminal Timing Channel 0TTl- Terminal Timing Channel 1TVSEL Transmit Vector SelectTWCCK- Transmit Word Count Register ClockTWCE- Transmit Word Count Register Output EnableTX- Baud Rate Generator, Transmit ClockTXCO- Transmit clock Channel 0TXCl- Transmit Clock Channel 1TXDOH Transmit Data Channel 0, + Term from DriverTXDOBO Transmit Data Channel 0,TXDOL Transmit Data Channel 0,TXDOLO Transmit Data Channel 0,TXD1B Transmit Data Channel 1,TXDlHO Transmit Data Channel 1,TXDlL Transmit Data Channel 1,TXD1LO Transmit Data Channel 0,VCT03 Interrupt Vector Bit 3VCT04 Interrupt Vector Bit 4VCT05 Interrupt Vector Bit 5VCT06 Interrupt Vector Bit 6VCT07 Interrupt Vector Bit 7VECTFN- MDMA Vector FunctionVECTR- Vector IVM Voltage Pullup on N-BoardVP Voltage Pullup on P-Boardw- WriteWAITEN Memory M1 Cycle Wait EnableWAITRES- Wait Reset
7-8I
WRREG- Write into 4 X 4 Register FilesWRT- WriteWRTFN- MDMA Write FunctionI XBADOO X-Bus Address Bit 00XBAD01 X-Bus Address Bit 01XBAD02 X-Bus Address Bit 02XBAD03 X-Bus Address Bit 03XBAD04 X-Bus Address Bit 04XBADO5 X-Bus Address Bit 05XBAD06 X-Bus Address Bit 06XBAD07 X-Bus Address Bit 07XBCLK X-Bus Clock (Active Falling Edge)XBCNTO X-Bus Control Bit 0XBCNT1 X-Bus Control Bit 1XBCNT2 X-Bus Control Bit 2XBDAOO X-Bus Data Bit 00XBDA01 X-Bus Data Bit 01XBDA02 X-Bus Data Bit 02XBDA03 X-Bus Data Bit 03XBDA04 X-Bus Data Bit 04XBDA05 X-Bus Data Bit 05XBDA06 X-Bus Data Bit 06XBDA07 X-Bus Data Bit 07XBDA08 X-Bus Data Bit 08XBDA09 X-Bus Data Bit 09XBDAIO X-Bus Data Bit 10XBDAI2 X-Bus Data Bit 11XBDA12 X-Bus Data Bit 12XBDA13 X-Bus Data Bit 13XBDA14 X-Bus Data Bit 14XBDA15 X-Bus Data Bit 15XBEOT X-Bus End of TransferXBRDY- X-Bus Ready BitXBRST X-Bus ResetZADROO ZSO Address Bit 00ZADRO Z80 Address Bit 01ZADR02 Z80 Address Bit 02ZADR03 Z80 Address Bit 03ZADR04 Z?0 Address Bit 04ZADR05 Z80 Address Bit 05ZADR06 Z80 Address Bit 06ZADR07 Z80 Address Bit 07ZADR08 Z80 Address Bit 08ZADR09 ZSO Address Bit 09ZADR10 Z80 Address Bit 10ZADR1l Z80 Address Bit 11ZADR12 Z80 Address Bit 12ZADR13 Z80 Address Bit 13ZADR14 Z80 Address Bit 14ZADRI5 ZO Address Bit 15ZBUSRZ- Z80 Bus RequestZDATO z80 Data Bit 0ZDAT1 Z80 Data Bit 1ZDAT2 Z80 Data Bit 2ZDAT3 Z0 Data Bit 3ZDAT4 Z0 Data Bit 4
.' ' 7.9
ZDAT5 Z80 Data Bit 5ZDAT6 Z80 Data Bit 6ZDAT7 Z80 Data Bit 7ZDBOE Z80 Data Buffer Output EnableZDBOES Z80 Data Buffer Output Enable SynchronizeZHALT- Z80 Halt StateZINT- Z80 Interrupt RequestZIORQ- Z80 Input/Output RequestZMI Z80 Machine Cycle OneZMREQ- Z80 Memory RequestZRCREN- Z80 Receiver Control Register EnableZRCROE- ZS0 Receive Control Register Output EnableZRCYL Z80 Receive CycleZRD- Z80 Memory ReadZRDATEN- Z80 Receive Data Register EanbleZRES- Z80 ResetZRES1 Z80 Reset Term 1ZRESQ- Z80 Reset Q OutputZRFSH Z80 RefreshZS0 Z80 Status Bit 0ZSl Z80 Status Bit 1ZS2 Z80 Status Bit 2ZS3 Z80 Status Bit 3ZTCRCLK Z80 Transmit Control Register ClockZTCREN Z80 Transmit Control Register EnableZTCROE- Z80 Transmit Control Register Output EnableZTCYL Z80 Transmit CycleZTDATEN- Z80 Transmit Data Register EnableZTDATWR Z80 Transmit Data Register WriteZTDATWRS Z80 Transmit Data Register Write SynchronizedZTFULL Z80 Transmit Data Buffer FullZTFULLK Z80 Transmit Data Buffer Full K InputZWAIT- Z80 WaitZWR Z80 Memory Write
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