OTP & MTP/FRP Non -Volatile Memory IP for Standard Logic CMOS · Our OTP Cell Tr. SONOS NVM Cell...

Copyrights © 2004-2018 NSCore, Inc., All Rights Reserved.

Jan. 2018

OTP & MTP/FRP Non-Volatile Memory IP for Standard Logic

CMOS

NSCore, Inc. http://www.nscore.com/


Jan. 2018 Outlines

1. Corporate Overview

2. Program, Read & Erase Mechanism

3. OTP IP Lineups

4. New MTP Technologies


Jan. 2018

Corporate Overview


Jan. 2018

Head Quarter: Fukuoka, Japan Sales Office: Kanagawa, Japan California, U.S.A. Texas, U.S.A. Paris, France Herzliya, Israel Hsinchu, Taiwan Seoul, Korea

Company Profile

Company Name Head Quarter

Foundation Management Team

Advisory

Financing

NSCore, Inc. Fukuoka, Japan 2004 CEO: T. Horiuchi CTO: K. Noda Prof. Chenming Hu (UC Berkeley) USD6.8M from VC USD5.2M from Gov’t


Jan. 2018 Embedded Logic NVM Technology

Benefits to LSI Design: Reduced Cost Reliability Improved Security Level

on CMOS Process Platforms

•Program Code •Security Code •Analog Trimming •SRAM Repair •Gamma Correction

Non-Volatile Memory IP

Applications


Track Record of License Jan. 2018

Over 1.5 billion units of licensed products have been shipped.

“NSCore” inside major smart phone

Gamma table for LCD display Power IC for mobile phone Sensor IC for mobile phone

Firmware storage of WiFi chip Product TAG


NSCore Technology Position Jan. 2018

Write/Erase Cycle

Mem

ory

Cap

acity

1 time OTP

1K-10K times MTP

Kilopass Sidense

NSCore OTP “PermSRAM”

eMemory

100bit-10Kbit

100Kbit-10Mbit

Synopsys

NSCore MTP/FRP

“TwinBitTM”

OTP MTP FRP (Flash Replacement Programmable)


Program, Read and Erase Mechanism

Jan. 2018


Programming Mechanism Jan. 2018

Drain Source Electrons

Hot electron

Ec

Electrons

Impact Ionization

Si3N4

SiO2

Common sidewall spacer structure

When nMOSFET turns ON, hot-electrons are generated and trapped in side-wall spacer.

LDD implant is masked to accelerate impact ionization.

5-7V

5-7V


In Read Operation Jan. 2018

Source Drain

Trapped electron

Ec

Trapped electron bends the conduction band to form a barrier. Channel current is reduced.

Conduction band without electron trapping

Electrons

“Source” and “Drain” are reversed from Program Operation

0.5-1V

1.8-3.3V


Erase Mechanism for TwinBit/PolarBit (MTP) Jan. 2018

Drain Source

Hot-Hole Injection and Recombination

0V 5-7V

- 5-7V

When Gate is negatively biased, hot-holes are injected into the spacer and recombine with the trapped electrons.

Band-to-Band tunneling current generates hot-carriers.


-

Gate

Source Drain

-

Our OTP Cell Tr. SONOS NVM Cell Tr.

Gate

Source Drain

Si3N4

SiO2

Similarity with SONOS Memory Jan. 2018

Program mechanism in Our OTP is similar to SONOS memory, which has strong track record as embedded Flash memories. Both memories uses electron trapping in Si3N4 layer. Our OTP does not need any extra process, while SONOS requires special gate structure.


NSCore utilizes “Charge-Trap” in Si3N4 Film

TSMC 40nm node

MOSFETs in most of the foundry processes have “Sidewall Si3N4/SiO2 structure” even down to 28nm node, including SOI processes.

- -

- -

- -

- - -

- -

- -

-

-

~2 eV

p-Si SiO2 Si3N4 TSMC 28nm node

Jan. 2018


Excellent Retention Characteristics Jan. 2018

The cell current was drastically reduced and has been stable even after baking for 100 hours at 200ºC, which is equivalent to over 30 years at 125ºC.

ID[A

]

0.18µm process

program

Baking


Jan. 2018 Program Operation

Driver & Pre-Amplifier

WL0 On

L H

Ex. High

High Off

Low WL1

Bit Bit

Gate Voltage

Dra

in C

urre

nt Hot-Carrier Effect

Program current flows in one transistor in a cell and generate hot-carriers.

OTP bit cell


Jan. 2018 Read Operation

Ion0 << Ion1

Amplifying Latch Driver & Pre-Amplifier

WL0

H H L

Low

High

Low WL1

Bit Bit

Ion1 Ion0

Hot Carrier Trapped Tr.

Both bit-lines are pre-charged and current flows through selected cell transistors. Sense amplifier senses current difference and latches.


Erase Operation in TwinBitTM Jan. 2018

Driver & Pre-Amplifier

SWL0

L L

Ex. High

Negative

Negative SWL1

Bit Bit


Jan. 2018

OTP IP Lineup


Jan. 2018 Availability in Foundry Processes

TSMC 0.18µm TSMC 0.13µm TSMC 0.11µm TSMC 90nm TSMC 65nm IBM 0.18µm Toshiba 65nm TowerJazz 0.18µm UMC 0.11µmAE UMC 0.11µmE SMIC 0.13µm GF 0.13µm Silterra 0.18µm Silterra 0.13µm Silterra 0.11µm LFoundry 0.15µm LFoundry 0.11µm

IP9000 Full Qual., Volume Production IP9000 Full Qual., Volume Production Silicon Verified Silicon Verified IP9000 Full Qual., Volume Production Ready-for-IBM, Volume Production Full Qualification, Volume Production Full Qualification, Volume Production Silicon Verified Silicon Verified Silicon Verified Silicon Verified In Silicon Verification In Silicon Verification In Silicon Verification Silicon Verified In Silicon Verification


Jan. 2018

New MTP Technologies


Jan. 2018

TwinBit™ for Automotive in TSMC0.18um (1.8V+5.0V)


Jan. 2018 Cell Current Distribution after 10K Cycle and Baking


Jan. 2018 Retention Lifetime Estimation after 10K Cycles

CEA Split L [µm] W [µm] 0.1 1 10 1003.6σ 6143 14.29% 13.64% 22.73% 45.83%3.0σ 6135 12.50% 12.00% 20.00% 42.31%2.0σ 6004 10.00% 8.70% 14.81% 37.04%1.0σ 5169 8.33% 4.76% 11.54% 29.63%0.0σ 3072 7.14% 4.35% 8.00% 23.08%0.0σ 3071 7.14% 4.35% 8.00% 23.08%-1.0σ 974 6.25% 4.00% 4.35% 18.52%-2.0σ 139 5.56% 3.85% 3.85% 13.79%-3.0σ 8 5.26% 3.57% 3.57% 10.34%-3.6σ 0 5.00% 3.45% 3.45% 7.14%

True/Bar Ratio[%]Sigma

Program Time: 1 [ms]Bake time at 200c [h]

5 Asymmetric 4 0.24 0.6

Before Baking

Lifetime of the worst bit = 8.86 years at 200°C

Worst Bit


Jan. 2018 Retention Lifetime Estimation after 10K Cycles

Temp.(°C) Lifetime (hours) Lifetime (years) 200 28,531 3.26 175 112,180 12.81 150 518,560 59.20 125 2,905,425 331.67

Assuming Ea = 1.0 eV, Cell Failure Rate = 1ppm.

Temp.(°C) Lifetime (hours) Lifetime (years) 200 8,496 0.97 175 33,405 3.81 150 154,416 17.63 125 865,172 98.76

Assuming Ea = 1.0 eV, Cell Failure Rate = 1ppb.


Jan. 2018

TwinBit™ in Fujitsu55nmDDC (0.9V+3.3V)


Endurance & Retention for 55nm (1) Jan. 2018

32Kbit: 10K cycle pre-bake 32Kbit: 10K cycle post-bake

Clear Gaussian distribution No tailing behavior Operational window for date retention


Endurance & Retention for 55nm (2) Jan. 2018

32Kbit: 10K cycle pre-bake 32Kbit: 10K cycle post-bake

Over 5-sigma window remaining even after baking.


TwinBitTM Cell Structure

0.25µm

in 55nm node

Bit Cell (0.1µm2)

Cross-point Cell Structure

Jan. 2018


MTP Comparison Table Jan. 2018

Vendor Type

Bit Cell Poly HV OX

Extra Mask Max Capacity Temp Range

Prog./Erc. Time Read Current Access Time

Endurance Data Retention

Company-A Floating Gate 1.5 Tr./Cell 3 Layers ~12V Core/IO/HV +13 2M Byte -40 to +125°C 10us/4ms 60uA/MHz <25ns 100K cycles 10Y@85-125°C

Company-B Floating Gate 3 Tr. + /Cell 1 Layer ~15V Core/IO 0 512Kb -40 to +125°C 50us/220ms 100uA/MHz <40ns 1K cycles 10Y@85-125°C

NSCore Charge-Trap 2 Tr./Cell 1 Layer 5-6V Core/IO 0 2M Byte -40 to +150°C 10us/100ms 30uA/MHz <20ns 100K cycles 100Y@175°C


Jan. 2018

Thank you!

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OTP & MTP/FRP Non -Volatile Memory IP for Standard Logic CMOS · Our OTP Cell Tr. SONOS NVM Cell...

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