Outline - polito.it ! IP routers ! OQ routers ! IQ routers " Scheduling " Optimal algorithms ... •...

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1

Scheduling algorithms for input-queued IP routers

Andrea Bianco Paolo Giaccone

Gruppo Reti di Telecomunicazioni Dipartimento di Elettronica

Politecnico di Torino http://www.tlc-networks.polito.it

Switching Architectures 2014/15 2

Outline

Ø  IP routers Ø  OQ routers Ø  IQ routers

§  Scheduling §  Optimal algorithms §  Heuristic algorithms §  Packet-mode algorithms §  Networks of routers §  QoS support

Ø  CIOQ routers Ø  Multicast traffic Ø  Conclusions

Switching Architectures 2014/15

3

Note

The slides marked RWP are reproduced with permission of Prof.Nick McKeown from the Electrical Engineering and Computer Science Dept. of Stanford University (CA,USA)


Outline





5

“The Internet is a mesh of routers”

core router

access router

enterprise router


Access router: Ø  high number of ports at low speed (kbps/Mbps) Ø  several access protocols (modem, ADSL, cable)

Enterprise router: Ø  medium number of ports at high speed (Mbps) Ø  several services (IP classification, filtering)

Core router: Ø  low number of ports at very high speed (Mbps/Gbps) Ø  very high throughput Ø  few services

“The Internet is a mesh of routers”


2

7

Basic architecture

Control Plane

Datapath per-packet processing

Switching Forwarding Table

Routing table

Routing protocols


Basic functions

Ø  Routing §  computation of the output port of

an incoming packet (forwarding) §  uses the routing tables computed by

the routing protocols §  can be a complex procedure:

•  very large routing tables •  dynamic variation of routes in the Internet


9

Basic functions

Ø  Switching §  transfer of packets from input ports

to output ports §  solution of the contentions for output ports

• queueing methods –  where to store

•  scheduling methods –  what to transfer


Faster and faster

Ø  Need for high performance routers §  to accommodate the bandwidth demands

for new users and new services §  to support QoS (over-provisioning) §  to reduce costs with respect to a cloud of smaller size

routers (maybe) •  a smaller number of fibers is needed •  a smaller number of devices (but it is less costly?) •  May be more energy hunghry

§  to ease of the management task

10 Switching Architectures 2014/15

11

Packet processing and link speed

0,1

1

10

100

1000

10000

1985 1990 1995 2000

Fibe

r Cap

acity

(Gbi

t/s)

TDM DWDM

Packet processing Power Link Speed

Source: http://www.gotw.ca/publications/concurrency-ddj.htm

RWP

Ø  Increase of electronic packet processing power cannot accommodate the increase in link speed


Moore’s law 2x / 18 months

Butter’s Law 2x / 9 months

12 0,001

0,01

0,1

1

10

100

10001980 1983 1986 1989 1992 1995 1998 2001

Acc

ess

Tim

e (n

s)

Moore’s Law 2x / 18 months

1.1x / 18 months

RWP

Memory access time


3

13

It’s hard to keep up with Moore’s law: §  the bottleneck is memory speed

Moore’s law is too slow: §  routers need to improve faster

than Moore’s law

RWP

Moore’s law


Router capacity exceeds Moore’s law

Growth in capacity of commercial routers: §  1992 ~ 2 Gb/s §  1995 ~ 10 Gb/s §  1998 ~ 40 Gb/s §  2001 ~ 160 Gb/s §  2003 ~ 640 Gb/s § … till 2003 average grow rate around 2.2x/18

months §  2012 ~ 10 Tb/s §  2014 ~ 100 Tb/s

RWP Switching Architectures 2014/15

15

Single packet processing

Ø  The time to process one packet is becoming shorter and shorter § worst case: 40-Byte packets (ACKs)

travelling over the Internet • 3.2 µs at 100 Mbps • 320 ns at 1 Gps • 32 ns at 10 Gps • 3.2 ns at 100 Gbps • 320 ps at 1Tbps


S F

LC

LC

LC

LC

CP

S F

IP

IP

IP

IP

CP

OP

OP

OP

OP

Hardware architecture

physical structure logical structure


17


Main elements Ø  line cards

§  support input/output transmissions §  adapt packets to the internal format of the switching fabric §  support data link protocols §  In most architectures

•  store packets •  classify packets •  schedule packets •  support security

Ø  switching fabric §  transfers packets from input ports to output ports


Ø  control processor/network processor §  runs routing protocols §  computes and stores routing tables §  manages the overall system §  sometimes

•  store packets •  classify packets •  schedule packets •  support security

Ø  forwarding engines §  inspect packet headers §  compute the packet destination (lookup)

•  Searching routing or forwarding (chaching) tables §  rewrite packet headers



4

19

switching fabric

line card line card

control processor &

forwarding engine

1 N

Interconnections among main elements - I


switching fabric

line card line card

control

processor

forwarding

engine

forwarding

engine

1 N

Interconnections among main elements - II


21

Interconnections among main elements - II

switching fabric

line card & forwarding engine

control

processor

1

line card & forwarding engine

N Switching Architectures 2014/15

Cell-based routers

Ø  ISM: Input-Segmentation Module

Ø  ORM: Output-Reassembly Module

Ø  packet: variable-size data unit

Ø  cell: fixed-size data unit

22

Cell switch (fabric) ORM 1

ORM N

1

ISM

N

ISM

packets cells cells packets


23

Switching fabric

Ø  Our assumptions: §  bufferless

•  to reduce internal hardware complexity §  non-blocking

• given a non-conflicting set of inputs/outputs, it is always possible to connect inputs with outputs


Switching fabric

Ø  Examples: §  bus §  shared memory §  crossbar §  Multi-stage

•  rearrangeable Clos network •  Benes network •  Batcher-Banyan network (self-routing)

Ø  Switching constraints §  at most one cell for each input and for each output

can be transferred

1 2 3 4

1 2 3 4 outputs

inpu

ts


5

25

Switching fabric

Ø  We do not discuss switching fabrics with internal buffers §  e.g.: crossbars with buffer at each crosspoint


Generic switching architecture

Output 1

switching fabric

Input 1

Input N Output N

Sin

Sin

Sout

Sout

input queues output queues


27

Speedup

Ø  The speedup limits the switch performance §  Sin = reading speed from input queues §  Sout = writing speed to output queues

Ø  The main performance limit can be due to the maximum speedup factor:

S = max(Sin,Sout)


Performance comparison

Ø  The performance of different switching systems can be studied § with analytical models

•  introducing simplifying assumptions, but obtaining general results

§ with simulation models • obtaining more detailed results


29

Traffic description Ø  Aij(n) = 1 if a packet arrives at time n at input i,

with destination reachable through output j Ø  λij = E[Aij(n)] Ø  An arrival process is admissible if:

§ ∑i λij < 1

§ ∑j λij < 1 •  that is, no input and no output are overloaded

on average •  note that OQ switches exhibit finite delays only

for admissible traffic Ø  traffic matrix: Λ = [λij ]


Traffic scenarios

Ø  Uniform traffic §  Bernoulli i.i.d. arrivals §  usual testbed in the literature

•  “easy to schedule”

Ø  Diagonal traffic §  Bernoulli i.i.d arrivals §  critical to schedule, since only two matchings are good

⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

=Λ

2001120001200012

3ρ

⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

=Λ

1111111111111111

Nρ


6

31

Traffic scenarios

Ø  LogDiagonal traffic §  Bernoulli i.i.d. arrivals § more critical than uniform,

less than diagonal traffic

⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

−=Λ

8124481224811248

12Nρ


Outline





33

Output Queued (OQ) switches

Ø  Sin = 1 Sout = N Ø  used for low bandwidth routers

§  no coordination among ports § work-conserving

• best average delays §  complete control of delays

•  support of QoS scheduling


Output Queued (OQ) switch

speedup N

Output N

Output 1

switching fabric

Input 1

Input N


35

0% 20% 40% 60% 80% 100%

Normalized load

Del

ay

OQ performance

OQ

Note: OQ is optimal from the point of view of average delay and

throughput

Uniform traffic


Stability, throughput and delays

Ø  Hp: stationary system, infinite queue

Ø  for a particular λin §  stable ⇔ finite occupancy ⇔ finite delays ⇔ λin= λout

Ø  100% throughput ⇔ stable under any λin admissible

λin λout


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37

Stability, throughput and delays

Ø  λout≤ λmax

Ø  stable(λin) ⇔ λin= λout ⇒ λin≤ λmax §  hence, λmax is

•  maximum throughput achievable •  maximum offered load for stability

Ø  unstable (λin) ⇔ λin> λmax

§  queue grows with rate λin- λmax

λin

λout

λmax

λin

delay

λmax λmax


Outline





39

Simple Input Queued (IQ) switches

Ø  Sin = 1 Sout = 1 Ø  1 FIFO queue for each input port Ø  throughput limitations

§  due to head of the line (HOL) blocking Ø  scheduling

§  to solve contentions for the same output

Output N

Input 1 Output 1

switching fabric

Input 1


Head of the Line (HOL) Blocking


41

0% 20% 40% 60% 80% 100%

Normalized load

Del

ay

Simple IQ switch performance

OQ Simple IQ

Uniform traffic

%5822 ≈−


Single IQ switch

Ø  Using a simple Markov chain model §  2x2 à throughput 0.75

•  states: (2,0), (1,1) §  3x3 à throughput ?

•  states: (3,0,0), (2,1,0), (1,1,1)


8

Bufferless switch

Ø  Throughput= §  uniform i.i.d. Bernoulli arrivals §  input load p


63.0111 1 ≈−→⎟⎠

⎞⎜⎝

⎛ −− −eNp N

44

Improving IQ switches performance

Ø  Window/bypass schedulers §  the first w cells of each queue contend

for outputs § HOL blocking is reduced, not eliminated § w = 1 means FIFO at each input §  higher complexity

•  the scheduler deals with wN cells • non-FIFO queues


45


Ø  Maximum throughput in an NxN switch with variable window size w

N W=1 W=2 w=3 w=4 W=5 W=6 W=7 W=8 2 0.75 0.84 0.89 0.92 0.93 0.94 0.95 0.96 4 0.66 0.76 0.81 0.85 0.87 0.89 0.91 0.92 8 0.62 0.72 0.78 0.82 0.85 0.87 0.88 0.89

16 0.60 0.71 0.77 0.81 0.84 0.86 0.87 0.88 32 0.59 0.7 0.76 0.8 0.83 0.85 0.87 0.88 64 0.59 0.7 0.76 0.8 0.83 0.85 0.86 0.88

128 0.59 0.7 0.76 0.8 0.83 0.85 0.86 0.88



Ø  Virtual output queueing (VOQ) §  one queue for each input/output pair

• N queues at each input • N2 queues in the whole switch

§  eliminates HOL blocking §  used in high-bandwidth routers

•  scheduling implemented in hardware at very high speed


47

IQ switches with VOQ

Output N

Input 1 1

N

Output 1

Input N 1

N

scheduler

switching fabric

Note: from now on, we always assume VOQ at the switch inputs

input constraints

output constraints


Outline





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49

Scheduling in IQ switches

Ø  Scheduling can be modeled as a matching problem in a bipartite graph §  the edge from node i to node j refers to packets

at input i and directed to output j §  the weight of the edge can be

•  binary (not empty/empty queue) •  queue length •  HOL cell waiting time, or cell age •  some other metric indicating the priority

of the HOL cell to be served


Scheduling in IQ switches

5

Graph G Matching M1

2

3

4

3

4

2

54

8

2

5

4

4

8

1

2

3

4

1

2

3

4

1

2

3

4

Graph Matching

inputs outputs

scheduler Switching Architectures 2014/15

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Implementing schedulers

Ø  Scheduling is a complex task §  a scheduling algorithm can be implemented

in hardware if: •  it shows good performance for a wide range

of traffic patterns •  it can be efficiently parallelized •  it can be efficiently pipelined •  it requires few iterations (or clock cycles) •  it requires limited control information


Scheduling uniform traffic

Ø  A number of algorithms give 100% throughput when traffic is uniform §  For example:

• TDM and a few variants •  iSLIP (see later)

RWP

Example of TDM for a 4x4 switch


53

Scheduling non-uniform traffic

Ø  If the traffic is known and admissible, 100% throughput can be achieved by a TDM using: §  for a fraction of time a1 matching M1 §  for a fraction of time a2 matching M2 §  for a fraction of time ak matching Mk

§  subject to ∑i ai = 1 Ø  thanks to the Birkhoff - von Neumann

theorem Switching Architectures 2014/15 54

Outline





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55

Maximum Weight Matching

Ø  Maximum Weight Matching (MWM) §  among all the possible N! matchings, selects the one

with the highest weight (sum of the edge metrics) •  MWM is generally not unique

§  MWM is too complex to be implemented in hardware at high speed

•  the best MWM algorithm requires O(N3) iterations, and cannot be implemented efficiently, since it is based on a flow augmentation path algorithm

•  cannot be parallelized and pipelined efficiently §  MWM has never been implemented in a commercial

chipset Switching Architectures 2014/15 56

Maximum Weight Matching

Ø  MWM is the optimal solution of the scheduling problem when the traffic is unknown, when the weight is either the queue length or the cell age §  achieves 100% throughput under any traffic

•  also under non-Bernoulli arrival processes, satisfying the law of large numbers

§  achieves low average delays, very close to those of OQ switches

§  possible starvation for lightly loaded packet flows


57

MWM with pipeline and latency

Ø  Let T and P be fixed Ø  Dt denotes the matching used at time t Ø  The following variations of MWM also achieve

100% throughput: §  Dt = MWM(t-P) MWM with pipeline degree P §  Dt = MWM(ceil(t/T)•T) MWM with latency T §  combinations of both

Ø  thus, it seems easy to achieve 100% throughput!


MWM with pipeline and latency

Ø  But: § What about throughput?

• 100% throughput – but needs the computation of a MWM …

§ What about delays? • delays can be really bad!

J

L

L


59

General consideration

Ø  When scheduling in IQ switches, it is very difficult to achieve simultaneously §  high throughput §  low delay §  limited implementation complexity


Maximum Size Matching

Ø  Maximum Size Matching (MSM) §  among all the possible matchings, selects the one

with the highest number of edges (like MWM with binary edge weights)

•  MSM is generally not unique §  the best MSM algorithm requires O(N2.5) iterations,

and cannot be implemented efficiently, since it is based on a flow augmentation path algorithm


11

61

Maximum Size Matching

Ø  MSM maximizes the instantaneous throughput

Ø  MSM may not yield 100% throughput §  short term decisions can be inefficient

in the long term §  non-binary edge weights allow MWM

to maximize the long-term throughput


Instability of MSM Ø  Assume:

§  P(arrival at Q12) = λ §  P(arrival at Q11) = P(arrival at Q22) = 1-λ-ε

§  Q12 = B » 0 Q11 = Q22 = 0 §  in case of parity serve Q11 and/or Q22 instead of Q12

Ø  Observe: §  Q12 is served only when A11 = 0 and A22 = 0, i.e. with probability:

P(serve Q12) = P(no arrivals at both Q11 and Q22 ) = [1-(1-λ-ε)]2 = (λ+ε)2 §  P(serve Q12) < P(arrival at Q12) if ε is small enough §  Example: λ = 0.5; ε = 0.1;

P(serve Q12) = 0.36 In1

In2

Out1

Out2

1-λ-ε

1-λ-ε

λ

Note: this proof is due to I.Keslassy and R.Zhang, Stanford Univ. Switching Architectures 2014/15

63

Uniform traffic Ø  MWM and MSM behave almost identically

1

10

100

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Mea

n de

lay

Normalized Load

Uniform Traffic

MWM MSM


LogDiagonal traffic Ø  MSM is somewhat inferior to MWM

1

10

100

1000

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Mea

n de

lay

Normalized Load

LogDiagonal Traffic

MWM MSM


65

Diagonal traffic Ø  MSM yields much longer delays than MWM at medium/high loads

1

10

100

1000

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Mea

n de

lay

Normalized Load

Diagonal Traffic

MWM MSM


Outline





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67

Approximations of MSM and MWM

Ø  Motivation §  strong interest in scheduling algorithms with

•  very low complexity • high performance

Ø  Usually §  implementable schedulers (low complexity)

⇒ low throughput, long delays §  theoretical schedulers (high complexity)

⇒ high throughput, short delays


Some implementable algorithms

Ø  Approximate MSM § WFA, iSLIP, 2DRR, RC, FIRM and many others

Ø  Approximate MWM with wij = Xij (queue length) §  iLQF, RPA, learning algorithms

Ø  Approximate MWM with wij = cell age §  iOCF

Ø  Approximate MWM with wij = ∑i Xij+ ∑j Xij §  iLPF, MUCS


69

APPROXIMATIONS OF MAXIMUM SIZE

MATCHING


Wave Front Arbiter

Requests Match 1

2

3

4

1

2

3

4

1

2

3

4

1

2

3

4


71

Wave Front Arbiter

Requests Match

RWP

2N-1 steps


Wrapped Wave Front Arbiter

Requests Match

N steps instead of 2N-1


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73

iSLIP

Ø  iSLIP means “iterative SLIP” Ø  iterates among the following 3 phases

§ Request § Grant §  Accept


iSLIP

iSLIP demo

from: http://tiny-tera.stanford.edu/tiny-tera/demos/index.html


75

iSLIP Ø  3 phases:

§ Request (from inputs to outputs) • each unmatched input sends a request

to every output for which it has a cell § Grant (from outputs to inputs)

•  if an unmatched output receives requests, it sends a grant to one of the inputs

– contentions solved by a round-robin mechanism §  Accept (from inputs to outputs)

•  if an unmatched input receives grants, it selects a single output and it becomes matched to it

– contentions solved by a round-robin mechanism Switching Architectures 2014/15 76

iSLIP

Ø  The round robin mechanism in iSLIP is designed so that, under uniform traffic, iSLIP emulates a dynamic TDM scheduler synchronized on the arrival pattern


77

iSLIP

Ø  iSLIP is maximal • often, with log N iterations • always, with N iterations

Ø  iSLIP was implemented on a single chip in the Cisco 12000 router §  http://www.cisco.com/warp/public/cc/pd/rt/12000/tech/fasts_wp.pdf


APPROXIMATIONS OF MAXIMUM WEIGHT

MATCHING


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79

iLQF

Ø  iLQF means “iterative Longest Queue First”

Ø  iterates among the following 3 phases § Request § Grant §  Accept


iLQF

iLQF demo

from: http://tiny-tera.stanford.edu/tiny-tera/demos/index.html


81

iLQF Ø  3 phases:

§  Request (from inputs to outputs) •  each unmatched input sends all its queue lengths

as requests to corresponding outputs §  Grant (from outputs to inputs)

•  if an unmatched output receives requests, it sends a grant to the input corresponding to the longest queue

–  contentions solved by random choice

§  Accept (from inputs to outputs) •  if an unmatched input receives grants, it selects

the output with the longest queue –  contentions solved by random choice


iLQF

Ø  iLQF is maximal • often, with log N iterations • always, with N iterations

Ø  iLQF is robust to non-uniform traffic


87

Uniform traffic Ø  comparison between MWM, iSLIP, iLQF, and RPA

1

10

100

1000

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Mea

n de

lay

Normalized Load

Uniform Traffic MWM iSLIP iLQF RPA


LogDiagonal traffic Ø  iSLIP saturates close to 84% throughput

1

10

100

1000

10000

100000

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Mea

n de

lay

Normalized Load

LogDiagonal Traffic

MWM iSLIP iLQF RPA


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89

Diagonal traffic Ø  RPA achieves 98% throughput, iLQF 87%, iSLIP 83%

1

10

100

1000

10000

100000

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Mea

n de

lay

Normalized Load

Diagonal Traffic

MWM iSLIP iLQF RPA


Outline





106

Routers and switches

Ø  IP routers deal with variable-size packets Ø  Hardware switching fabrics often deal

with fixed-size cells Question:

§  how to integrate an hardware switching fabric within an IP router?


Router based on an IQ cell switch: cell-mode

switching fabric

IQ cell switch 1 ISM

N ISM

ORM 1

ORM N


108

Cell-mode scheduling

Ø  Scheduling algorithms work at cell level §  pros:

• 100% throughput achievable §  cons:

•  interleaving of packets at the outputs of the switching fabric


Router based on an IQ cell switch: packet-mode

switching fabric


N ISM

ORM 1

ORM N

NO packet interleaving

if packet-mode


16

110

Router based on an IQ cell switch: packet-mode

switching fabric


N ISM

ORM 1

ORM N

NO packet interleaving

if packet-mode

ORMs can be removed


Packet-mode scheduling

Ø  Rule: packets transferred as trains of cells §  when an input starts transferring the first cell

of a packet comprising k cells, it continues to transfer in the following k-1 time slots

Ø  Pros: §  no interleaving of packets at the outputs §  easy extension of traditional schedulers

Ø  Cons: §  starvation due to long packets

•  inherent in packet systems without preemption •  negligible for high speed rates


112

Packet-mode scheduling

Ø  Questions § can packet mode provide high

throughput?

§ what about delays? YES! J

It depends…K


Packet-mode properties

Ø  Main theoretical results § MWM in packet-mode yields 100% throughput §  Packet mode can provide shorter delays

than cell mode, depending on the packet length distribution


114

Simulation scenario

Ø  Router with ISMs and ORMs Ø  Uniform packet traffic

§  uniform packet load §  uniform (1,192) packet size

distribution Ø  Spotted packet traffic

§  non uniform packet load §  bimodal (3,100) packet size

distribution

1 1 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 0 1 0 1 1 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 1 1 0 1 1 1 0 1 0 0 1 1 1 0 1 0 1

ΛP=


Uniform packet traffic Ø  Packet mode and cell mode reach the same throughput

Cell-mode Packet-mode

100

1000

10000

100000

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Mea

n pa

cket

del

ay

Normalized Load

Uniform packet traffic for packet mode

100

1000

10000

100000

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Mea

n pa

cket

del

ay

Normalized Load

Uniform packet traffic for cell mode MWM MSM iSLIP iLQF


17

116

Spotted packet traffic Ø  Packet mode reaches higher throughput than cell mode

100

1000

10000

100000

0.5 0.6 0.6 0.7 0.7 0.8 0.8 0.9 0.9 1.0 1.0

Mea

n pa

cket

del

ay

Normalized Load

Spotted packet traffic for packet mode

100

1000

10000

100000

0.5 0.6 0.6 0.7 0.7 0.8 0.8 0.9 0.9 1.0 1.0

Mea

n pa

cket

del

ay

Normalized Load

Spotted packet traffic for cell mode MWM MSM iSLIP iLQF

Cell-mode Packet-mode


At high load PM becomes better

Effect of packet size distribution Ø  iSLIP delayCM/delayPM for different packet size distributions

better PM

better CM

0

0.5

1

1.5

2

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Pac

ket m

ode

gain

for i

SLI

P

Normalized load

Uniform Exponential Trimodal Bimodal


118

Packet mode features

Ø  Packet mode scheduling §  is a feasible modification of schedulers §  improves throughput

• but it can generate some unfairness between long and short packets

– inherent to all variable-packet networks without preemption

§ may give better packet delays than cell mode • depends on the packet size distribution


Outline





120

Network of IQ routers

Ø  Question: §  given a network of IQ switches running MWM

and an admissible input traffic, is the network always stable?

NO! L

this is quite counterintuitive…but true


Networks of IQ routers

Ø  Consider the acyclic network of IQ routers in the following slide §  derived from well established results

from adversarial queueing theory §  a very specific scenario, but comprises

only few switches… •  this situation may not be common,

but cannot be excluded in real networks


18

122

Pathological network of IQ switches

Network with 8 switches and 4 flows


Instability of MWM

Ø  If MWM is adopted at each IQ router, and the traffic is admissible, the system can be unstable under Bernoulli i.i.d. arrivals


124

Instability of MWM

Ø  MWM is too greedy, in the sense that it can create traffic bursts that are amplified by each scheduler

Ø  A server can be idling when large bursts (directed to it) are blocked because of the contentions upstream §  the problem arises when a packet flow is

subject to priority changes along its path through the network


Stability in networks of routers

Ø  Global policies §  “Oldest in the network” and many others

• problem: requires global information about the network, and synchronized clocks at the ingress of the network


126

Stability in networks of routers

Ø  Semi-local policies § MWM with local information about the router

neighbors can achieves 100% throughput under i.i.d. Bernoulli arrivals

§  Virtual network queue •  the weights used by MWM are:

–  wij = max{0,Xij-Xdown-queue(ij))} where down-queue(ij) is the first downstream

queue which is receiving packets from Xij


Outline





19

128

IQ and QoS

Ø  Problem: §  support rate guarantees, with admissible rate

matrix


Birkhoff von Neumann decomposition

Ø  goal: find a sequence of matchings Mk and their fraction of time φk such that the service given to all the queues satisfies R


130

IQ and frame scheduling

Ø  Example:

M1

φ1=1/4, φ2=1/2, φ3=1/4

M2 M2 M3 M1 M2 M2 M3

frame i frame i+1


How to decompose R?

Ø  R double substochastic

Ø  R’ double stochastic such that R’≥R

Ø  R’ decomposition

augmentation algorithm

BvN algorithm


132

Augmentation algorithm


BvN algorithm


20

134

BvN algorithm


Outline





136

CIOQ routers

Output 1

switching fabric

Output N

S

S

o1

oN

Input 1 S

Input N S

VOQ


CIOQ routers

Ø  Question: §  if a low speedup S is allowed (and queues

are available at both inputs and outputs), is it possible to design simple scheduling algorithms, capable of achieving high throughput and low delay?

YES! J


138

OQ emulation

Ø  a CIOQ switch achieves perfect OQ emulation if the departure order of all the packets from each output is the same as the emulated OQ §  it is impossible to distinguish, by observing

arrivals and departures, if the switching architecture is CIOQ or OQ

§  delays are perfectly controlled • easy to implement scheduling algorithms

born for OQ (eg: WFQ)


Work conservation

Ø  a CIOQ switch is work-conserving when each output is busy at the same time as the corresponding OQ switch §  i.e., each output of the switch for which there are cells

(either at the inputs or at the outputs) at the beginning of cell slot T is active at the end of the cell slot T

§  output never idling whenever a packet is present destined to it

§  good delay performance: same average delays as OQ Ø  note that OQ emulation implies work conservation

but not viceversa


21

140

Speedup and performance

Ø  speedup 4 §  exact OQ emulation

Ø  speedup 2 §  exact OQ emulation § work conservation

•  same average delay than OQ


CIOQ routers with S=2

Ø  If S = 2 §  easy to obtain 100% throughput

• any maximal matching obtains 100% throughput

§  less easy to obtain work conservation • LOOFA algorithm

§  it is difficult to obtain perfect OQ emulation •  stable marriage algorithm with special

preference list Switching Architectures 2014/15

142

LOOFA

Ø  Occupancy oj : number of cells currently residing at the j-th output queue

• at each time slot, oj is decremented by one because of departures

Ø  Basic idea of LOOFA § Higher priority is given to outputs with lower

occupancy, thereby attempting to maintain work-conservation for all outputs


LOOFA

Ø  If S = 2, during each of the two phases §  each unmatched input selects a non-empty

VOQ directed to the unmatched output with the lowest occupancy, and sends a request to that output

§  each unmatched output grants one request •  the selection can be round robin, random, ...

§  repeat until the matching is maximal


144

LOOFA with S=2

Ø  TEO: §  LOOFA achieves work conservation if S = 2


OQ emulation with S=4

Ø  urgency of a cell=departure time in OQ-current time

Ø  MUCF (Most urgent cell first) During each phase: 1.  outputs request their most urgent cells from inputs 2.  input grants output with the most urgent cell 3.  loser output tries to obtain their next urgent cell 4.  when no more matchings are possible, cells are

transferred and the next phase starts


22

146

OQ emulation with S=4

Note: picture reproduced from Balaji Prabhakar and Nick McKeown, "On the Speedup Required for Combined Input and Output Queued Switching.", Computer Systems Technical Report, November 1997


OQ emulation and speedup 4

Ø  TEO: § MUCF with speedup 4 obtains OQ emulation


148

CIOQ routers

Ø  CIOQ are very promising architectures §  many degrees of freedom in design

•  how to balance input/output buffers •  how the buffers interact

–  e.g., by backpressure mechanisms

Ø  Several currently designed architectures are supposed to be CIOQ

Ø  Speedup S is becoming closer and closer to 1 in practical implementations of new switching architectures (CIOQ →IQ)


Outline





150

Multicast traffic

Misleading idea: Ø  observe

1.  OQ can achieve 100% throughput under any admissible unicast and multicast traffic

2.  OQ can be perfectly emulated by CIOQ with S = 2

§  then, with S = 2 it is possible to achieve 100% throughput for multicast traffic

WRONG! L because observation 2 holds only for unicast traffic Switching Architectures 2014/15 151

Multicast traffic

Ø  Question: § what is the minimum speedup required

to achieve 100% throughput?

unknown! L


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152

Multicast traffic Ø  Possible implementations

§  copy network before the switching fabric •  a multicast cell with f destinations is treated as f cells •  possible bandwidth inefficiency

§  dedicated queue •  multicast packets are treated in some specific way

1 UC

MC N

N × N

UC+MC

N × N


Multicast traffic: optimal queueing

Ø  MC-VOQ queueing §  best throughput performance

•  avoids HOL blocking §  2N-1 queues for each input, one for each fanout set

•  re-enqueuing process ⇒ out-of-sequence problem •  no re-enqueuing ⇒ some throughput degradation

MC+UC

1

2N-1 N × N


154

Multicast traffic: optimal scheduling

Ø  The optimal scheduling for multicast traffic can be defined similarly to unicast traffic §  it is a sort of max flow algorithm on all N(2N-1)

queues Ø  Many heuristics can be envisaged

to approximate it


Summary

Ø  3 main ingredients for IQ scheduling algorithms: §  Weight computation §  Matching computation §  Contention resolution


156

Summary

Ø  Weight computation § obtains the priority of each input queue § the metric can be related to queue length,

waiting time of the cell at the HOL, … Ø  Contention resolution

§ whenever the selection is among situations with equal weights

§ can be round robin, or random


Summary

Ø  Matching computation § computes the matching, trying to maximize

its total weight § can be based on

§ an iterative search, like in iSLIP, iOCF, iLQF

§ a matrix greedy approach, like in MUCS, WFA

§ a reservation vector, like in RPA § a learning approach, like in APSARA


24

158

Summary

Ø  Good IQ scheduling algorithms exist: §  100% throughput §  short delay §  limited complexity

Ø  Performance differences are significant only close to saturation


Summary

Ø  Open questions concerning IQ schedulers: §  QoS guarantees §  stability of networks of switches §  multicast traffic


160

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Magazine, Jan.1997, pp.64-69 §  Wolf T., Turner J.S., ``Design issues for high-performance active routers'', IEEE Journal on Selected Areas in

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switches'', IEEE INFOCOM'98, vol.2, 1998, pp.792-9, New York, NY §  Tamir Y., Chi H.-C., ``Symmetric crossbar arbiters for VLSI communication switches'', IEEE Transaction on

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GLOBECOM 95


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Transactions on Computer Systems, vol.11, n.4, Nov.1993 §  LaMaire R.O., Serpanos D.N., ``Two dimensional round-robin schedulers for packet switches with multiple

input queues'', IEEE/ACM Transaction on Networking, vol.2, n.5, Oct.1994, p.471-482 §  Chen H., Lambert J., Pitsilledes A., ``RC-BB switch. A high performance switching network for B-ISDN'', IEEE

GLOBECOM 95, 1995 §  Duan H., Lockwood J.W., Kang S.M., Will J.D., `À high performance OC12/OC48 queue design prototype for

input buffered ATM switches'', IEEE INFOCOM'97, vol.1, 1997, pp.20-8, Los Alamitos, CA §  Partridge C., et al., `À 50-Gb/s IP router'', IEEE Transactions on Networking, vol.6, n.3, June 1998, pp.

237-248 §  Ajmone Marsan M., Bianco A., Leonardi E., Milia L., ``RPA: a flexible scheduling algorithm for input buffered

switches'', IEEE Transactions on Communications, vol.47, n.12, Dec.1999, pp.1921-1933 §  Ajmone Marsan M., Bianco A., Filippi E., Giaccone P.,Leonardi E., Neri F.,`Òn the behavior of input

queueing switch architectures'', European Transactions on Telecommunications, vol.10, n.2, Mar.1999, pp.111-124

§  Christensen K.J.,``Design and evaluation of a parallel-polled virtual output queued switch'', IEEE ICC 2001, vol.1, pp.112-116, 2001

§  Serpanos D.N., Antoniadis P.I., ``FIRM: a class of distributed scheduling algorithms for high-speed ATM switches with multiple input queues'', IEEE INFOCOM 2000, vol.2, pp.548-555, 2000

§  Ying Jiang, Hamdi, M., “A 2-stage matching scheduler for a VOQ packet switch architecture”, IEEE ICC 2002, vol.4, pp.2105-2110, 2002

§  Tassiulas L., ``Linear complexity algorithms for maximum throughput in radio networks and input queued switches'', IEEE INFOCOM'98, vol.2, New York, NY, 1998, pp.533-539

§  Giaccone P., Prabhakar B., Shah D., ``Towards simple, high-performance schedulers for high-aggregate bandwidth switches '', IEEE INFOCOM'02, New York, Jun.2002 Switching Architectures 2014/15

162

References Packet scheduling in IQ switches §  Ajmone Marsan M., Bianco A., Giaccone P., Leonardi E., Neri F., ``Packet scheduling in input-queued cell-

based switches'', IEEE INFOCOM'01, Anchorage, Alaska, Apr.2001(extended version to appear in IEEE Trans. on Networking, about Oct.2002)

§  Moon S.H., Sung D.K., ``High-performance variable-length packet scheduling algorithm for IP traffic'', IEEE GLOBECOM'01, Dec.2001

Scheduling multicast traffic in IQ switches §  Hayes J.F., Breault R., Mehmet-Ali M.K., ``Performance analysis of a multicast switch'', IEEE Transactions on

Communications, vol.39, n.4, Apr.1991, pp.581-587 §  Kim C.K., Lee T.T., ``Call scheduling algorithm in multicast switching systems'', IEEE Transactions on

Communications, vol.40, n.3, Mar.1992, pp.625-635 §  McKeown N., Prabhakar B., ``Scheduling multicast cells in an input-queued switch'', INFOCOM'96, vol.1,

San Francisco, CA, Mar.1996, pp.261-278 §  Prabhakar B., McKeown N., Ahuja R., ``Multicast scheduling for input-queued switches'', IEEE Journal on

Selected Areas in Communications, vol.15, n.5, Jun.1997, pp.855-866 §  Chen W., Chang Y., Hwang W., `À high performance cell scheduling algorithm in broadband multicast

switching systems'', IEEE GLOBECOM'97, vol.1, New York, NY, 1997, pp.170-174 §  Guo M., Chang R., ``Multicast ATM switches: survey and performance evaluation'', Computer Communication

Review, vol.28, n.2, Apr.1998, pp.98-131 §  Andrews M., Khanna S., Kumaran K., `Ìntegrated scheduling of unicast and multicast traffic in an input-

queued switch'', IEEE INFOCOM'99, vol.3, New York, NY, 1999, pp.1144-1151 §  Liu Z., Righter R., ``Scheduling multicast input-queued switches'', Journal of Scheduling, John Wiley & Sons,

May 1999 Switching Architectures 2014/15 163

References Scheduling multicast traffic in IQ switches §  Nong G., Hamdi M., `Òn the provision of integrated QoS guarantees of unicast and multicast traffic in input-

queued switches'', IEEE GLOBECOM'99, vol.3, 1999 §  Ajmone Marsan M., Bianco A., Giaccone P., Leonardi E., Neri F., `Òn the throughput of input-queued cell-

based switches with multicast traffic'', IEEE INFOCOM'01, Anchorage Alaska, Apr.2001 §  Ge Nong, Hamdi M., “Providing QoS guarantees for unicast/multicast traffic with fixed/variable-length packets

in multiple input-queued switches”, IEEE Symposium on Computers and Communications, pp.166 –171, 2001

§  Smiljanic A., “Flexible bandwidth allocation in high-capacity packet switches”, IEEE/ACM Transactions on Networking, vol.10, n.2, pp.287-293, Apr.2002

QoS support in IQ switches §  Tabatabaee V., Georgiadis L., Tassiulas L., ``QoS provisioning and tracking fluid policies in input queueing

switches'', IEEE INFOCOM'00, New York, Mar.2000 §  Chang C.S., Lee D.S., Jou Y.S., ``Load balanced Birkhoff-von Neumann switches'', 2001 IEEE Workshop on

High Performance Switching and Routing, 2001, pp.276-280. §  Hung A., Kesidis G., McKeown N.,`ÀTM input-buffered switches with guaranteed-rate property'', IEEE

ISCC'98, July 1998, pp.331-335, Athens, Greece

Advanced architectures derived from pure IQ §  Iyer S., McKeown N., ``Making parallel packet switches practical'', IEEE INFOCOM'01, Alaska, Mar.2001 §  Chang C.S., Lee D.S., Jou Y.S., ``Load balanced Birkhoff-von Neumann switches'', 2001 IEEE Workshop on

High Performance Switching and Routing, 2001, pp.276-280 §  Sivaram R., Stunkel C.B., Panda D.K., “HIPIQS: a high-performance switch architecture using input queuing”,

IEEE Transactions on Parallel and Distributed Systems, vol.13, n.3, pp.275-289, Mar.2002


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References Scheduling in networks of IQ switches §  L.Tassiulas, A.Ephremides,``Stability properties of constrained queueing systems and scheduling policies for

maximum throughput in multihop radio networks'',IEEE Transactions on Automatic Control,vol.37, n.12, Dec.1992, pp.1936-1948

§  M.Andrews, L.Zhang,`Àchieving Stability in Networks of Input-Queued Switches'',IEEE INFOCOM 2001, Anchorage, Alaska, Apr.2001, pp.1673-1679

§  M.Ajmone Marsan, E.Leonardi, M.Mellia, F.Neri,`Òn the Throughput Achievable by Isolated and Interconnected Input-Queued Switches under Multicass Traffic'',IEEE INFOCOM 2002, New York, NY (USA), June 2002

§  M. Ajmone Marsan, P. Giaccone, E. Leonardi, F. Neri,`Òn the Stability of Local Scheduling Policies in Networks of Packet Switches with Input Queues'', IEEE JSAC, to appear, 2003


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