1
EE311/ Saraswat/ Cu Interconnect1 tanford University
Outline
•Interconnect scaling issues
•Polycides, silicides and metal gates
•Aluminum technology
•Copper technology
EE311/ Saraswat/ Cu Interconnect2 tanford University
Wire Half Pitch vs Technology Node
Narrow line effects
Ref: J. Gambino, IEDM, 2003
ITRS 2002
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EE311/ Saraswat/ Cu Interconnect3 tanford University
1
1
A1
CS1
1
A1/S
1
SCS1
0.5 0.5
1
1
A1
CS1
1
0.5
CS1
0.5 0.5
A1/S2
Interconnect Scaling Scenarios• Scale Metal Pitch with Constant Height
- R, Cs and J increase by scaling factor
- Higher aspect ratio for gapfill / metal etch
- Need for lower resistivity metal, Low-k
• Scale Metal Pitch and Height
- R and J increase by square of scaling factor
- Sidewall capacitance unchanged
- Aspect ratio for gapfill / metal etch unchanged
- Need for very low resistivity metal with significantly improved EM performance
EE311/ Saraswat/ Cu Interconnect4 tanford University
Low ρ (Resistivity)Metal
AgCuAuAlW
Bulk Resistivity [µΩ•cm]1.631.672.352.675.65
Why Copper?
Cu is the second best conducting element
Reduced RC delay
2
3
4
5
6789
10
20
30
40
0.1 0.2 0.3 0.4 0.5 0.6
De
aly
Tim
e (
ps
ec
)
Feature Size (µm)
50
Cu+Low-k(2.0) Interconnect Delay
Gate Delay
Al+SiO2
Interconnect Delay
Cu+Low-k(2.0) Total Delay
Al+SiO2
Total Delay
Calculations assume longest interconnect in the chip controls delay
RC =!
tM
"L2#
ILD
tILD
3
EE311/ Saraswat/ Cu Interconnect5 tanford University
Ref: S. Luce, (IBM), IEEE IITC 1998
highelectromigration
resistance
Al Cu
Melting Point 660 ºC 1083 ºC
Ea for Lattice Diffusion 1.4 eV 2.2 eV
Ea for Grain BoundaryDiffusion
0.4 – 0.8 eV 0.7 – 1.2 eV
Cu Has Excellent Reliability
Stress Time (hours)
Per
cent
ile
J = 2.5x106 A/cm2
T = 295°C
CuT50= 147.7 Hrs
Al(Cu)T50= 1.31 Hrs
> 110X
EE311/ Saraswat/ Cu Interconnect6 tanford University
Why Cu and Low-k Dielectrics?
Better electromigration resistance, reduced resistivity and dielectricconstant results in reduction in number of metal layers as more wirescan by placed in lower levels of metal layers.
global
semiglobal
local
Ref: M. Bohr, IEDM 1995.0
2
4
6
8
10
12
14
Num
ber
of M
eta
l Layers
Technology Generation (µm)
0.09 0.13 0.18 0.25 0.35
Cu/Low-k
Al/Low-kCu/SiO
2
Al/SiO2
RC =!
tM
"L2#
ILD
tILD
4
EE311/ Saraswat/ Cu Interconnect7 tanford University
Cu atoms ionize, penetrate into the dielectric, andthen accumulate in the dielectric as Cu+ space charge.
Problem: Copper Diffusion in Dielectric Films
EE311/ Saraswat/ Cu Interconnect8 tanford University
Copper Diffusion in Dielectric FilmsBias temperature stressing is employed to characterize behavior
• Both field and temperature affect barrier lifetime• Neutral Cu atoms and Cu ions contribute to Cu transport through dielectrics
Ref: A. Loke et al., Symp. VLSI Tech. 1998
Silicon nitride and oxynitride films are better barriers
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EE311/ Saraswat/ Cu Interconnect9 tanford University
• Fast diffusion of Cu into Si and SiO2• Poor oxidation/corrosion resistance• Poor adhesion to SiO2
Diffusion barrier /adhesion promotor Passivation
• Difficulty of applying conventional dry-etching technique
Damascene Process
Typical Damascene Process
Dielectrics
Barrier Layer
Cu
Solutions to Problems in CopperMetallization
EE311/ Saraswat/ Cu Interconnect10 tanford University
Barriers/Linears
Dielectric
Barrier/Linear
Metal
Via
Space for wire
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EE311/ Saraswat/ Cu Interconnect11 tanford University
Materials for Barriers / Liners• Transition metals (Pd, Cr, Ti, Co, Ni, Pt) generally poor barriers, due to high reactivities to
Cu <450˚C. Exception: Ta, Mo, W ... more thermally stable, but fail due to Cu diffusionthrough grain boundaries (polycrystalline films)
• Transition metal alloys: e.g., TiW. Can be deposited as amorphous films (stable up to500˚C)
• Transition metal - compounds: Extensively used, e.g., TiN, TaN, WN.
• Amorphous ternary alloys: Very stable due to high crystallization temperatures (i.e.,Ta36S14,N50, Ti34Si23N43)
• Currently PVD (sputtering/evaporation is used primarily to deposit the barrier/liner, however,step coverage is a problem. ALD is being developed for barrier/liner application.PVDALD
EE311/ Saraswat/ Cu Interconnect12 tanford University
Interconnect Fabrication Options
Metal
Etch
Positive
Pattern
Dielectric
Deposition
Dielectric
Planarization
by CMP
Negative
Pattern
Dielectric
Etch
Metal
Deposition
Metal CMP
Dielectric
Deposition
Metal
Dielectric
Photoresist
Etch Stop(Dielectric)
Subtractive Etch(Conventional Approach) Damascene
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EE311/ Saraswat/ Cu Interconnect13 tanford University
Cu Damascene Flow Options
Oxide
Copper
Conductive Barrier
Dielectric Etch Stop/Barrier
Single Damascene Dual Damascene
Barrier
& Cu
Dep
Cu Via
CMP
Nitride
+ Oxide
Dep
Lead
Pattern
& Etch
+
Barrier
& Cu
Dep
Via
Pattern
& Etch
Cu Lead
CMPLead
Via
Via &
Lead
Pattern
& Etch
Barrier
& Cu
Dep
Cu CMPLead
Via
Cu Damascene Flow Options
EE311/ Saraswat/ Cu Interconnect14 tanford University
Various deposition methods for Cu metallization has been attempted :
Physical vapor deposition (PVD) : Evaporation, Sputtering• conventional metal deposition technique: widely used for Al interconnects
• produce Cu films with strong (111) texture and smooth surface, in general
• poor step coverage: not tolerable for filling high-aspect ratio features
Deposition methods of Cu films: PVD
Deposited film
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EE311/ Saraswat/ Cu Interconnect15 tanford University
Deposition methods: CVD
EE311/ Saraswat/ Cu Interconnect16 tanford University
Various deposition methods for Cu metallization has been attempted : Physical vapor deposition (PVD) : Evaporation, Sputtering
• conventional metal deposition technique: widely used for Al interconnects• produce Cu films with strong (111) texture and smooth surface, in general• poor step coverage: not tolerable for filling high-aspect ratio features
Chemical vapor deposition (CVD)• conformal deposition with excellent step coverage in high-aspect ratio holes and vias• costly in processing and maintenance• generally produce Cu films with fine grain size, weak (111) texture and rough surface
Electrochemical deposition (EVD) Good step coverage and filling capability comparable to CVD process (0.25 µm) Compatible with low-K dielectrics Generally produce strong (111) texture of Cu film Produce much larger sized grain structure than any other deposition methods through self-annealing process
Why Cu Electroplating?:
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EE311/ Saraswat/ Cu Interconnect17 tanford University
Deposition methods: Electroplating
Dissociation : CuSO4 → Cu2+ + SO42- (solution)
Oxidation: Cu → Cu2++ 2e- (anode)Reduction : Cu2+ + 2e- → Cu (cathode, i.e., wafer)
Copper electroplating Chemistry :
Plating Bath : standard sulfuric acidcopper sulfate bath (H2SO4, CuSO4solution)
Additives to improve the film quality
EE311/ Saraswat/ Cu Interconnect18 tanford University
non-conformal"bottom-up filling"
("superfilling")
void
Trench Filling PVD vs. Electroplating of Cu
PVD Electroplating
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EE311/ Saraswat/ Cu Interconnect19 tanford University
Additives for Copper ECDDEFINITION
• Mixture of organic molecules and chloride ion which are adsorbed at thecopper surface during plating to:
-- enhance thickness distribution and feature fill
-- control copper grain structure and thus ductility, hardness, stress,and surface smoothness
COMPONENTS
• Most commercial mixtures use 3 or more organic components andchloride ion which adsorb at the cathode during plating.
Brighteners (Accelerators) Levelers Carriers Chloride Suppressors
EE311/ Saraswat/ Cu Interconnect20 tanford University
Wafers immersed in platingbath. Additives not yetadsorbed on Cu seed.
Additives adsorbed on Cuseed. No current flow.
Conformal plating begins.Accelerators accumulate atbottom of via, displacing lessstrongly absorbed additives.
Accumulation of acceleratordue to reduced surface area innarrow features, causes rapidgrowth at bottom of via.
t = 2 sec
t = 10 sec t = 20 sec
t = 0 sec= Accelerators= Suppressors
c = Chloride ionsL = Levelers
Mechanisms of Superconformal Cu plating
Ref: J. Reid et al., Solid St. Tech., 43, 86 (2000)D. Josell et al., J. Electrochem. Soc., 148, C767 (2001)
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EE311/ Saraswat/ Cu Interconnect21 tanford University
Brighteners (Accelerators)
• Adsorbs on copper metal during plating, participates in charge transfer reaction.Determines Cu growth characteristics with major impact on metallurgy
Levelers• Reduce growth rate of copper at protrusions and edges to yield a smooth final
deposit surface.
• Effectively increases polarization resistance at high growth areas by inhibitinggrowth to a degree proportional to mass transfer to localized sites
Carriers• Carriers adsorbed during copper plating to form a relatively thick monolayer film
at the cathode (wafer). Moderately polarizes Cu deposition by forming a barrierto diffusion of Cu2+ ions to the surface.
Chloride• Adsorbs at both cathode and anode.
• Accumulates in anode film and increases anode dissolution kinetics.
• Modifies adsorption properties of carrier to influence thickness distribution.
Role of Additives
EE311/ Saraswat/ Cu Interconnect22 tanford University
Effect of of the seed layer on theproperties of the final Cu
Seed Layer Texture
Seed Layer Surface Roughness
Plated Film TexturePlated Film Texture
Plated Film Grain Size
• Strong (111) texture • Smooth surface
• Strong (111) texture• Large grain size
Seed Layer Electroplated Film
(Thin, PVD seed preferred)
• Electroplating needs a seed layer of Cu as it does not occur at a dielectric surface.• Properties of the final Cu layer critically depend upon the characteristics of the seed layer.• The deposition of the seed layer can be done by PVD, CVD or ALD.• Currently PVD is preferred, CVD and ALD being investigated
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EE311/ Saraswat/ Cu Interconnect23 tanford University
Seed only 5 seconds 10 seconds 15 seconds 25 seconds
Plated Copper Fill Evolution
Ref: Jonathan Reid, IITC, 1999
EE311/ Saraswat/ Cu Interconnect24 tanford University
Trench Filling Capability of CuElectroplating
0.13µ trenches 0.18µ vias 029µ vias
Ref: Jonathan Reid, IITC, 1999
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EE311/ Saraswat/ Cu Interconnect25 tanford University
Grain Size Distribution Lognormal grain size distribution
electro- plating
0
0.02
0.04
0.06
0.08
0.1
0.01 0.1 1 10
annealedS = 2.682µmσ = 0.435
as-depositedS = 0.863µmσ = 0.716
electroless plating
0
0.02
0.04
0.06
0.08
0.1
0.01 0.1 1 10D (µm)
S = 0.150µmσ = 0.318
as-deposited
CVD
0
0.02
0.04
0.06
0.08
0.1
0.01 0.1 1 10D (µm)
as-deposited
annealed
S = 0.161µmσ = 0.372
S = 0.294µmσ = 0.344
(a)
(b)
(c)
D (µm)
Ref: H. Lee, PhD Thesis,Stanford Univ., 2002
Electroplated Cu givesbigger grain size
EE311/ Saraswat/ Cu Interconnect26 tanford University
Electroplated Cu has higher resistance to electromigrationbecause of its grain structure
Electromigration: CVD vs. Electroplating
CVD Cu
Electroplated Cu
104
105
106
107
1.8 1.9 2.0 2.1 2.2 2.3
Tim
e-t
o-F
ail
ure
(s
ec
)
1/T (10-3
/K)
213 °C238263
Electroplated CuE
a = 0.89 eV
CVD CuE
a = 0.82 eV
grain size
eµ
eµ
=1.4 µm
=0.3 µm
Ref: Ryu, et al., IEEE IRPS 1997.
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EE311/ Saraswat/ Cu Interconnect27 tanford University
• Empirical relationship (for Al & Al alloys)
Film Microstructure vs. EM Time-to-Failure
MTF !eµ
"2 log[
I(111)
I(200)
]3
103
104
105
106
107
1.8 1.9 2.0 2.1 2.2 2.3
Tim
e-t
o-F
ailure
(sec)
1/T (10-3
/K)
(111) CVD Cu
Ea = 0.86 eV
(200) CVD Cu
Ea = 0.81 eV
213238263 188°C
• EM dependence on the microstructure of Cu films
S. Vaidya et al., Thin Solid Films, Vol. 75, 253, 1981
Ref: Ryu, Loke, Nogami and Wong, IEEE IRPS 1997.
EE311/ Saraswat/ Cu Interconnect28 tanford University
Self-annealing at Room Temperaturet = 2 hrs
t = 60 days 1 µm
1 µm
Grains are initially small in all films but recrystallizationincreases their size
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0 10 20 30 40 50
gra
in s
ize
(µ
m)
DC plating current density (mA/cm2)
2 hrs
1 day
10 days
60 days
Ref: H. Lee, PhD Thesis, Stanford Univ., 2002
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EE311/ Saraswat/ Cu Interconnect29 tanford University
e
e
Surface scattering
Bulk scattering
Effect of Electron Scattering
•Reduced mobility as dimensions decrease
Grain boundary scattering
Surface scattering
•Reduced mobility as chip temperature increases
Increased phonon scattering
Thin Film Cu Resistivity
GrainGrain boundary
EE311/ Saraswat/ Cu Interconnect30 tanford University
W. Steinhögl et al., Phys. Rev. B66 (2002)
Cu Resistivity: Effect of Line Width Scaling
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EE311/ Saraswat/ Cu Interconnect31 tanford University
W. Steinhögl et al., Phys. Rev. B66 (2002)
Resistivity increases as grain size decreases due to increase in densityof grain boundaries which act as carrier scattering sites
Resistivity increases as main conductor size decreases due toincreased surface scattering
Cu Resistivity: Effect of Line Width ScalingModel
EE311/ Saraswat/ Cu Interconnect32 tanford University
Thin Film Cu Resistivity
Effect of Cu diffusion Barrier
• Barriers have higher resistivity
• Barriers can’t be scaled below a minimum thickness
• Consumes larger area as dimensions decrease
Resistivity of the composite wire is increased
Resistivity of metal wires could be much higher than bulk value
FutureCuBarrier
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EE311/ Saraswat/ Cu Interconnect33 tanford University
Cu Resistivity: Theoretical Background
Barrier Effect
Electron Surface Scattering Effect
w
h!
!b
o bA
AR w
=
"
1
12
*
• Important parameter: Ab to Aint ratio • ρb increase with Abto Aint ratio• Future: ratio may increase
AR=h/wAint=AR*w2
Cu
P: Fraction of electrons scattered elastically from the interfacek= d/ λmfpλmfp: Bulk mean free path for electronsd: Smallest dimension of the interconnect
Elastic scattering No Change in Mobility
Diffuse scattering Lower Mobility
P=0
P=1
• Reduced electron mobility• Operational temperature• Copper/barrier interface quality• Dimensions decrease in tiers: local, semiglobal, global
Barrier
Kapur, McVittie & Saraswat, IEEE Trans. Electron Dev. April 2002
!
"s"o
=1
1#3(1# P)$mfp
2d
1
X3#1
X5
% &
' ( 1# e#kX
1# Pe#kXdX
1
)
*
EE311/ Saraswat/ Cu Interconnect34 tanford University
Cu Resistivity: Effect of Barrier
IPVDC PVD ALDEffect of Barrier Technology
Cu barrier
• Barriers can’t be scaled and have high resistivity• Surface electron scattering increases resistivity• Real chips operate at higher temperatures
Technology node (µm)
Al P=0P=0.5P=1
Cu, P=0.5
0.18 0.15 0.12 0.1 0.07 0.05 0.035
PVDC-PVD
I-PVD
ALD: 10nm
ALD: 3nmALD: 1nm
No BarrierEffe
ctiv
e re
sist
ivity
(µ o
hm-c
m)
Year
Kapur and Saraswat, IEEE TED, April 2002
Effect of Scaling
Cubarrier
Global100°C
e
Al
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EE311/ Saraswat/ Cu Interconnect35 tanford University
Semi-global & Local Interconnects
Kapur, McVittie & Saraswat, IEEE Trans. Electron Dev . April 2002
Temp.=100 0C
Technology node (µm)
Al P=0P=0.5P=1
Cu, P=0.5
0.18 0.15 0.12 0.1 0.07 0.05 0.035
PVD C-PVD
ALD: 10nm
ALD: 3nmALD: 1nm
No Barrier
Local
Year
Effe
ctiv
e re
sist
ivity
(µ o
hm-c
m)
Local Temp.=100 0C
With ALD least resistivity rise Al resistivity rises slower than Cu. Cross over with Cu resistivity possible
– no 4 sided barrier– smaller λmfp => smaller k Al Cu
Technology node (µm)
Al P=0P=0.5P=1
Cu, P=0.5
0.18 0.15 0.12 0.1 0.07 0.05 0.035
PVDC-PVD
I-PVDALD: 10nm
ALD: 3nmALD: 1nm
No Barrier
Semiglobal Temp.=100 0C
EE311/ Saraswat/ Cu Interconnect36 tanford University
• Higher temperature ⇒ lower mobility ⇒ higher resistivity• Realistic Values at 35 nm node: P=0.5, temp=100 0C
- local ~ 5 µΩ-cm- semi-global ~ 4.2 µΩ-cm- global ~ 3.2 µΩ-cm
Cu Resistivity: Effect of Chip Temperature
2000 2004 2008 2012Year
0.18 0.12 0.07 0.05Technology Node (µm)
0.0353.6
3.2
2.4
1.6Effe
ctive
resis
tivity
( micr
oohm
-cm
)
2
2.8
T=100 0C
T=27 0C
GlobalKapur, McVittie & Saraswat IEEE Trans. Electron Dev . April 2002
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EE311/ Saraswat/ Cu Interconnect37 tanford University
Summary
•Interconnect scaling issues
•Thermal issues
•Electromigration
•Aluminum technology
•Copper technology