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ECE 156A 1
Overview of Design Methodology
Lecture 1
Put things into perspective
A Few Points Before We Start
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State-of-the-Art
• State-of-the-Art: The most advanced technology practiced in the industry today
• If state-of-the-art can be described in a textbook, then the industry is not advancing in a rapid speed (e.g. every two years there is something new)
• If the industry is advancing rapidly, we can’t expect textbook incorporates state-of-the-art
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Before we start …
• This course is an entry point to begin an understanding on how design is done in the real world
• Verilog is just a tool to start
• I hope to teach you more about what’s going on in the real world– But if your scope is focused on only exam
questions and HWs, you will find half of the lecture materials boring and useless
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All About Handling The “Complexity”
• Design and manufacturing of semiconductor products are very complex processes– Design methodologies– Manufacturing methodologies
• Good engineering means effective way to manage the “complexity”– Yet, complex problem usually doesn’t require complex
solution
• Today, it is no longer a secret to design a complex processor– “Better” means: faster, cheaper, lower-power, higher
quality, easier to use, etc.
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Three Types of Skill
• In the engineering world, there are three types of skill– Don’t have implementation skills -> marketing– Don’t have domain knowledge -> solving a wrong problem– Don’t have theoretical sense -> re-inventing the wheel
Implementationskills (programming)
Theoreticalsense
Applicationdomain
knowledgeExperience
Self-drive
Knowing the limits
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How to learn the three skills?• Implementation skill
– Basic constructs can be taught– Skill to implement cannot be taught– Depend on self motivation and learning
• Theoretical sense– Theories and concepts can be taught
• There are only a few useful ones– Application of theories and concepts cannot be taught
– It is based on experience
• Application domain knowledge– Facts and phenomenon can be described– Empirical judgments are hard to teach
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Lectures
• In addition to Verilog, I also talk about “application domain knowledge”
• Some that you can learn here are hard to get by self-study (and also most irrelevant to your grade)– Trends (facts and phenomenon)– Experience
• You can always learn more by self-studying– Use the Internet– Practice your Verilog skills– Read papers and other books
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Design Begins With Models and Simulation
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Design and manufacturing
• In a design process, people rely on modelsand simulation tools to construct a design– Keep in mind, in design we do NOT deal with the
real things. We only deal with models and simulations
• In a manufacturing process, the final design model is used to produce the real product
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The need for models
• You need to worry about two main things– Logical functionality– Electrical properties or characteristics– How to ensure those before manufacturing?
• How do we model a design … – So that we can simulate the design to check its
behavior (logical & electrical)?– So that we can be sure about its functionality and
properties before sending the design for manufacturing?
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First, Model for Functionality
• We need some sort of “formal model” to describe logical functionality– This formal model is understandable by some
software tools that can do some required analyses on the design
• To build a design model, you need to have a modeling language– A language to describe hardware functionality– This language is important because everything
else in the design process depends on it
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Keep this picture in mind
• Design idea needs to be translated into a formal representation
• The meaning of a representation is interpreted by the respective software
• The result needs to be checked to verify the idea is sound and valid
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FormalRepresentationIdea Interpretation
SoftwareCheck of
result
Hardware Description Language (HDL)
• HDL is just a modeling language for people to construct a formal representation (or model) to describe functionality of their designs
• Popular HDLs are Verilog and VHDL
• A HDL model is interpreted by a simulation tool for its behavior– ModelSIM
• The interpretation is as important as the language itself
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Hardware Description Languages (HDLs)
• Highly portable• Describe multiple levels of abstraction• Provide many descriptive styles
– Structural– Register Transfer Level (RTL)– Behavioral
• Serve as input to simulator & synthesis• Support structured design methodology
What is a design methodology
• A design methodology is like a flow chart– Each component in this flow chart is performing a
specific design task, such as logic synthesis
• A design methodology is determined by the Electronic Design Automation (EDA) software tools you purchased– And based on some in-house (software) tools
• In a design flow, you may have >50 such tasks to perform
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Fig 1-1 – Design Methodology
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• Typical design flow for an ASIC (Page 3)
Ask The Right Questions
• Why so many boxes?
• Why the existence of each box?
• Which are the most important boxes?
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HDL-based Design Flow Example• Create behavior
– The initial design model for functional simulation• Verify/simulate functionality• Pre-synthesis Signoff
• Synthesize into gate-level model– Eg. using Design Compiler
• Post-synthesis design validation– Compare gate-level mode and behavior model– Logic equivalence checking
• Fault Simulation and Test Generation– Design For Test (DFT)– Based on gate level model
• Post-synthesis Timing Verification– Eg. using PrimeTime, static timing analyzer
• Place & route (physical synthesis)• Verify physical and electrical design rules
– layout rules for manufacturability• Extract parasitics
– RC (L) extraction • Design sign-off
RTL Model
Gate Netlist Model
Layout Model
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From One Model To The Next
↓ Specification↓ HDL -- Behavior↓ HDL -- RTL↓ Netlist/schemati
cs --Gate level, switch level
↓ GDS II -- Layout↓ Geometries on
the die
behavior of nand4 isbegin process(a,b,c,d)beginz<=NOT(a AND b AND c AND d)end process
end architecture behavior
Verilog
Verilog
LEF/DEFGDSII
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HDL-based Design Flow Example• Create behavior
– The initial design model for functional simulation• Verify/simulate functionality• Pre-synthesis Signoff
• Synthesize into gate-level model– Eg. using Design Compiler
• Post-synthesis design validation– Compare gate-level mode and behavior model– Logic equivalence checking
• Fault Simulation and Test Generation– Design For Test (DFT)– Based on gate level model
• Post-synthesis Timing Verification– Eg. using PrimeTime, static timing analyzer
• Place & route (physical synthesis)• Verify physical and electrical design rules
– layout rules for manufacturability• Extract parasitics
– RC (L) extraction • Design sign-off
RTL Model
Gate Netlist Model
Layout Model
Design flow depends on style
• Not everyone follows the same flow– No exactly same flow for two companies
• Different design styles result in different flows
• An FPGA-style is very different from ASIC-style, and very different from processor-style
• Every design process is unique in some sense– Flow is proprietary to a company
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Design Styles• ASIC
– examples: controllers– typical characteristics
• low cost• slower speed• specific applications• short development time• older manufacturing technologies• mass market
– ASIC designs can be large in size• millions of transistors and more
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Processor Designs
• Designs that follow architectural SPECs– microprocessors, signal processors, etc.– Typical characteristics
• architectural specification• long development time• expensive• fixed market• high performance• state-of-the-art manufacture facilities
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Memory Designs
• On-chip / off-chip storage devices– video RAM, flash memory, etc.– high density– high performance– regular structure– special design methodology– special manufacture facilities– growing market
• Memory designs are crucial in many high-performance applications
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SOC (System on Chip)• Core-based design or IP design• Current hot market• New challenges in tools/methodologies• System-on-a-chip
VideoCore
AudioCore
MicrocontrollerCore
RAMASIC
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Design Styles• Considerations (Tradeoff)
– Performance (Power, Speed)– Area– Cost– Functionality– Time to Market
• Design approaches– Custom – design circuit by hand– Standard cell – use synthesis tool like Design Compiler– IP – purchase design from another company– FPGA – hardware simulation of your Verilog
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Examples
• For fastest time-to-market, rapid prototyping– Use FPGA
• For fast time-to-market, low cost ASIC– Use commercial standard EDA design flow– Make everything as automatic as possible
• For high-performance, high volume design– No high-performance and low volume (why?)– Use custom design flow, optimize in every step
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Post-Silicon
• For complex design, it is virtually impossible to do everything correct first time– Yield is usually low at 1st silicon
• Design effort continues into post-silicon stage– Fix design to improve yield– Develop an effective test methodology
• Top two concerns – Yield– Test Cost
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Yield and Test
• Yield = % of parts manufactured that are good
• Test = screening method to classify parts into good parts and bad parts
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TestParts
Good parts
Bad parts
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Post-Silicon
• For complex design, it is virtually impossible to do everything correct first time– Yield is usually low at 1st silicon
• Design effort continues into post-silicon stage– Fix design to improve yield– Develop an effective test methodology
• Top two concerns – Yield– Test Cost
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Design - Post-silicon stage• Before design - setup manufacture line
– Test chip, yield learning– Either done by foundry or before/during design stage
• After design sign-off, obtain silicon samples– Diagnosis of bugs/ Yield improvement– Silicon calibration/ On-chip repair– Determine mass-production test strategies
• Speed sorting method– System bring-up test– Performance validation– Re-spin
• After several re-spins, start mass production– Manufacturing test (for defects)– Performance sorting– System test– Reliability test (burn-in)– Ship to customers
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Post-production stage• Continuous yield improvement
– Identify common failure modes– Root causing– Generate fix(es)
• Test cost reduction– Identify redundant tests– Adapt test processes to save cost by removing
redundant tests
• Failure analysis– Obtain customer returns– Diagnosis and silicon debug (root causing)– Feedback to design (if worthy)
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Recall: HDL-based Design Flow• Create behavior
– The initial design model for functional simulation• Verify/simulate functionality• Pre-synthesis Signoff
• Synthesize into gate-level model– Eg. using Design Compiler
• Post-synthesis design validation– Compare gate-level mode and behavior model– Logic equivalence checking
• Fault Simulation and Test Generation– Design For Test (DFT)– Based on gate level model
• Post-synthesis Timing Verification– Eg. using PrimeTime, static timing analyzer
• Place & route (physical synthesis)• Verify physical and electrical design rules
– layout rules for manufacturability• Extract parasitics
– RC (L) extraction • Design sign-off
RTL Model
Gate Netlist Model
Layout Model
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Design Data Hierarchy
• Behavior– Like a C program
• RTL (Register Transfer Level)– Explicitly define all state-holding elements– Provide a cycle-accurate model
• Gate– All high-level constructs (if, case, assign) are
converted to gates (and, or, not).• Transistor
– All are converted with nmos, pmos, etc.• Layout (final picture)
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Purpose of Data Model
Behavior
RTL
Gate Level
Transistor/Layout
FunctionalSimulation
Synthesis/Simulation
Test GenerationDesign for Test;Timing Analysis
Physical PropertiesArea/Timing Optimization
=
=
=
Specification
Implementation
Less Complex
Very Complex
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Verification/Test Problems
↓ Specification↓ HDL -- Behavior↓ HDL -- RTL↓ Netlist/schemati
cs --Gate level, switch level
↓ GDS II -- Layout↓ Geometries on
the die
behavior of nand4 isbegin process(a,b,c,d)beginz<=NOT(a AND b AND c AND d)end process
end architecture behavior
=?
=?
=? Testing
Functional Verification
Logic Verification
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Verification Challenges• Functional Verification (with slow simulation)
– What functions do we need?– How do we know the design performs all functions we want?
• Equivalence Checking (with discrepancy in modeling perspective)– Specification = Implementation?
• Test Preparation (with unpredictable defects)– A chip is manufactured correctly?
• Performance Constraints (with inaccurate modeling)– Timing, power, noise are ok?
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Verification Perspective
• Functional verification is most time consuming• Timing and power validation cannot be 100% in the pre-
silicon phase due to model inaccuracy
ManufacturingChip!
LayoutTransistor-
LevelSchematic
DesignLibrary
Gate-LevelModel
RTLModel
BehaviorModel
ImplementationSpecification
Book
ArchitectureSpecification
Book
Concept!
Functional verification
Logic verification Validation of Timing, Power, etc.
synthesis
customdesign
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Quality Issues
• How do we know we have done a good job?– Never can be sure?– Can our customers find out?
• How do we know what it is going wrong?– Locate a design error or manufacturing defect– Analysis the cause– Go back and fix the design or the process– can be costly
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Do Everything Early• Because the later you have a problem, the higher
price it will cost you• However, the earlier the stage, the less accurate the
models are– Fundamental question: With a somewhat accurate but not
100% accurate model, how can you NOT over-doing it?
Costof finding a bug
Initial Design Chip System CustomerTime
# of bugs found
Design Challenges
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How difficult to do a design?• How big a HDL model can be?
– Millions of lines
• How long to simulate a design– Days, weeks
• How long to do a design– Months, years
• How do we know it is done– No body truly know
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No body truly knows?• Why?
– Because the design is too complex– No body has the power to know
• Also …– There is no need to know
• In the real world, you don’t need to be perfect to be successful– You need to be much better than all your
competitors
• In the real world, there is always someone else to solve the problems left by you
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How Complex?
• Over the years, the design industry follows this so-called “Moore’s Law”
• By advancing the technologies so fast, we are making chips today that are so complex
• The complexity of making chips is so high today that it can go beyond control soon if we don’t do something about it
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Moore’s law?• Gordon Moore, Intel co-founder (1968)
– Visit http://www.pbs.org/transistor/album1/moore/index.html
• Moore’s Law – rule of thumb in semiconductor industry (a reference for competition)– He said that the number of “components” on a
single silicon chip would double every 1.X year– Somebody says double every 1 year– Somebody says double every 1.5 years– Most recently, we say “double every 2 years
• Some people also say the “performance double every 1.x year”– In short, “industry should move fast!”
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Trend – Transistor Count
We are putting 1 billion transistor on a single chip!
Trend – Frequency (Speed)
We are stuck below 5 GHz
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Trend - Performance
MIPS: million instructions per secondTIPS: 1 million MIPS
Trend – Transistor Size
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Change in 10 yearsIntel® Pentium® Processor
350nm Technology
1995 - 133MHz, 3.3M transistors
Intel® Pentium® 4 Processor on 90nm Technology
2004 - 3.4GHz, 125M transistors
But, if we keep going like this …
We are going to have …
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Power Dissipation
Power Density
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Transistor – the basic building block
• Essentially, it is a switch– When voltage on GATE is high (above Vt), current
flows between SOURCE and DRAIN– When GATE voltage is low (below Vt), supposedly
no current flows between them
• But …
Experimental transistors …
Source: Intel
We need to do something to control the leakage power …
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Transistor is smaller …
Small devices leak current!
Sub-Threshold Leakage Current
• Why this is bad?– Current flow = Power dissipation– A transistor is sitting there doing
nothing and still consumes Power– One consequence: running out of
battery quickly
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Leakage power consumption
Power is a key limiter of Moore’s Law
3D Transistor – Year 2007
45nm productionImprove performanceLower off current flow
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High-k Dielectrics for leakage reduction
high-k dielectrics are defined as those with adielectric-constant greater than that of silicon nitrideThis is required for 32nm and below …
Power Wall
• While manufacturing guys are busy improving their process, ECE people are developing new designs and design methods
Power Wall
Need to turn!
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For example, multi-voltage design
• More power = faster• So, if we don’t need to run too fast in some part of
the chip, just give it lower voltage to save power– Is this also happening in the car industry as well?– We have seen more hybrid models because of the rising
gas price
• This has implications to many design methods
For example – multi-threading design
Multi-threading improves performance by better utilizing powerSo we can boost performance without increasing power
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The general idea – valued performance
The overall performance is what we really care aboutSo more processors together, multi-threading make better sense
In Summary• In the past 20 years, manufacturing
technology improved so fast– That we were busy building more and more
complex designs
• We didn’t actually have time to really think hard to optimize our design to better utilize the resource such as Power
• In these few years, people have started working on optimizing the designs– Continue to push for better performance– But not utilizing more power
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Two more walls• Process wall (variation, reliability)
– When transistors become so small, it is hard to control their behavior
– Transistor behavior (sizes) vary significantly
• Verification wall– We said we wanted to build more complex designs– Today’s microprocessors consists of millions of lines
of RTL codes– How do we know that our designs do not have a
bug?• We need to verify their correctness• Very tough task!!
Process variations
This is not new … it just that they are affecting our designs now …
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With-in die variation
Depending on where the transistors are located, their sizes differ
Did I mention Power density varies?
• Power is related to speed• Temperature is related to speed• Power is related to temperature• How do I know that my design can really run at
3GHz?– You need to consider all the uncertainties
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How do I know power density does vary?
Temperature variation
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Variations and Defects• In industry, people worry about “process”
“temperature” “voltage” (PVT) variations– We need to design our chips with these
variations in mind
• Not only that, the process uncertainties can cause many unintentional errors on the silicon– Manufacturing defects!
• We need to test our silicon to screen for any defect
• The bottom line is– You don’t ship a bad product out of the door!– Even though there are so many variations and
uncertainties
Modeling all defects is impossibleVoid under anchor Silicon damage
Metal2 extrusion/ILD2 crack Metal 1 Shelving
M4 Void FormationsM4-M4 Short Poly stringer
Too Many and Difficult to Predict when or how they will change
Credits: Greg Spirakis, Intel Corp. 7th European Test Workshop
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A Real Latent Defect Example
• SOC controller for automotive • Start to fail after driving 15000 miles• Show failure only under -40°C
– Failure is also frequency dependent• Determine to be a latent defect!
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Test equipment are expensive
S9000 tester, costs millions each
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Off-shore test facility – Intel
Test is complex and costs a lot!
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Verification
• Verification is to make sure that what you design is what your customer wants and expects
• How do you do it?– Simulate your design before you have it as real silicon
• It may cost you millions to do silicon so you better make sure nothing is wrong …
– Problem: Design is too complex and simulation is very “slow”
Whatyour
customerwant/expect
YourdesignSame?
Functional Verification Demand• Functional verification cost grows faster
than design complexity
100K 1M 10M
1M
100M
10B
(gates)
Simulation time
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Pre-Silicon functional verificationnot that we don’t try
0
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(Millions)
Pentium 4
Full-chip
~1/4 secof real time execution
Verification Crisis• More than 50% of the project
budget already goes to verification• Simulation and preparation time
already drags the time-to-market• Design complexity grows
tremendously with the use of multiple cores
• Cost of chip re-spin is high– > $100K for medium chips– > $1M or more for a complex designs
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In summary, we have 3 big walls
Power WallVa
riatio
n W
all
Verif
icat
ion
Wal
l
Future design
Some Questions to Think
• The three walls are just problems that manifest some fundamental problem(s) of how we do design– What is the fundamental problem?
• Will we see a fourth wall in the near future?
• What will be the key enabling technology to succeed five years from now?
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In Summary• We are hitting the verification wall
– The simulation time drags time-to-market– Don’t know if we have simulate enough
• We are hitting the power wall– Too many transistors on a single die– Leakage is serious for 65nm or below– Wireless applications require low power
• We are hitting the process (variation, reliability) wall– 22nm will be in mass product – Most people stays at 90 or 65nm– Analog world stays at .13 or higher– Process variations are too high for today’s design methods
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Cost Vs. Performance
• In the past 20 years, performance is the king to make big money
• Now, it is “cost” and “application”– Reduce design cost, improve turn-around time– Improve margin– Expand applications to sell more chips– Eg. Intel is driving for “total performance” on a
single chip (with n processors)
• The world has changed
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Design Art
• Design is a “constrained optimization” process– Optimize for your goals
• Timing, power, area, functionality, time to market
– Under some constraints• Constraints may not be well defined• Limited time, resources, expense, chip area, etc.
• Constrained optimization is to explore some tradeoff in the design space– Understanding the tradeoff is the key– The space may not be convex and hence, you may
have many local optimal but not global optimal points
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Jobs• Designs
– System level– Logic level– Circuit level– Verification and debug– DFT and test
• Tools– Methodologist– Tool Developer– Application Engineer
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Example - Design Companies• Processors (SoC)
– IBM, Intel, Freescale, TI, Qualcomm, SamSung, nVidia, Apple, AMD, ARM, Oracle, Broadcom, MediaTek, etc.
• Analog– Dialog, Qualcomm, TI, Freescale, etc.
• Memory– SamSung, Micron, etc.
• Embedded Cores– You can buy them from tool companies such as
Synopsys, Cadence Design Systems, etc.