Your Name: Grade: 106/100 ------------------------------------------------------------------------------------------------------------------------------------ ELE 444 Analog Integrated Circuits Fall '05 ________________________________________________________________________________________ Dr. M.G. Guvench TEST No.1 10/26/05 ________________________________________________________________________________________ Note 1. This is a closed books/notes examination. You may not use equations/formulas stored in electronic memory. Note 2. In all the questions/problems below take the process to be P-Well CMOS. Note 3. In all the questions/problems take the transistor to be N-Channel enhancement NMOS. 1. CMOS Process and Layout Design: (~35 pts) (42 pts) a. Draw the cross sectional view on the left side of the page and top view on the right of a CMOS inverter cell in P-

Well CMOS Technology (!). (12 +12 pts) Clearly show the mask patterns and their relative placements to each other. Use different colors to enhance different layers. Keep the NMOS transistor on the left side of your drawings as shown. Which device (NMOS or PMOS)should be larger in size to make the characteristics equal in magnitude? Why? (1 pt)

b. On the final step mark the length (L) and the width (W) of the resulting MOSFETs with arrows. (3 pts) c. If “Positive” photoresist is being used throughout the process redraw your ACTIVE CONTACT and METAL1

mask patterns and cross hatch the areas that need to be opaque (dark) on the mask. (4 pts) d. Design a P-Well Resistor which will have R=50 Kohms (take well sheet resistance to be 2500 ohms/square. Draw the cross sectional and top

views of it . (10 pts)

CMOS INVERTER CROSS SECTION TOP VIEW NMOS PMOS NMOS PMOS

See attached pages for answers.

PMOS is made larger (by about 2/1 ratio) to compensate for the smaller hole mobilityin PMOS than the electron

mobility in NMOS.

CMOS P-Well RESISTOR Designed

CROSS SECTION TOP VIEW

3. CMOS Inverting Amplifier Design/Analysis: ~(41 pts)

VDD=5VDC, KP(PMOS)= 4 uA/V2, KP(NMOS)= 10 uA/V2 , VTN = -VTP = 1V, λN = 0.01 λP = 0.02 3.a Draw the circuit diagram of a CMOS (NMOS+PMOS Mirror Load) inverter/amplifier which drives a

capacitive load of 2 pF. Draw its DC transfer chs and mark the values of its important points and identify the modes of operation of its transistors. Where would you bias it for the highest small signal amplification?

a. CMOS Inverter Circuit (NMOS+PMOS Mirror) (4 pts)

b. CMOS Inverter Circuit (NMOS+PMOS Mirror) Layout (TOP VIEW) (10 pts)

c. Plot, DC Voltage Transfer (Vout-Vin) Chs. (6 pts) ID and Supply Current vs Input Voltage (Vin): (3 pts)

For the highest gain the transistors should both operate in Saturation as shown above on the Vout-Vin chs. d. Small-signal AC Equivalent Circuit and simplified form of it: (3 pts)

Design: e. Calculate Av, the small-signal gain (derive the formulas, not numerical calculations, yet) and, Rout and Bandwidth (7 pts)

f. Design the amplifier for a s.s. gain of 20 and GBW of 1MHz. Specify the operating current and the W/L ratio(s) of all transistor(s) in the circuit. Try (if possible) to pick transistors' sizes same order of magnitude as the driver NMOS. (8 pts)