P89LPC9102/9103/9107 8-bit microcontrollers with two-clock ... · The P89LPC9102/9103/9107 are...

1. General description

The P89LPC9102/9103/9107 are single-chip microcontrollers in low-cost 10-pin and14-pin packages based on a high performance processor architecture that executesinstructions in two to four clocks, six times the rate of standard 80C51 devices. Manysystem-level functions have been incorporated into the P89LPC9102/9103/9107 in orderto reduce component count, board space, and system cost.

2. Features

2.1 Principal featuresn 1 kB byte-erasable flash code memory organized into 256-byte sectors and 16-byte

pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.

n 128-byte RAM data memory.

n Two 16-bit timer/counters (P89LPC9102/9107). Two 16-bit timers (P89LPC9103)

n 23-bit system timer that can also be used as a RTC.

n Four input multiplexed 8-bit A/D converter/single DAC output. One analog comparatorwith selectable reference.

n Enhanced UART with fractional baud rate generator, break detect, framing errordetection, automatic address detection and versatile interrupt capabilities(P89LPC9103/9107).

n High-accuracy internal RC oscillator option, factory calibrated to 1 %, allows operationwithout external oscillator components. The RC oscillator option is selectable and finetunable.

n VDD operating range of 2.4 V to 3.6 V with 5 V tolerant I/O pins (may be pulled up ordriven to 5.5 V).

n Up to 10 (P89LPC9107) or eight (P89LPC9102/9103) I/O pins when using internaloscillator and reset options.

n Ultra-small 10-pin HVSON package (P89LPC9102/9103). 14-pin TSSOP and DIPpackages (P89LPC9107).

2.2 Additional featuresn A high performance 80C51 CPU provides instruction cycle times of 136 ns to 272 ns

for all instructions except multiply and divide when using the internal 7.3728 MHz RCoscillator in clock doubling mode (111 ns to 222 ns when using an external 18 MHzclock). A lower clock frequency for the same performance results in power savings andreduced EMI.

P89LPC9102/9103/91078-bit microcontrollers with two-clock accelerated 80C51 core1 kB 3 V byte-erasable flash with 8-bit A/D converterRev. 03 — 10 July 2007 Product data sheet

NXP Semiconductors P89LPC9102/9103/91078-bit microcontrollers with two-clock accelerated 80C51 core

n In-Application Programming (IAP-Lite) and byte erase allows code memory to be usedfor non-volatile data storage.

n Serial flash ICP allows simple production coding with commercial EPROMprogrammers. Flash security bits prevent reading of sensitive application programs.

n Watchdog timer with separate on-chip oscillator, requiring no external components.The watchdog prescaler is selectable from eight values.

n Low voltage reset (Brownout detect) allows a graceful system shutdown when powerfails. May optionally be configured as an interrupt.

n Idle mode and two different reduced power Power-down modes. Improved wake-upfrom Power-down mode (a LOW interrupt input starts execution). Typical Power-downmode current is less than 1 µA (total Power-down mode with voltage comparatorsdisabled).

n Active-LOW reset. On-chip power-on reset allows operation without external resetcomponents. A reset counter and reset glitch suppression circuitry prevent spuriousand incomplete resets. A software reset function is also available.

n Programmable port output configuration options: quasi-bidirectional, open drain,push-pull, input-only.

n Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value ofthe pins match or do not match a programmable pattern.

n LED drive capability (20 mA) on all port pins. A maximum limit is specified for theentire chip.

n Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 nsminimum ramp times.

n Only power and ground connections are required to operate theP89LPC9102/9103/9107 when internal reset option is selected.

n Four interrupt priority levels.

n Two keypad interrupt inputs.

n Second data pointer.

n External clock input.

n Clock output (P89LPC9102/9107).

n Schmitt trigger port inputs.

n Emulation support.

3. Product comparison overview

Table 1 highlights the differences between these two devices. For a complete list of devicefeatures, please see Section 2 “Features”.

Table 1. Product comparison overview

Type number UART T0 toggle/PWM T1 toggle/PWM CLKOUT

P89LPC9102 - X X X

P89LPC9103 X - - -

P89LPC9107 X X X X

P89LPC9102_9103_9107_3 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 03 — 10 July 2007 2 of 61


4. Ordering information

4.1 Ordering options

Table 2. Ordering information

Type number Package

Name Description Version

P89LPC9102FTK HVSON10 plastic thermal enhanced very thin small outline package; no leads;10 terminals; body 3 × 3 × 0.85 mm

SOT650-1

P89LPC9103FTK

P89LPC9107FDH TSSOP14 plastic thin shrink small outline package; 14 leads; body width4.4 mm

SOT402-1

P89LPC9107FN DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

Table 3. Ordering options

Type number Temperature range Frequency

P89LPC9102FTK −40 °C to +85 °C internal RC or watchdogtimerP89LPC9103FTK

P89LPC9107FDH

P89LPC9107FN




5. Block diagram

Fig 1. Block diagram of P89LPC9102

ACCELERATED 2-CLOCK 80C51 CPU

1 kB FLASH

PORT 1CONFIGURABLE I/Os


KEYPADINTERRUPT

PROGRAMMABLEOSCILLATOR DIVIDER

CPU clock

CONFIGURABLEOSCILLATOR

ON-CHIP RC OSCILLATOR

WITH CLOCKDOUBLER OPTION

internalbus

POWER MONITOR(POWER-ON RESET, BROWNOUT RESET)

002aaa967

128 BYTERAM

ANALOGCOMPARATORS

ADC1/DAC1

P89LPC9102

WATCHDOG TIMERAND OSCILLATOR

REAL-TIME CLOCK/SYSTEM TIMER

TIMER 0TIMER 1

CLKOUT

CLKIN

P1.2, P1.5

P0[1:5], P0.7

KBI1

AD10AD11AD12

DAC1

T0

T1

CIN1A

CIN1B

AD13

KBI2






1 kB FLASH



KEYPADINTERRUPT


CPUclock


internalbus


002aaa968

UART

ANALOGCOMPARATORS

ADC1/DAC1

P89LPC9103



TIMER 0TIMER 1

128 BYTERAM

CLKINON-CHIP

RC OSCILLATORWITH CLOCK

DOUBLER OPTION

P1.0, P1.1, P1.5

P0[1:5]

KBI1

TXD

RXD

CIN1A

CIN1B

KBI2

AD10AD11AD12

DAC1AD13




6. Functional diagram



1 kB FLASH



KEYPADINTERRUPT


CPUclock


internal bus


002aab100

UART

ANALOGCOMPARATORS

ADC1/DAC1

P89LPC9107



TIMER 0TIMER 1

128 BYTERAM

CLKIN

CLKOUT ON-CHIP RC OSCILLATOR

WITH CLOCKDOUBLER OPTION

P1[0:2], P1.5

P0[1:5], P0.7

KBI1

AD10

TXD

RXD

AD11AD12

DAC1

CIN1A

CIN1B

T0

T1

AD13

KBI2

Fig 4. Functional diagram of P89LPC9102

VDD VSS

PORT 0

T0RST

002aaa971

CIN1ACMPREF

CIN1B

AD13CLKINAD11AD12AD10

CLKOUT

DAC1

KBI2

KBI1T1

PORT 1

P89LPC9102






VDD VSS

PORT 0RXDRST

002aaa972

CIN1ACMPREF

CIN1B


DAC1

KBI2

KBI1

PORT 1TXD

P89LPC9103

VDD VSS

PORT 0

RXDRST

002aab084

CIN1ACMPREF

CIN1B


DAC1

KBI2

KBI1CLKOUT T1

PORT 1TXDT0P89LPC9107




7. Pinning information

7.1 Pinning

Fig 7. P89LPC9102 pinning (HVSON10)

Fig 8. P89LPC9103 pinning (HVSON10)

Fig 9. P89LPC9107 pinning (TSSOP14)

002aaa969

LPC9102

P0.7/T1/CLKOUTP1.2/T0

VDD

VSS P0.5/CMPREF/CLKIN

P0.4/CIN1A/AD13/DAC1

P0.2/KBI2/AD11 P0.3/CIN1B/AD12

Transparent top view

5 6

4 7

3 8

2 9

1 10

terminal 1index area

P1.5/RST

P0.1/KBI1/AD10

002aaa970

LPC9103

P1.1/RXD

P0.1/KBI1/AD10

P1.0/TXD

VDD


P1.5/RST P0.4/CIN1A/AD13/DAC1


Transparent top view

5 6

4 7

3 8

2 9

1 10


LPC9107


n.c. n.c.

P1.5/RST P0.4/CIN1A/AD13/DAC1


P0.1/KBI1/AD10 VDD

P1.0/TXD P1.1/RXD

P1.2/T0 P0.7/T1/CLKOUT

002aab083

1

2

3

4

5

6

7 8

10

9

12

11

14

13




Fig 10. P89LPC9107 pinning (DIP14)

LPC9107

P0.2/KBI2/AD11

n.c.

002aac987

1

2

3

4

5

6

7 8

10

9

12

11

14

13

P1.5/RST

VSS

P0.1/KBI1/AD10

P1.0/TXD

P1.2/T0

P0.3/CIN1B/AD12

n.c.


P0.5/CMPREF/CLKIN

VDD

P1.1/RXD

P0.7/T1/CLKOUT




7.2 Pin description

Table 4. P89LPC9102 pin description

Symbol Pin Type Description

P0.1 to P0.5,P0.7

I/O Port 0: Port 0 is an I/O port with a user-configurable output type. During reset Port 0latches are configured in the input-only mode with the internal pull-up disabled. Theoperation of Port 0 pins as inputs and outputs depends upon the port configurationselected. Each port pin is configured independently. Refer to Section 8.12.1 “Portconfigurations” and Table 12 “Static characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

P0.1/KBI1/AD10

4 I/O P0.1 — Port 0 bit 1.

I KBI1 — Keyboard input 1.

I AD10 — ADC1 channel 0 analog input.

P0.2/KBI2/AD11

1 I/O P0.2 — Port 0 bit 2.



P0.3/CIN1B/AD12

10 I/O P0.3 — Port 0 bit 3.

I CIN1B — Comparator 1 positive input.



9 I/O P0.4 — Port 0 bit 4.

I CIN1A — Comparator 1 positive input.


O DAC1 — Digital to analog converter output.

P0.5/CMPREF/CLKIN

8 I/O P0.5 — Port 0 bit 5.

I CMPREF — Comparator reference (negative) input.

I CLKIN — External clock input.

P0.7/T1/CLKOUT

6 I/O P0.7 — Port 0 bit 7.

I/O T1 — Timer/counter 1 external count input or overflow/PWM output.

I CLKOUT — Clock output.

P1.2, P1.5 I/O Port 1: Port 1 is an I/O port with a user-configurable output type. During reset Port 1latches are configured in the input-only mode with the internal pull-up disabled. Theoperation of the configurable Port 1 pins as inputs and outputs depends upon theport configuration selected. Each of the configurable port pins are programmedindependently. Refer to Section 8.12.1 “Port configurations” and Table 12 “Staticcharacteristics” for details. P1.5 is input-only.



P1.2/T0 5 I/O P1.2 — Port 1 bit 2.





P1.5/RST 2 I P1.5 — Port 1 bit 5 (input-only).

I RST — External Reset input during power-on or if selected via User ConfigurationRegister 1 (UCFG1). When functioning as a reset input a LOW on this pin resets themicrocontroller, causing I/O ports and peripherals to take on their default states, andthe processor begins execution at address 0. When using an oscillator frequencyabove 12 MHz, the reset input function of P1.5 must be enabled. An externalcircuit is required to hold the device in reset at power-up until V DD has reachedits specified level. When system power is removed V DD will fall below theminimum specified operating voltage. When using an oscillator frequencyabove 12 MHz, in some applications, an external brownout detect circuit maybe required to hold the device in reset when V DD falls below the minimumspecified operating voltage.

VSS 3 I Ground: 0 V reference.

VDD 7 I Power supply: This is the power supply voltage for normal operation as well as Idlemode and Power-down mode.

Table 4. P89LPC9102 pin description …continued







P0.1 to P0.5 I/O Port 0: Port 0 is an I/O port with a user-configurable output type. During reset Port 0latches are configured in the input-only mode with the internal pull-up disabled. Theoperation of Port 0 pins as inputs and outputs depends upon the port configurationselected. Each port pin is configured independently. Refer to Section 8.12.1 “Portconfigurations” and Table 12 “Static characteristics” for details.




P0.1/KBI1/AD10

4 I/O P0.1 — Port 0 bit 1.



P0.2/KBI2/AD11

1 I/O P0.2 — Port 0 bit 2.



P0.3/CIN1B/AD12

10 I/O P0.3 — Port 0 bit 3.




9 I/O P0.4 — Port 0 bit 4.




P0.5/CMPREF/CLKIN

6 I/O P0.5 — Port 0 bit 5.



P1.0 to P1.5 I/O Port 1: Port 1 is an I/O port with a user-configurable output type. During reset Port 1latches are configured in the input-only mode with the internal pull-up disabled. Theoperation of the configurable Port 1 pins as inputs and outputs depends upon the portconfiguration selected. Each of the configurable port pins are programmedindependently. Refer to Section 8.12.1 “Port configurations” and Table 12 “Staticcharacteristics” for details. P1.5 is input-only.



P1.0/TXD 5 I/O P1.0 — Port 1 bit 0.

O TXD — Serial port transmitter data.

P1.1/RXD 6 I/O P1.1 — Port 1 bit 1.

I RXD — Serial port receiver data.





I RST — External Reset input during Power-on or if selected via UCFG1. Whenfunctioning as a reset input a LOW on this pin resets the microcontroller, causing I/Oports and peripherals to take on their default states, and the processor beginsexecution at address 0. When using an oscillator frequency above 12 MHz, thereset input function of P1.5 must be enabled. An external circuit is required tohold the device in reset at power-up until V DD has reached its specified level.When system power is removed V DD will fall below the minimum specifiedoperating voltage. When using an oscillator frequency above 12 MHz, in someapplications, an external brownout detect circuit may be required to hold thedevice in reset when V DD falls below the minimum specified operating voltage.







P0.1 to P0.5,P0.7

I/O Port 0: Port 0 is an I/O port with a user-configurable output type. During reset Port 0latches are configured in the input-only mode with the internal pull-up disabled. Theoperation of Port 0 pins as inputs and outputs depends upon the port configurationselected. Each port pin is configured independently. Refer to Section 8.12.1 “Portconfigurations” and Table 12 “Static characteristics” for details.




P0.1/KBI1/AD10

5 I/O P0.1 — Port 0 bit 1.



P0.2/KBI2/AD11

1 I/O P0.2 — Port 0 bit 2.



P0.3/CIN1B/AD12

14 I/O P0.3 — Port 0 bit 3.




12 I/O P0.4 — Port 0 bit 4.




P0.5/CMPREF/CLKIN

11 I/O P0.5 — Port 0 bit 5.



P0.7/T1/CLKOUT

8 I/O P0.7 — Port 0 bit 7.


I CLKOUT — Clock output.




P1.0 to P1.2,P1.5

I/O Port 1: Port 1 is an I/O port with a user-configurable output type. During reset Port 1latches are configured in the input-only mode with the internal pull-up disabled. Theoperation of the configurable Port 1 pins as inputs and outputs depends upon the portconfiguration selected. Each of the configurable port pins are programmedindependently. Refer to Section 8.12.1 “Port configurations” and Table 12 “Staticcharacteristics” for details. P1.5 is input-only.



P1.0/TXD 6 I/O P1.0 — Port 1 bit 0.

O TXD — Serial port transmitter data.

P1.1/RXD 9 I/O P1.1 — Port 1 bit 1.

I RXD — Serial port receiver data.

P1.2/T0 7 I/O P1.2 — Port 1 bit 2.



I RST — External Reset input during Power-on or if selected via UCFG1. Whenfunctioning as a reset input a LOW on this pin resets the microcontroller, causing I/Oports and peripherals to take on their default states, and the processor beginsexecution at address 0. When using an oscillator frequency above 12 MHz, thereset input function of P1.5 must be enabled. An external circuit is required tohold the device in reset at power-up until V DD has reached its specified level.When system power is removed V DD will fall below the minimum specifiedoperating voltage. When using an oscillator frequency above 12 MHz, in someapplications, an external brownout detect circuit may be required to hold thedevice in reset when V DD falls below the minimum specified operating voltage.








8. Functional description

Remark: Please refer to the P89LPC9102/9103/9107 User manual UM10112 for a moredetailed functional description.

8.1 Special function registersRemark: Special Function Registers (SFRs) accesses are restricted in the followingways:

• User must not attempt to access any SFR locations not defined.

• Accesses to any defined SFR locations must be strictly for the functions for the SFRs.

• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any valuewhen read (even if it was written with ‘0’). It is a reserved bit and may be used infuture derivatives.

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.

– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.



xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

P89LP

C9102_9103_9107_3

Product data shee

NX

P S

emiconductors

P89LP

C9102/9103/9107

8-bit microcontrollers w

ith two-clock accelerated 80C

51 core

Table 7. P89LPC9102 special function registers* indicates SFRs that are bit addressable.

Name Description SFRaddr.

Bit functions and addresses Reset value

MSB LSB Hex Binary

E1 E0

00 0000 0000

ADCS11 ADCS10 00 0000 0000

- - 00 0000 0000

- - 00 0000 0000

BSA1 - 00 000x 0000

FF 1111 1111

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

- DPS 00[1] 0000 00x0

F1 F0

00 0000 0000

CO1 CMF1 00 xx00 0000

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

SV OI 70 0111 0000

FMCMD.1

FMCMD.0

00 0000 0000

ET0 - 00[1] 0000 0000

© N

XP

B.V. 2007. A

ll rights reserved.

tR

ev. 03 — 10 July 2007

16 of 61

Bit address E7 E6 E5 E4 E3 E2

ACC* Accumulator E0H

ADCON1 A/D control register 1 97H ENBI1 ENADCI1

TMM1 - ADCI1 ENADC1

ADINS A/D input select A3H AD13 AD12 AD11 AD10 - -

ADMODA A/D mode register A C0H BNDI1 BURST1 SCC1 SCAN1 - -

ADMODB A/D mode register B A1H CLK2 CLK1 CLK0 - ENDAC1 -

AD1BH A/D_1 boundary high register C4H

AD1BL A/D_1 boundary low register BCH

AD1DAT0 A/D_1 data register 0 D5H



AD1DAT3 A/D_1 data register 3 F5H

AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENT0 SRST 0

Bit address F7 F6 F5 F4 F3 F2

B* B register F0H

CMP1 Comparator 1 control register ACH - - CE1 CP1 CN1 -

DIVM CPU clock divide-by-Mcontrol

95H

DPTR Data pointer (2 bytes)

DPH Data pointer high 83H

DPL Data pointer low 82H

FMADRH Program flash address high E7H

FMADRL Program flash address low E6H

FMCON Program flash Control (Read) E4H BUSY - - - HVA HVE

Program flash Control (Write) FMCMD.7

FMCMD.6

FMCMD.5

FMCMD.4

FMCMD.3

FMCMD.2

FMDATA Program flash data E5H

IEN0* Interrupt enable 0 A8H EA EWDRT EBO - ET1 -


P89LP

C9102_9103_9107_3

Product data shee

NX

P S

emiconductors

P89LP

C9102/9103/9107



51 core

E9 E8

EKBI - 00[1] 00x0 0000

B9 B8

PT0 - 00[1] x000 0000

PT0H - 00[1] x000 0000

F9 F8

PKBI - 00[1] 00x0 0000

PKBIH - 00[1] 00x0 0000

PATN_SEL

KBIF 00[1] xxxx xx00

- - 00 xxxx x00x

- - FF xxxx x11x

81 80

KBI1 - [2]

91 90

- -

(P0M1.1) - FF 1111 1111

(P0M2.1) - 00 0000 0000

- - FF[1] 1111 1111

- - 00[1] 0000 0000

PMOD1 PMOD0 00 0000 0000

- 00[1] 0000 0000

- - 00[1] xxxx xxxx

D1 D0

F1 P 00 0000 0000

PT0AD.1 - 00 xx00 000x

Table 7. P89LPC9102 special function registers …continued* indicates SFRs that are bit addressable.



MSB LSB Hex Binary

© N

XP

B.V. 2007. A

ll rights reserved.

tR

ev. 03 — 10 July 2007

17 of 61

Bit address EF EE ED EC EB EA

IEN1* Interrupt enable 1 E8H EAD - - - - EC

Bit address BF BE BD BC BB BA

IP0* Interrupt priority 0 B8H - PWDRT PBO - PT1 -

IP0H Interrupt priority 0 high B7H - PWDRTH

PBOH - PT1H -

Bit address FF FE FD FC FB FA

IP1* Interrupt priority 1 F8H PAD - - - - PC

IP1H Interrupt priority 1 high F7H PADH - - - - PCH

KBCON Keypad control register 94H - - - - - -

KBMASK Keypad interrupt maskregister

86H - - - KBMASK.2

KBMASK.1

KBPATN Keypad pattern register 93H - - - - KBPATN.2

KBPATN.1

Bit address 87 86 85 84 83 82

P0* Port 0 80H CLKOUT/T1

- CMPREF/CLKIN

CIN1A CIN1B CIN2A/KBI2

Bit address 97 96 95 94 93 92

P1* Port 1 90H - - RST - - T0

P0M1 Port 0 output mode 1 84H (P0M1.7) - (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2)

P0M2 Port 0 output mode 2 85H (P0M2.7) - (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2)

P1M1 Port 1 output mode 1 91H - - - - - (P1M1.2)

P1M2 Port 1 output mode 2 92H - - - - - (P1M2.2)

PCON Power control register 87H - - BOPD BOI GF1 GF0

PCONA Power control register A B5H RTCPD VCPD ADPD -

PCONB reserved for Power controlregister B

B6H - - - - - -

Bit address D7 D6 D5 D4 D3 D2

PSW* Program status word D0H CY AC F0 RS1 RS0 OV

PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2


P89LP

C9102_9103_9107_3

Product data shee

NX

P S

emiconductors

P89LP

C9102/9103/9107



51 core

ese bits since they may be used for other

ared except POF and BOF; the power-on reset

TRIM register.

tchdog timer reset and is logic 0 after power-on

R_SF R_EX [3]

ERTC RTCEN 60[4] 011x xx00

00[4] 0000 0000

00[4] 0000 0000

07 0000 0111

- T0M2 00 xxx0 xxx0

89 88

- - 00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

T0M1 T0M0 00 0000 0000

TRIM.1 TRIM.0 [4][5]

WDTOF WDCLK [4][6]

FF 1111 1111




MSB LSB Hex Binary

© N

XP

B.V. 2007. A

ll rights reserved.

tR

ev. 03 — 10 July 2007

18 of 61

[1] Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to thpurposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read.

[2] All ports are in input-only (high-impedance) state after power-up.

[3] The RSTSRC register reflects the cause of the P89LPC9102/9103/9107 reset. Upon a power-up reset, all reset source flags are clevalue is xx11 0000.

[4] The only reset source that affects these SFRs is power-on reset.

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the

[6] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1s, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after wareset. Other resets will not affect WDTOF.

RSTSRC Reset source register DFH - - BOF POF - R_WD

RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - -

RTCH Real-time clock register high D2H

RTCL Real-time clock register low D3H

SP Stack pointer 81H

TAMOD Timer 0 and 1 auxiliary mode 8FH - - - T1M2 - -

Bit address 8F 8E 8D 8C 8B 8A

TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 - -

TH0 Timer 0 high 8CH

TH1 Timer 1 high 8DH

TL0 Timer 0 low 8AH

TL1 Timer 1 low 8BH

TMOD Timer 0 and 1 mode 89H - - T1M1 T1M0 - -

TRIM Internal oscillator trim register 96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2

WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN

WDL Watchdog load C1H

WFEED1 Watchdog feed 1 C2H



P89LP

C9102_9103_9107_3

Product data shee

NX

P S

emiconductors

P89LP

C9102/9103/9107



51 core




MSB LSB Hex Binary

E1 E0

00 0000 0000

ADCS11 ADCS10 00 0000 0000

- - 00 0000 0000

- - 00 0000 0000

BSA1 - 00 000x 0000

FF 1111 1111

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

- DPS 00[1] 0000 00x0

F1 F0

00 0000 0000

00 0000 0000

00 0000 0000

SBRGS BRGEN 00[2] xxxx xx00

CO1 CMF1 00[1] xx00 0000

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

SV OI 70 0111 0000

FMCMD.1

FMCMD.0

© N

XP

B.V. 2007. A

ll rights reserved.

tR

ev. 03 — 10 July 2007

19 of 61




TMM1 - ADCI1 ENADC1










AUXR1 Auxiliary function register A2H CLKLP EBRR - - SRST 0


B* B register F0H

BRGR0[2] Baud rate generator rate low BEH

BRGR1[2] Baud rate generator rate high BFH

BRGCON Baud rate generator control BDH - - - - - -



95H








FMCMD.6

FMCMD.5

FMCMD.4

FMCMD.3

FMCMD.2


P89LP

C9102_9103_9107_3

Product data shee

NX

P S

emiconductors

P89LP

C9102/9103/9107



51 core

00 0000 0000

ET0 - 00 0000 0000

E9 E8

EKBI - 00[1] 00x0 0000

B9 B8

PT0 - 00[1] x000 0000

PT0H - 00[1] x000 0000

F9 F8

PKBI - 00[1] 00x0 0000

PKBIH - 00[1] 00x0 0000

PATN_SEL


KBMASK.1

- 00 xxxx x00x

KBPATN.1

- FF xxxx x11x

81 80

KBI1 - [3]

91 90

RXD TXD

(P0M1.1) - FF 1111 1111

(P0M2.1) - 00 0000 0000

(P1M1.1) (P1M1.0) FF[1] 1111 1111

(P1M2.1) (P1M2.0) 00[1] 0000 0000

PMOD1 PMOD0 00 0000 0000

SPD 00[1] 0000 0000

- - 00[1] xxxx xxxx




MSB LSB Hex Binary

© N

XP

B.V. 2007. A

ll rights reserved.

tR

ev. 03 — 10 July 2007

20 of 61


IEN0* Interrupt enable 0 A8H EA EWDRT EBO ES/ESR ET1 -


IEN1* Interrupt enable 1 E8H EAD EST - - - EC


IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 -


PBOH PSH/PSRH

PT1H -


IP1* Interrupt priority 1 F8H PAD PST - - - PC

IP1H Interrupt priority 1 high F7H PADH PSTH - - - PCH



86H - - - - KBMASK.2

KBPATN Keypad pattern register 93H - - - - - KBPATN.2

Bit address 87 86 85 84 83 82

P0* Port 0 80H - - CMPREF/CLKIN

CIN1A CIN1B KBI2

Bit address 97 96 95 94 93 92

P1* Port 1 90H - - RST - - -

P0M1 Port 0 output mode 1 84H - - (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2)


P1M1 Port 1 output mode 1 91H - - - - - -


PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0



B6H - - - - - -


P89LP

C9102_9103_9107_3

Product data shee

NX

P S

emiconductors

P89LP

C9102/9103/9107



51 coreese bits since they may be used for other

npredictable.

D1 D0

F1 P 00 0000 0000

PT0AD.1 - 00 xx00 000x

R_SF R_EX [4]


00[5] 0000 0000

00[5] 0000 0000

00 0000 0000

00 0000 0000

xx xxxx xxxx

99 98

TI RI 00 0000 0000

OE STINT 00 0000 0000

07 0000 0111

89 88

- - 00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

T0M1 T0M0 00 0000 0000


WDTOF WDCLK [5][7]

FF 1111 1111




MSB LSB Hex Binary

© N

XP

B.V. 2007. A

ll rights reserved.

tR

ev. 03 — 10 July 2007

21 of 61


[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is u




RSTSRC Reset source register DFH - - BOF POF R_BK R_WD




SADDR Serial port address register A9H

SADEN Serial port address enable B9H

SBUF Serial port data buffer register 99H


SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8

SSTAT Serial port extended statusregister

BAH DBMOD INTLO CIDIS DBISEL FE BR






TL0 Timer 0 low 8AH

TL1 Timer 1 low 8BH


TRIM Internal oscillator trim register 96H RCCLK - TRIM.5 TRIM.4 TRIM.3 TRIM.2






P89LP

C9102_9103_9107_3

Product data shee

NX

P S

emiconductors

P89LP

C9102/9103/9107



51 core


[4] The RSTSRC register reflects the cause of the P89LPC9102/9103/9107 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on resetvalue is xx11 0000.


[6] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.


© N

XP

B.V. 2007. A

ll rights reserved.

tR

ev. 03 — 10 July 2007

22 of 61



P89LP

C9102_9103_9107_3

Product data shee

NX

P S

emiconductors

P89LP

C9102/9103/9107



51 core




MSB LSB Hex Binary

E1 E0

00 0000 0000

ADCS11 ADCS10 00 0000 0000

- - 00 0000 0000

- - 00 0000 0000

BSA1 - 00 000x 0000

FF 1111 1111

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

- DPS 00[1] 0000 00x0

F1 F0

00 0000 0000

00 0000 0000

00 0000 0000

SBRGS BRGEN 00[2] xxxx xx00

CO1 CMF1 00[1] xx00 0000

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

SV OI 70 0111 0000

FMCMD.1

FMCMD.0

© N

XP

B.V. 2007. A

ll rights reserved.

tR

ev. 03 — 10 July 2007

23 of 61




TMM1 - ADCI1 ENADC1










AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENT0 SRST 0


B* B register F0H

BRGR0[2] Baud rate generator rate low BEH

BRGR1[2] Baud rate generator rate high BFH

BRGCON Baud rate generator control BDH - - - - - -



95H








FMCMD.6

FMCMD.5

FMCMD.4

FMCMD.3

FMCMD.2


P89LP

C9102_9103_9107_3

Product data shee

NX

P S

emiconductors

P89LP

C9102/9103/9107



51 core

00 0000 0000

ET0 - 00 0000 0000

E9 E8

EKBI - 00[1] 00x0 0000

B9 B8

PT0 - 00[1] x000 0000

PT0H - 00[1] x000 0000

F9 F8

PKBI - 00[1] 00x0 0000

PKBIH - 00[1] 00x0 0000

PATN_SEL


KBMASK.1

- 00 xxxx x00x

KBPATN.1

- FF xxxx x11x

81 80

KBI1 - [3]

91 90

RXD TXD

(P0M1.1) - FF 1111 1111

(P0M2.1) - 00 0000 0000

(P1M1.1) (P1M1.0) FF[1] 1111 1111

(P1M2.1) (P1M2.0) 00[1] 0000 0000

PMOD1 PMOD0 00 0000 0000

SPD 00[1] 0000 0000

- - 00[1] xxxx xxxx




MSB LSB Hex Binary

© N

XP

B.V. 2007. A

ll rights reserved.

tR

ev. 03 — 10 July 2007

24 of 61


IEN0* Interrupt enable 0 A8H EA EWDRT EBO ES/ESR ET1 -


IEN1* Interrupt enable 1 E8H EAD EST - - - EC


IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 -


PBOH PSH/PSRH

PT1H -


IP1* Interrupt priority 1 F8H PAD PST - - - PC

IP1H Interrupt priority 1 high F7H PADH PSTH - - - PCH



86H - - - - KBMASK.2

KBPATN Keypad pattern register 93H - - - - - KBPATN.2

Bit address 87 86 85 84 83 82

P0* Port 0 80H - - CMPREF/CLKIN

CIN1A CIN1B KBI2

Bit address 97 96 95 94 93 92

P1* Port 1 90H - - RST - - -





PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0



B6H - - - - - -


P89LP

C9102_9103_9107_3

Product data shee

NX

P S

emiconductors

P89LP

C9102/9103/9107



51 core

D1 D0

F1 P 00 0000 0000

PT0AD.1 - 00 xx00 000x

R_SF R_EX [4]


00[5] 0000 0000

00[5] 0000 0000

00 0000 0000

00 0000 0000

xx xxxx xxxx

99 98

TI RI 00 0000 0000

OE STINT 00 0000 0000

07 0000 0111




MSB LSB Hex Binary

© N

XP

B.V. 2007. A

ll rights reserved.

tR

ev. 03 — 10 July 2007

25 of 61




RSTSRC Reset source register DFH - - BOF POF R_BK R_WD




SADDR Serial port address register A9H

SADEN Serial port address enable B9H

SBUF Serial port data buffer register 99H


SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8

SSTAT Serial port extended statusregister

BAH DBMOD INTLO CIDIS DBISEL FE BR



P89LP

C9102_9103_9107_3

Product data shee

NX

P S

emiconductors

P89LP

C9102/9103/9107



51 core

ese bits since they may be used for other

npredictable.

ared except POF and BOF; the power-on reset

TRIM register.


89 88

- - 00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

T0M1 T0M0 00 0000 0000


WDTOF WDCLK [5][7]

FF 1111 1111




MSB LSB Hex Binary

© N

XP

B.V. 2007. A

ll rights reserved.

tR

ev. 03 — 10 July 2007

26 of 61


[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is u


[4] The RSTSRC register reflects the cause of the P89LPC9102/9103/9107 reset. Upon a power-up reset, all reset source flags are clevalue is xx11 0000.


[6] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the






TL0 Timer 0 low 8AH

TL1 Timer 1 low 8BH


TRIM Internal oscillator trim register 96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2






8.2 Enhanced CPUThe P89LPC9102/9103/9107 uses an enhanced 80C51 CPU which runs at six times thespeed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, andmost instructions execute in one or two machine cycles.

8.3 Clocks

8.3.1 Clock definitions

The P89LPC9102/9103/9107 device has internal clocks as defined below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of the clocksources (see Figure 11 “Block diagram of P89LPC9102 oscillator control”) and can alsobe optionally divided to a slower frequency (see Section 8.8 “CCLK modification: DIVMregister”).

Note: fosc is defined as the OSCCLK frequency.

CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machinecycle, and most instructions are executed in one to two machine cycles (two or four CCLKcycles).

RCCLK — The internal 7.373 MHz RC oscillator output. The clock doubler option, whenenabled, provides an output frequency of 14.746 MHz.

PCLK — Clock for the various peripheral devices and is CCLK⁄2.

8.3.2 CPU clock (CCLK)

The P89LPC9102/9103/9107 provides user-selectable oscillator options in generating theCPU clock. This allows optimization for a range of needs from high precision to lowestpossible cost. These options are configured when the flash memory is programmed andinclude an on-chip watchdog oscillator, an on-chip RC oscillator, and an external clockinput.

8.4 On-chip RC oscillator optionThe P89LPC9102/9103/9107 has a 6-bit TRIM register that can be used to tune thefrequency of the RC oscillator. During reset, the TRIM value is initialized to a factorypre-programmed value to adjust the oscillator frequency to 7.373 MHz ± 1 % at roomtemperature. End-user applications can write to the Trim register to adjust the on-chip RCoscillator to other frequencies. When the clock doubler option is enabled (UCFG1.3 = 1)the output frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit(AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0allowing highest performance access. This bit can then be set in software if CCLK isrunning at 8 MHz or slower.

The RCCLK bit (TRIM.7) can be used to switch between the clock source selected byUCFG1 and the internal RC oscillator. This allows a low frequency source such as theWDT or low speed external source to clock the device in order to save power and thenswitch to the higher speed internal RC oscillator to perform processing.




8.5 Watchdog oscillator optionThe watchdog timer has a separate oscillator which has a frequency of 400 kHz. Thisoscillator can be used to save power when a high clock frequency is not needed.

8.6 External clock input optionIn this configuration, the processor clock is derived from an external source driving theP0.5/CMPREF/CLKIN pin. The rate may be from 0 Hz up to 18 MHz. TheP0.5/CMPREF/CLKIN pin may also be used as a standard port pin. When using anoscillator frequency above 12 MHz, the reset input function of P1.5 must beenabled. An external circuit is required to hold the device in reset at power-up untilVDD has reached its specified level. When system power is removed V DD will fallbelow the minimum specified operating voltage. When using an oscillator

Fig 11. Block diagram of P89LPC9102 oscillator control

Fig 12. Block diagram of P89LPC9103/9107 oscillator control

÷2

002aaa973

RTC

CPU

WDT

DIVMCCLKOSCCLK

PCLK TIMER 0TIMER 1

WATCHDOGOSCILLATOR


DOUBLER OPTION

(7.3728 MHz or14.7456 MHz)

(400 kHz)

CLKINADC1/DAC1

÷2

002aaa974

RTC

CPU

WDT

DIVMCCLKOSCCLK

PCLK TIMER 0TIMER 1

WATCHDOGOSCILLATOR

(400 kHz)

CLKINADC1/DAC1

BAUD RATEGENERATOR

UART


DOUBLER OPTION

(7.3728 MHz or14.7456 MHz)




frequency above 12 MHz, in some applications, an external brownout detect circuitmay be required to hold the device in reset when V DD falls below the minimumspecified operating voltage.

8.7 CCLK wake-up delayThe P89LPC9102/9103/9107 has an internal wake-up timer that delays the clock until itstabilizes depending to the clock source used.

8.8 CCLK modification: DIVM registerThe OSCCLK frequency can be divided down up to 510 times by configuring a dividingregister, DIVM, to generate CCLK. This feature makes it possible to temporarily run theCPU at a lower rate, reducing power consumption. By dividing the clock, the CPU canretain the ability to respond to events that would not exit Idle mode by executing its normalprogram at a lower rate. This can also allow bypassing the oscillator start-up time in caseswhere Power-down mode would otherwise be used. The value of DIVM may be changedby the program at any time without interrupting code execution.

8.9 Low power selectIf CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lowerthe power consumption further. On any reset, CLKLP is logic 0.

8.10 Memory organizationThe various P89LPC9102/9103/9107 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00H:7FH) accessed via direct or indirectaddressing, using instruction other than MOVX and MOVC. All or part of the stackmay be in this area.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and statusregisters, accessible only via direct addressing.

• CODE

1 kB of Code memory space, accessed as part of program execution and via theMOVC instruction.

8.11 InterruptsThe P89LPC9102 supports nine interrupt sources: timers 0 and 1, brownout detect,watchdog timer/RTC, keyboard, comparator 1, and the A/D converter.

The P89LPC9103/9107 support nine interrupt sources: timers 0 and 1, serial port Tx,serial port Rx, combined serial port Rx/Tx, brownout detect, watchdog timer/RTC,keyboard, comparator, and the A/D converter.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit inthe interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a globaldisable bit, EA, which disables all interrupts.




Each interrupt source can be individually programmed to one of four priority levels bysetting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. Aninterrupt service routine in progress can be interrupted by a higher priority interrupt, butnot by another interrupt of the same or lower priority. The highest priority interrupt servicecannot be interrupted by any other interrupt source. If two requests of different prioritylevels are pending at the start of an instruction, the request of higher priority level isserviced.

If requests of the same priority level are pending at the start of an instruction, an internalpolling sequence determines which request is serviced. This is called the arbitrationranking. Note that the arbitration ranking is only used to resolve pending requests of thesame priority level.

8.11.1 External interrupt inputs

The P89LPC9102/9103/9107 has a Keypad Interrupt function. This can be used as anexternal interrupt input.

If enabled when the P89LPC9102/9103/9107 is put into Power-down mode or Idle mode,the interrupt will cause the processor to wake-up and resume operation. Refer to Section8.14 “Power reduction modes” for details.

Fig 13. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC9102)

002aaa976

BOFEBO

KBIFEKBI

interruptto CPU

wake-up(if in power-down)

EWDRT

CMF

EC

EA (IE0.7)

RTCFERTC

(RTCCON.1)

WDOVF

TF1ET1

TF0ET0

ENADCI1ADCI1

ENBI1BNDI1

EAD




8.12 I/O portsThe P89LPC9102/9103/9107 has either 6, 7, or 8 I/O pins depending on the reset pinoption and clock source option chosen. Refer to Table 10.

[1] Required for operation above 12 MHz.

8.12.1 Port configurations

All but one I/O port pin on the P89LPC9102/9103/9107 may be configured by software toone of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 portoutputs), push-pull, open drain, and input-only. Two configuration registers for each portselect the output type for each port pin.

P1.5 (RST) can only be an input and cannot be configured.

Fig 14. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC9103/9107)

002aaa977

BOFEBO

KBIFEKBI

interruptto CPU

wake-up(if in power-down)

EWDRT

CMF

EC

EA (IE0.7)

RTCFERTC

(RTCCON.1)

WDOVF

TF1ET1

TI and RI/RIES/ESR

TIEST

TF0ET0

ENADCI1ADCI1

ENBI1BNDI1

EAD

Table 10. Number of I/O pins available

Clock source Reset option Number of I/O pins(10-pin package)

Number of I/O pins(14-pin package)

On-chip oscillator or watchdogoscillator

No external reset (except duringpower-up)

8 10

External RST pin supported 7 9

External clock input No external reset (except duringpower-up)

7 9

External RST pin supported[1] 6 8




8.12.2 Quasi-bidirectional output configuration

Quasi-bidirectional output type can be used as both an input and output without the needto reconfigure the port. This is possible because when the port outputs a logic HIGH, it isweakly driven, allowing an external device to pull the pin LOW. When the pin is drivenLOW, it is driven strongly and able to sink a fairly large current. These features aresomewhat similar to an open-drain output except that there are three pull-up transistors inthe quasi-bidirectional output that serve different purposes.

The P89LPC9102/9103/9107 is a 3 V device, however, the pins are 5 V-tolerant. Inquasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current flowingfrom the pin to VDD, causing extra power consumption. Therefore, applying 5 V inquasi-bidirectional mode is discouraged.

A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitchsuppression circuit.

8.12.3 Open-drain output configuration

The open-drain output configuration turns off all pull-ups and only drives the pull-downtransistor of the port driver when the port latch contains a logic 0. To be used as a logicoutput, a port configured in this manner must have an external pull-up, typically a resistortied to VDD.

An open-drain port pin has a Schmitt triggered input that also has a glitch suppressioncircuit.

8.12.4 Input-only configuration

The input-only port configuration has no output drivers. It is a Schmitt triggered input thatalso has a glitch suppression circuit.

8.12.5 Push-pull output configuration

The push-pull output configuration has the same pull-down structure as both theopen-drain and the quasi-bidirectional output modes, but provides a continuous strongpull-up when the port latch contains a logic 1. The push-pull mode may be used whenmore source current is needed from a port output. A push-pull port pin has a Schmitttriggered input that also has a glitch suppression circuit.

8.12.6 Port 0 analog functions

The P89LPC9102/9103/9107 incorporates an Analog Comparator. In order to give thebest analog function performance and to minimize power consumption, pins that are beingused for analog functions must have the digital outputs and digital inputs disabled.

Digital outputs are disabled by putting the port output into the Input-only (high-impedance)mode as described in Section 8.12.4 “Input-only configuration”.

Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On anyreset, the PT0AD bits default to logic 0s to enable digital functions.

8.12.7 Additional port features

After power-up, all pins are in Input-only mode. Please note that this is different fromthe LPC76x series of devices.




• After power-up all I/O pins, except P1.5, may be configured by software.

• Pin P1.5 is input-only.

Every output on the P89LPC9102/9103/9107 has been designed to sink typical LED drivecurrent. However, there is a maximum total output current for all ports which must not beexceeded. Please refer to Table 12 “Static characteristics” for detailed specifications.

All ports pins that can function as an output have slew rate controlled outputs to limit noisegenerated by quickly switching output signals. The slew rate is factory-set toapproximately 10 ns rise and fall times.

8.13 Power monitoring functionsThe P89LPC9102/9103/9107 incorporates power monitoring functions designed toprevent incorrect operation during initial power-up and power loss or reduction duringoperation. This is accomplished with two hardware functions: Power-on Detect andBrownout detect.

8.13.1 Brownout detection

The Brownout detect function determines if the power supply voltage drops below acertain level. The default operation is for a Brownout detection to cause a processor reset,however, it may alternatively be configured to generate an interrupt.

Brownout detection may be enabled or disabled in software.

If Brownout detection is enabled, the brownout condition occurs when VDD falls below thebrownout trip voltage, Vbo (see Table 12 “Static characteristics”), and is negated when VDDrises above Vbo. If the P89LPC9102/9103/9107 device is to operate with a power supplythat can be below 2.7 V, Brownout detect Enable (BOE) should be left in theunprogrammed state so that the device can operate at 2.4 V, otherwise continuousbrownout reset may prevent the device from operating.

For correct activation of Brownout detect, the VDD rise and fall times must be observed.Please see Table 12 “Static characteristics” for specifications.

8.13.2 Power-on detection

The Power-on Detect has a function similar to the Brownout detect, but is designed towork as power comes up initially, before the power supply voltage reaches a level whereBrownout detect can work. The Power-on detect flag (POF) in the RSTSRC register is setto indicate an initial power-up condition. The POF flag will remain set until cleared bysoftware.

8.14 Power reduction modesThe P89LPC9102/9103/9107 supports three different power reduction modes. Thesemodes are Idle mode, Power-down mode, and Total Power-down mode.

8.14.1 Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processorwhen an interrupt is generated. Any enabled interrupt source or reset may terminate Idlemode.




8.14.2 Slow-down mode using the DIVM register

Slow-down mode is achieved by dividing down the OSCCLK frequency to generate CCLK.This division is accomplished by configuring the DIVM register to divide OSCCLK by up to510 times. This feature makes it possible to temporarily run the CPU at a lower rate,reducing power consumption. By dividing the clock, the CPU can retain the ability torespond to events that would not exit Idle mode by executing its normal program at a lowerrate. This can also allow bypassing the oscillator start-up time in cases wherePower-down mode would otherwise be used. The value of DIVM may be changed by theprogram at any time without interrupting code execution.

8.14.3 Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption. TheP89LPC9102/9103/9107 exits Power-down mode via any reset, or certain interrupts. InPower-down mode, the power supply voltage may be reduced to the data retentionvoltage VDDR. This retains the RAM contents at the point where Power-down mode wasentered. SFR contents are not guaranteed after VDD has been lowered to VDDR, thereforeit is highly recommended to wake-up the processor via reset in this case. VDD must beraised to within the operating range before the Power-down mode is exited.

Some chip functions continue to operate and draw power during Power-down mode,increasing the total power used during Power-down mode. These include: Brownoutdetect, watchdog timer, comparators (note that comparator can be powered-downseparately), and RTC/system timer. The internal RC oscillator is disabled unless both theRC oscillator has been selected as the system clock and the RTC is enabled.

8.14.4 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry andthe voltage comparators are also disabled to conserve additional power. The internal RCoscillator is disabled unless both the RC oscillator has been selected as the system clockand the RTC is enabled. If the internal RC oscillator is used to clock the RTC duringPower-down mode, there will be high power consumption. Please use an external lowfrequency clock to achieve low power with the RTC running during Power-down mode.

8.15 ResetThe P1.5/RST pin can function as either an active-LOW reset input or as a digital input,P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to logic 1, enables the externalreset input function on P1.5. When cleared, P1.5 may be used as an input pin.

Remark: During a power-up sequence, the RPE selection is overridden and this pin willalways function as a reset input. An external circuit connected to this pin should nothold this pin LOW during a power-on sequence as this will keep the device in reset.After power-up this input will function either as an external reset input or as a digital inputas defined by the RPE bit. Only a power-up reset will temporarily override the selectiondefined by RPE bit. Other sources of reset will not override the RPE bit.

Remark: During a power cycle, VDD must fall below VPOR (see Table 12 “Staticcharacteristics”) before power is reapplied, in order to ensure a power-on reset.

Reset can be triggered from the following sources:

• External reset pin (during power-up or if user configured via UCFG1)




• Power-on detect

• Brownout detect

• Watchdog timer

• Software reset

• UART break character detect reset (P89LPC9103/9107).

For every reset source, there is a flag in the Reset Register, RSTSRC. The user can readthis register to determine the most recent reset source. These flag bits can be cleared insoftware by writing a logic 0 to the corresponding bit. More than one flag bit may be set:

• During a power-on reset, both POF and BOF are set but the other flag bits arecleared.

• For any other reset, previously set flag bits that have not been cleared will remain set.

8.16 Timers 0 and 1The P89LPC9102 has two general purpose timer/counters which are similar to thestandard 80C51 Timer 0 and Timer 1. These timers have five operating modes (modes 0,1, 2, 3, and 6). Modes 0, 1, and 2 are the same for both Timers. Mode 3 is different.

The P89LPC9103/9107 has two general purpose timers which are similar to the standard80C51 Timer 0 and Timer 1. These timers have four operating modes (modes 0, 1, 2, and3). Modes 0, 1, and 2 are the same for both Timers. Mode 3 is different.

8.16.1 Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bitCounter with a divide-by-32 prescaler. In this mode, the Timer register is configured as a13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.

8.16.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

8.16.3 Mode 2

Mode 2 configures the Timer register as an 8-bit counter with automatic reload. Mode 2operation is the same for Timer 0 and Timer 1.

8.16.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bitcounters and is provided for applications that require an extra 8-bit timer. When Timer 1 isin Mode 3 it can still be used by the serial port as a baud rate generator.

8.16.5 Mode 6 (P89LPC9102/9107)

In this mode, the corresponding timer can be changed to a PWM with a full period of256 timer clocks.




8.16.6 Timer overflow toggle output (P89LPC9102/9107)

Timers 0 and 1 can be configured to automatically toggle a port output whenever a timeroverflow occurs. The same device pins that are used for the T0 and T1 count inputs arealso used for the timer toggle outputs. The port outputs will be a logic 1 prior to the firsttimer overflow when this mode is turned on.

8.17 RTC/system timerThe P89LPC9102/9103/9107 has a simple RTC that allows a user to continue running anaccurate timer while the rest of the device is powered-down. The RTC can be a wake-upor an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescalerand a 16-bit loadable down counter. When it reaches all logic 0s, the counter will bereloaded again and the RTCF flag will be set. The clock source for this counter is theCCLK. Only power-on reset will reset the RTC and its associated SFRs to the defaultstate.

8.18 UART (P89LPC9103/9107)The P89LPC9103/9107 has an enhanced UART that is compatible with the conventional80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. TheP89LPC9103/9107 does include an independent Baud Rate Generator. The baud ratecan be selected from CCLK (divided by a constant), Timer 1 overflow, or the independentBaud Rate Generator. In addition to the baud rate generation, enhancements over thestandard 80C51 UART include Framing Error detection, automatic address recognition,selectable double buffering and several interrupt options. The UART can be operated infour modes: shift register, 8-bit UART, 9-bit UART, and CCLK⁄32 or CCLK⁄16.

8.18.1 Mode 0

Serial data enters and exits through RXD. TXD outputs the shift clock. Eight bits aretransmitted or received, LSB first. The baud rate is fixed at 1⁄16 of the CPU clockfrequency.

8.18.2 Mode 1

10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is storedin RB8 in Special Function Register SCON. The baud rate is variable and is determinedby the Timer 1 overflow rate or the Baud Rate Generator (described in Section 8.18.5“Baud rate generator and selection”).

8.18.3 Mode 2

11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 databits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data istransmitted, the 9th data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1.Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data isreceived, the 9th data bit goes into RB8 in Special Function Register SCON, while the stopbit is not saved. The baud rate is programmable to either 1⁄16 or 1⁄32 of the CPU clockfrequency, as determined by the SMOD1 bit in PCON.




8.18.4 Mode 3

11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 isthe same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variableand is determined by the Timer 1 overflow rate or the Baud Rate Generator (described insection Section 8.18.5 “Baud rate generator and selection”).

8.18.5 Baud rate generator and selection

The P89LPC9103/9107 enhanced UART has an independent Baud Rate Generator. Thebaud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0SFRs which together form a 16-bit baud rate divisor value that works in a similar manneras Timer 1. If the baud rate generator is used, Timer 1 can be used for other timingfunctions.

The UART can use either Timer 1 or the baud rate generator output (see Figure 15). Notethat Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. Theindependent Baud Rate Generator uses CCLK.

8.18.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)is logic 1, framing errors can be made available in SCON.7, respectively. If SMOD0 islogic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON[7:6]) are set upwhen SMOD0 is logic 0.

8.18.7 Break detect

Break detect is reported in the status register (SSTAT). A break is detected when11 consecutive bits are sensed LOW. The break detect can be used to reset the device.

8.18.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to bewritten to SBUF while the first character is being transmitted. Double buffering allowstransmission of a string of characters with only one stop bit between any two characters,as long as the next character is written between the start bit and the stop bit of theprevious character.

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART iscompatible with the conventional 80C51 UART. If enabled, the UART allows writing toSnBUF while the previous data is being shifted out. Double buffering is only allowed inModes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled(DBMOD = 0).

Fig 15. Baud rate sources for UART (Modes 1, 3)

baud rate modes 1 and 3

SBRGS = 1

SBRGS = 0

SMOD1 = 0

SMOD1 = 1timer 1 overflow(PCLK-based)

baud rate generator(CCLK-based) 002aaa978

÷2




8.18.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the Tx interrupt is generatedwhen the double buffer is ready to receive new data.

8.18.10 The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as longas TB8 is updated some time before that bit is shifted out. TB8 must not be changed untilthe bit is shifted out, as indicated by the Tx interrupt.

If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 willbe double-buffered together with SBUF data.

8.19 Analog comparatorsOne analog comparator is provided on the P89LPC9102/9103/9107. Comparatoroperation is such that the output is a logic 1 (which may be read in a register) when thepositive input is greater than the negative input (selectable from a pin or an internalreference voltage). Otherwise the output is a zero. The comparator may be configured tocause an interrupt when the output value changes.

The connections to the comparator are shown in Figure 16. The comparator functions toVDD = 2.4 V.

When the comparator is first enabled, the comparator’s interrupt flag is not guaranteed tobe stable for 10 microseconds. The comparator interrupt should not be enabled duringthat time, and the comparator interrupt flag must be cleared before the interrupt is enabledin order to prevent an immediate interrupt service.

When a comparator is disabled the comparator’s output, COx, goes HIGH. If thecomparator output was LOW and then is disabled, the resulting transition of thecomparator output from a LOW to HIGH state will set the comparator flag, CMFx. This willcause an interrupt if the comparator interrupt is enabled. The user should thereforedisable the comparator interrupt prior to disabling the comparator. Additionally, the usershould clear the comparator flag, CMFx, after disabling the comparator.

8.20 Internal reference voltageAn internal reference voltage generator may supply a default reference when a singlecomparator input pin is used. The value of the internal reference voltage, referred to asVref(bg), is 1.23 V ± 3 %.

Fig 16. Comparator input and output connections

comparator

CN1

(P0.4) CIN1A(P0.3) CIN1B

(P0.5) CMPREF

VREF

CO1

002aaa979

change detect

CMF1 interrupt

EC

CP1




8.21 Comparator interruptThe comparator has an interrupt flag contained in its configuration register. This flag is setwhenever the comparator output changes state. The flag may be polled by software ormay be used to generate an interrupt.

8.22 Comparator and power reduction modesThe comparator may remain enabled when Power-down mode or Idle mode is activated,but the comparator is disabled automatically in Total Power-down mode.

If the comparator interrupt is enabled (except in Total Power-down mode), a change of thecomparator output state will generate an interrupt and wake-up the processor. If thecomparator output to a pin is enabled, the pin should be configured in the push-pull modein order to obtain fast switching times while in Power-down mode. The reason is that withthe oscillator stopped, the temporary strong pull-up that normally occurs during switchingon a quasi-bidirectional port pin does not take place.

The comparator consumes power in Power-down mode and Idle mode, as well as in thenormal operating mode. This fact should be taken into account when system powerconsumption is an issue. To minimize power consumption, the user can disable thecomparator via PCONA.5 or put the device in Total Power-down mode.

8.23 Keypad interrupt (KBI)The Keypad Interrupt function is intended primarily to allow a single interrupt to begenerated when Port 0 is equal to or not equal to a certain pattern. This function can beused for bus address recognition or keypad recognition. The user can configure the portvia SFRs for different tasks.

The Keypad Interrupt Mask Register (KBMASK) is used to define which input pinsconnected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) isused to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag(KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition ismatched while the Keypad Interrupt function is active. An interrupt will be generated ifenabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used todefine equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series,the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any keyconnected to Port 0 which is enabled by the KBMASK register will cause the hardware toset KBIF and generate an interrupt if it has been enabled. The interrupt may be used towake-up the CPU from Idle mode or Power-down mode. This feature is particularly usefulin handheld, battery powered systems that need to carefully manage power consumptionyet also need to be convenient to use.

In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longerthan six CCLKs.

8.24 Watchdog timerThe watchdog timer causes a system reset when it underflows as a result of a failure tofeed the timer prior to the timer reaching its terminal count. It consists of a programmable12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap




taken from the prescaler. The clock source for the prescaler is either the PCLK or thenominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by apower-on reset. When the watchdog timer feature is disabled, it can be used as an intervaltimer and may generate an interrupt. Figure 17 shows the watchdog timer in Watchdogmode. Feeding the watchdog timer requires a two-byte sequence. If PCLK is selected asthe watchdog timer clock and the CPU is powered-down, the watchdog timer is disabled.The watchdog timer has a time-out period that ranges from a few µs to a few seconds.Please refer to the P89LPC9102/9103/9107 User manual UM10112 for more details.

8.25 Additional features

8.25.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,as if an external reset or watchdog timer reset had occurred. Care should be taken whenwriting to AUXR1 to avoid accidental software resets.

8.25.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the addressused with certain instructions. The DPS bit in the AUXR1 register selects one of the twoData Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit maybe toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,without the possibility of inadvertently altering other bits in the register.

(1) Watchdog timer reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed bya feed sequence.

Fig 17. Watchdog timer in Watchdog mode (WDTE = 1)

PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLKWDCON (A7H)

SHADOW REGISTER

PRESCALER

002aaa980

8-BIT DOWN COUNTER

WDL (C1H)

watchdogoscillator

PCLK÷32

MOV WFEED1, #0A5HMOV WFEED2, #05AH

reset (1)




8.26 Flash program memory

8.26.1 General description

The P89LPC9102/9103/9107 flash memory provides in-circuit electrical erasure andprogramming. The flash can be erased, read, and written as bytes. The Sector and PageErase functions can erase any flash sector (256 bytes) or page (16 bytes). The ChipErase operation will erase the entire program memory. In-Circuit Programming usingstandard commercial programmers is available. In addition, In-Application ProgrammingLite (IAP-Lite) and byte erase allows code memory to be used for non-volatile datastorage. On-chip erase and write timing generation contribute to a user-friendlyprogramming interface. The P89LPC9102/9103/9107 flash reliably stores memorycontents even after more than 400000 erase and program cycles. The cell is designed tooptimize the erase and programming mechanisms. The P89LPC9102/9103/9107 usesVDD as the supply voltage to perform the Program/Erase algorithms.

8.26.2 Features

• Programming and erase over the full operating voltage range.

• Byte-erase allowing code memory to be used for data storage.

• Read/Programming/Erase using ICP.

• Any flash program/erase operation in 2 ms.

• Programming with industry-standard commercial programmers.

• Programmable security for the code in the flash for each sector.

• More than 400000 minimum erase/program cycles for each byte.

• 20-year minimum data retention.

8.26.3 Flash organization

The P89LPC9102/9103/9107 program memory consists of four 256 byte sectors. Eachsector can be further divided into 16-byte pages. In addition to sector erase, page erase,and byte erase, a 16-byte page register is included which allows from 1 byte to 16 bytes ofa given page to be programmed at the same time, substantially reducing overallprogramming time. In addition, erasing and reprogramming of user-programmableconfiguration bytes including UCFG1, the Boot Status Bit, and the Boot Vector issupported.

8.26.4 Flash programming and erasing

Different methods of erasing or programming of the flash are available. The flash may beprogrammed or erased in the end-user application (IAP-Lite) under control of theapplication’s firmware. Another option is to use the ICP mechanism. This ICP systemprovides for programming through a serial clock- serial data interface. Third, the flash maybe programmed or erased using a commercially available EPROM programmer whichsupports this device. This device does not provide for direct verification of code memorycontents. Instead this device provides a 32-bit CRC result on either a sector or the entire1 kB of user code space.




8.26.5 In-circuit programming

In-Circuit Programming is performed without removing the microcontroller from thesystem. The In-Circuit Programming facility consists of internal hardware resources tofacilitate remote programming of the P89LPC9102/9103/9107 through a two-wire serialinterface. The NXP In-Circuit Programming facility has made in-circuit programming in anembedded application, using commercially available programmers, possible with aminimum of additional expense in components and circuit board area. The ICP functionuses five pins. Only a small connector needs to be available to interface your applicationto a commercial programmer in order to use this feature. Additional details may be foundin the P89LPC9102/9103/9107 User manual UM10112.

8.26.6 In-application programming (IAP-Lite)

In-Application Programming is performed in the application under the control of themicrocontroller’s firmware. The IAP facility consists of internal hardware resources tofacilitate programming and erasing. The NXP In-Application Programming (IAP-Lite) hasmade in-application programming in an embedded application possible without additionalcomponents. This is accomplished through the use of four SFRs consisting of acontrol/status register, a data register, and two address registers. Additional details maybe found in the P89LPC9102/9103/9107 User manual UM10112.

8.26.7 Using flash as data storage

The flash code memory array of this device supports individual byte erasing andprogramming. Any byte in the code memory array may be read using the MOVCinstruction, provided that the sector containing the byte has not been secured (a MOVCinstruction is not allowed to read code memory contents of a secured sector). Thus anybyte in a non-secured sector may be used for non-volatile data storage.

8.26.8 User configuration bytes

Some user-configurable features of the P89LPC9102/9103/9107 must be defined atpower-up and therefore cannot be set by the program after start of execution. Thesefeatures are configured through the use of the flash byte UCFG1. Please see theP89LPC9102/9103/9107 User manual UM10112 for additional details.

8.26.9 User sector security bytes

There are four user sector security bytes, each corresponding to one sector. Please seethe P89LPC9102/9103/9107 User manual UM10112 for additional details.




9. A/D Converter

9.1 General descriptionThe P89LPC9102/9103/9107 has an 8-bit, 4-channel multiplexed successiveapproximation analog-to-digital converter. The A/D consists of a 4-input multiplexer whichfeeds a sample-and-hold circuit providing an input signal to one of two comparator inputs.The control logic in combination with the Successive Approximation Register (SAR) drivesa digital-to-analog converter which provides the other input to the comparator. The outputof the comparator is fed to the SAR. A block diagram of the A/D converter is shown inFigure 18.

9.2 Featuresn 8-bit, 4-channel multiplexed input, successive approximation A/D converter

n Four result registers

n Six operating modes

u Fixed channel, single conversion mode

u Fixed channel, continuous conversion mode

u Auto scan, single conversion mode

u Auto scan, continuous conversion mode

u Dual channel, continuous conversion mode

u Single step mode

n Two conversion start modes

u Timer triggered start

u Start immediately

n 8-bit conversion time of ≥ 3.9 µs at an ADC clock of 3.3 MHz

n Interrupt or polled operation

n Boundary limits interrupt

n DAC output to a port pin with high output impedance

n Clock divider

n Power-down mode




9.3 Block diagram

9.4 A/D operating modes

9.4.1 Fixed channel, single conversion mode

A single input channel can be selected for conversion. A single conversion will beperformed and the result placed in the result register which corresponds to the selectedinput channel. An interrupt, if enabled, will be generated after the conversion completes.

9.4.2 Fixed channel, continuous conversion mode

A single input channel can be selected for continuous conversion. The results of theconversions will be sequentially placed in the four result registers. An interrupt, if enabled,will be generated after every four conversions. Additional conversion results will againcycle through the four result registers, overwriting the previous results. Continuousconversions continue until terminated by the user.

9.4.3 Auto scan, single conversion mode

Any combination of the four input channels can be selected for conversion. A singleconversion of each selected input will be performed and the result placed in the resultregister which corresponds to the selected input channel. An interrupt, if enabled, will begenerated after all selected channels have been converted. If only a single channel isselected this is equivalent to single channel, single conversion mode.

9.4.4 Auto scan, continuous conversion mode

Any combination of the four input channels can be selected for conversion. A conversionof each selected input will be performed and the result placed in the result register whichcorresponds to the selected input channel. An interrupt, if enabled, will be generated afterall selected channels have been converted. The process will repeat starting with the firstselected channel. Additional conversion results will again cycle through the four resultregisters, overwriting the previous results. Continuous conversions continue untilterminated by the user.

Fig 18. ADC block diagram

+

–

comp

DAC1

SAR

8

INPUTMUX

CONTROLLOGIC

CCLK

002aaa975




9.4.5 Dual channel, continuous conversion mode

This is a variation of the auto scan continuous conversion mode where conversion occurson two user-selectable inputs. The result of the conversion of the first channel is placed inresult register, AD1DAT0. The result of the conversion of the second channel is placed inresult register, AD1DAT1. The first channel is again converted and its result stored inAD1DAT2. The second channel is again converted and its result placed in AD1DAT3. Aninterrupt is generated, if enabled, after every set of four conversions (two conversions perchannel).

9.4.6 Single step mode

This special mode allows ‘single-stepping’ in an auto scan conversion mode. Anycombination of the four input channels can be selected for conversion. After each channelis converted, an interrupt is generated, if enabled, and the A/D waits for the next startcondition. May be used with any of the start modes.

9.5 Conversion start modes

9.5.1 Timer triggered start

An A/D conversion is started by the overflow of Timer 0. Once a conversion has started,additional Timer 0 triggers are ignored until the conversion has completed. The Timertriggered start mode is available in all A/D operating modes.

9.5.2 Start immediately

Programming this mode immediately starts a conversion. This start mode is available in allA/D operating modes.

9.6 Boundary limits interruptThe A/D converter has both a high and low boundary limit register. After the four MSBshave been converted, these four bits are compared with the four MSBs of the boundaryhigh and low registers. If the four MSBs of the conversion are outside the limit an interruptwill be generated, if enabled. If the conversion result is within the limits, the boundarylimits will again be compared after all 8 bits have been converted. An interrupt will begenerated, if enabled, if the result is outside the boundary limits. The boundary limit maybe disabled by clearing the boundary limit interrupt enable.

9.7 DAC output to a port pin with high output impedanceThe A/D converter’s DAC block can be output to a port pin. In this mode, the AD1DAT3register is used to hold the value fed to the DAC. After a value has been written to the DAC(written to AD1DAT3), the DAC output will appear on the channel 3 pin.

9.8 Clock dividerThe A/D converter requires that its internal clock source be in the range of 500 kHz to3.3 MHz to maintain accuracy. A programmable clock divider that divides the clockfrom 1 to 8 is provided for this purpose.




9.9 Power-down and Idle modeIn Idle mode the A/D converter, if enabled, will continue to function and can cause thedevice to exit Idle mode when the conversion is completed if the A/D interrupt is enabled.In Power-down mode or Total Power-down mode, the A/D does not function. If the A/D isenabled, it will consume power. Power can be reduced by disabling the A/D.




10. Limiting values

[1] The following applies to Table 11 “Limiting values”:

a) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of thedevice at these or any conditions other than those described in Table 12 “Static characteristics” and Table 13 “Dynamiccharacteristics (12 MHz)” section of this specification are not implied.

b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessivestatic charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unlessotherwise noted.

Table 11. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

Tamb(bias) bias ambient temperature −55 +125 °C

Tstg storage temperature −65 +150 °C

IOH(I/O) HIGH-level output current perinput/output pin

- 8 mA

IOL(I/O) LOW-level output current perinput/output pin

- 20 mA

II/Otot(max) maximum total input/output current - 120 mA

Vn voltage on any other pin except VSS, with respect toVDD

−0.5 +5.5 V

Ptot(pack) total power dissipation per package based on package heattransfer, not device powerconsumption

- 1.5 W




11. Static characteristics

Table 12. Static characteristicsVDD = 2.4 V to 3.6 V unless otherwise specified.Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

IDD(oper) operating supply current 3.6 V; 12 MHz [2] - 7 11 mA

3.6 V; 7.373 MHz [3] - 4 7 mA

IDD(idle) Idle mode supply current 3.6 V; 12 MHz [2] - 3 5 mA

3.6 V; 7.373 MHz [3] - 2 4 mA

IDD(pd) Power-down mode supplycurrent

3.6 V; voltagecomparatorspowered-down

[2] - 55 80 µA

IDD(tpd) total Power-down modesupply current

3.6 V [4] - 0.5 5 µA

(dV/dt)r rise rate of VDD - - 2 mV/µs

(dV/dt)f fall rate of VDD - - 50 mV/µs

VPOR power-on reset voltage - - 0.2 V

VDDR data retention supply voltage 1.5 - - V

Vth(HL) HIGH-LOW threshold voltage 0.22VDD 0.4VDD - V

Vth(LH) LOW-HIGH threshold voltage - 0.6VDD 0.7VDD V

Vhys hysteresis voltage - 0.2VDD - V

VOL LOW-level output voltage IOL = 20 mA [5] - 0.6 1.0 V

IOL = 10 mA [5] - 0.3 0.5 V

IOL = 3.2 mA [5] - 0.2 0.3 V

VOH HIGH-level output voltage IOH = −8 mA;push-pull mode, all ports

VDD − 1.0 - - V

IOH = −3.2 mA;push-pull mode, all ports

VDD − 0.7 VDD − 0.4 - V

IOH = −20 µA;quasi-bidirectional mode,all ports

VDD − 0.3 VDD − 0.2 - V

Ciss input capacitance [6] - - 15 pF

IIL LOW-level input current VI = 0.4 V; all ports [7] - - −80 µA

ILI input leakage current VI = VIL or VIH; all ports [8] - - ±1 µA

ITHL HIGH-LOW transition current VI = 2.0 V atVDD = 3.6 V; all ports

[9][10] −30 - −450 µA

RRST_N(int) internal pull-up resistance onpin RST

10 - 30 kΩ




[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.

[2] The IDD(oper), IDD(idle), and IDD(pd) specifications are measured using an external clock with the following functions disabled: comparators,real-time clock, and watchdog timer.

[3] The IDD(oper) and IDD(idle) specifications are measured using with the following functions disabled: comparators, real-time clock, andwatchdog timer.

[4] The IDD(tpd) specification is measured using an external clock with the following functions disabled: comparators, real-time clock,brownout detect, and watchdog timer.

[5] Applies to all ports, in all modes except Hi-Z.

[6] Pin capacitance is characterized but not tested.

[7] Measured with port in quasi-bidirectional mode.

[8] Measured with port in high-impedance mode.

[9] Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups)

[10] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current ishighest when VI is approximately 2 V.

Vbo brownout trip voltage 2.4 V < VDD < 3.6 V; withBOV = 1, BOPD = 0

2.40 - 2.70 V

Vref(bg) band gap reference voltage 1.19 1.23 1.27 V

TCbg band gap temperaturecoefficient

- 10 20 ppm/°C

Table 12. Static characteristics …continuedVDD = 2.4 V to 3.6 V unless otherwise specified.Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit




12. Dynamic characteristics

[1] Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed tooperate down to 0 Hz.

Table 13. Dynamic characteristics (12 MHz)VDD = 2.4 V to 3.6 V unless otherwise specified.Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.[1]

Symbol Parameter Conditions Variable clock fext = 12 MHz Unit

Min Max Min Max

fosc(RC) internal RC oscillatorfrequency

clock doubleroption = OFF (default);nominal f = 7.3728 MHz;trimmed to ±1 % atTamb = 25 °C

7.189 7.557 7.189 7.557 MHz

clock doubleroption = ON; nominalf = 14.7456 MHz;VDD = 2.7 V to 3.6 V

14.378 15.114 14.378 15.114 MHz

fosc(WD) internal watchdogoscillator frequency

nominal f = 400 kHz 320 520 320 520 kHz

Tcy(clk) clock cycle time see Figure 20 83 - - - ns

fCLKLP low-power select clockfrequency

0 8 - - MHz

External clock

fext external clockfrequency

- - 0 12 MHz

tCHCX clock HIGH time VDD = 2.7 V to 3.6 V; seeFigure 20

33 Tcy(clk) − tCLCX 33 - ns

tCLCX clock LOW time 33 Tcy(clk) − tCHCX 33 - ns

tCLCH clock rise time - 8 - 8 ns

tCHCL clock fall time - 8 - 8 ns

Glitch filter

tgr glitch rejection P1.5/RST pin - 50 - 50 ns

any pin except P1.5/RST - 15 - 15 ns

tsa signal acceptance P1.5/RST pin 125 - 125 - ns

any pin except P1.5/RST 50 - 50 - ns

Shift register (UART mode 0 - P89LPC9103)

TXLXL serial port clock cycletime

see Figure 19 16Tcy(clk) - 1333 - ns

tQVXH output data set-up toclock rising edge


tXHQX output data hold afterclock rising edge

see Figure 19 - Tcy(clk) + 20 - 103 ns

tXHDX input data hold afterclock rising edge

see Figure 19 - 0 - 0 ns

tXHDV input data valid to clockrising edge

see Figure 19 150 - 150 - ns




[1] Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed tooperate down to 0 Hz.

Table 14. Dynamic characteristics (18 MHz)VDD = 3.0 V to 3.6 V unless otherwise specified.Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.[1]

Symbol Parameter Conditions Variable clock fext = 18 MHz Unit

Min Max Min Max

fosc(RC) internal RC oscillatorfrequency

clock doubleroption = OFF (default);nominal f = 7.3728 MHz;trimmed to ±1 % atTamb = 25 °C

7.189 7.557 7.189 7.557 MHz

clock doubleroption = ON; nominalf = 14.7456 MHz

14.378 15.114 14.378 15.114 MHz

fosc(WD) internal watchdogoscillator frequency

nominal f = 400 kHz 320 520 320 520 kHz

Tcy(clk) clock cycle time see Figure 20 83 - - - ns

fCLKLP low-power select clockfrequency

0 8 - - MHz

External clock

fext external clockfrequency

- - 0 18 MHz

tCHCX clock HIGH time see Figure 20 22 Tcy(clk) − tCLCX 22 - ns

tCLCX clock LOW time 22 Tcy(clk) − tCHCX 22 - ns

tCLCH clock rise time - 5 - 5 ns

tCHCL clock fall time - 5 - 5 ns

Glitch filter

tgr glitch rejection P1.5/RST pin - 50 - 50 ns

any pin except P1.5/RST - 15 - 15 ns

tsa signal acceptance P1.5/RST pin 125 - 125 - ns

any pin except P1.5/RST 50 - 50 - ns

Shift register (UART mode 0 - P89LPC9103)

TXLXL serial port clock cycletime


tQVXH output data set-up toclock rising edge


tXHQX output data hold afterclock rising edge

see Figure 19 - Tcy(clk) + 20 - 75 ns

tXHDX input data hold afterclock rising edge

see Figure 19 - 0 - 0 ns

tXHDV input data valid to clockrising edge

see Figure 19 150 - 150 - ns




12.1 Waveforms

Fig 19. Shift register mode timing (P89LPC9103/9107)

0 1 2 3 4 5 6 7

valid valid valid valid valid valid valid valid

TXLXL

002aaa906

set TI

set RI

tXHQXtQVXH

tXHDV

tXHDX

clock

output data

write to SBUF

input data

clear RI

Fig 20. External clock timing

tCHCL tCLCX

tCHCX

Tcy(clk)

tCLCH

002aaa907

0.2VDD + 0.9 V

0.2VDD − 0.1 V

VDD − 0.5 V

0.45 V




13. Other characteristics

13.1 Comparator electrical characteristics

[1] This parameter is characterized, but not tested in production.

13.2 A/D converter electrical characteristics

Table 15. Comparator electrical characteristicsVDD = 2.4 V to 3.6 V, unless otherwise specified.Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

VIO input offset voltage - - ±10 mV

VIC common-mode input voltage 0 - VDD − 0.3 V

CMRR common-mode rejection ratio [1] - - −50 dB

tres(tot) total response time - 250 500 ns

t(CE-OV) chip enable to output valid time - - 10 µs

ILI input leakage current 0 V < VI < VDD - - ±1 µA

Table 16. A/D converter electrical characteristicsVDD = 2.4 V to 3.6 V, unless otherwise specified.Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.All limits valid for an external source impedance of less than 10 kΩ.

Symbol Parameter Conditions Min Typ Max Unit

VIA analog input voltage VSS − 0.2 - VSS + 0.2 V

Ciss input capacitance - - 15 pF

ED differential linearity error - - ±1 LSB

EL(adj) integral non-linearity - - ±1 LSB

EO offset error - - ±2 LSB

EG gain error - - ±1 %

Eu(tot) total unadjusted error - - ±2 LSB

MCTC channel-to-channel matching - - ±1 LSB

αct(port) crosstalk between port inputs 0 kHz to 100 kHz - - −60 dB

SRin input slew rate - - 100 V/ms

Tcy(ADC) ADC clock cycle 111 - 2000 ns

tADC ADC conversion time A/D enabled - - 13tCLK(ADC) µs




14. Package outline

Fig 21. Package outline SOT650-1 (HVSON10)

0.50.210.050.00

A1 EhbUNIT D(1) ye

2

e1

REFERENCESOUTLINEVERSION

EUROPEANPROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.12.9

c Dh

1.751.45

y1

3.12.9

2.552.15

0.300.18

0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT650-1 MO-229 - - -- - -

E(1)

0.550.30

L

0.1

v

0.05

w

0 2 mm1

scale

SOT650-1HVSON10: plastic thermal enhanced very thin small outline package; no leads;10 terminals; body 3 x 3 x 0.85 mm

A(1)

max.

AA1

c

detail X

y

Dh

Eh

e

L

10

51

6

D

E

y1 C

C

B A

01-01-2202-02-08



X

e1

b ACC

Bv M

w M

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.




Fig 22. Package outline SOT402-1 (TSSOP14)

UNIT A1 A2 A3 bp c D (1) E (2) (1)e HE L L p Q Zywv θ



IEC JEDEC JEITA

mm 0.150.05

0.950.80

0.300.19

0.20.1

5.14.9

4.54.3

0.656.66.2

0.40.3

0.720.38

80

o

o0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.750.50

SOT402-1 MO-15399-12-2703-02-18

w Mbp

D

Z

e

0.25

1 7

14 8

θ

AA1

A2

Lp

Q

detail X

L

(A )3

HE

E

c

v M A

XA

y

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

Amax.

1.1

pin 1 index




Fig 23. Package outline SOT27-1 (DIP14)

UNIT Amax.

1 2 (1) (1)b1 c D(1)ZE e MHL



IEC JEDEC JEITA

mm

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT27-199-12-2703-02-13

A min.

A max. b max.

wMEe1

1.731.13

0.530.38

0.360.23

19.5018.55

6.486.20

3.603.05

0.2542.54 7.628.257.80

10.08.3

2.24.2 0.51 3.2

0.0680.044

0.0210.015

0.770.73

0.0140.009

0.260.24

0.140.12

0.010.1 0.30.320.31

0.390.33

0.0870.17 0.02 0.13

050G04 MO-001 SC-501-14

MH

c

(e )1

ME

A

L

seat

ing

plan

e

A1

w Mb1

e

D

A2

Z

14

1

8

7

b

E

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1




15. Abbreviations

Table 17. Acronym list

Acronym Description

A/D Analog-to-Digital

BOE Brownout Enable

CMRR Common-Mode Rejection Ratio

DAC Digital-to-Analog Converter

EMI Electromagnetic Interference

IAP In-Application Programming

ICP In-Circuit Programming

LSB Least Significant Bit

MSB Most Significant Bit

PWM Pulse Width Modulator

RTC Real-Time Clock

SAR Successive Approximation Register

UART Universal Asynchronous Receiver/Transmitter




16. Revision history

Table 18. Revision history

Document ID Release date Data sheet status Change notice Supersedes

P89LPC9102_9103_ 9107_3 20070710 Product data sheet - P89LPC9102_9103_9107_2

Modifications: • The format of this data sheet has been redesigned to comply with the new identityguidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Added new device P89LPC9107FN.

P89LPC9102_9103_ 9107_2 20050411 Product data sheet - P89LPC9102_9103_9107_1

P89LPC9102_9103_ 9107_1 20050111 Product data sheet - -




17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product statusinformation is available on the Internet at URL http://www.nxp.com.

17.2 Definitions

Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result inmodifications or additions. NXP Semiconductors does not give anyrepresentations or warranties as to the accuracy or completeness ofinformation included herein and shall have no liability for the consequences ofuse of such information.

Short data sheet — A short data sheet is an extract from a full data sheetwith the same product type number(s) and title. A short data sheet is intendedfor quick reference only and should not be relied upon to contain detailed andfull information. For detailed and full information see the relevant full datasheet, which is available on request via the local NXP Semiconductors salesoffice. In case of any inconsistency or conflict with the short data sheet, thefull data sheet shall prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate andreliable. However, NXP Semiconductors does not give any representations orwarranties, expressed or implied, as to the accuracy or completeness of suchinformation and shall have no liability for the consequences of use of suchinformation.

Right to make changes — NXP Semiconductors reserves the right to makechanges to information published in this document, including withoutlimitation specifications and product descriptions, at any time and withoutnotice. This document supersedes and replaces all information supplied priorto the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,authorized or warranted to be suitable for use in medical, military, aircraft,space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected toresult in personal injury, death or severe property or environmental damage.NXP Semiconductors accepts no liability for inclusion and/or use of NXPSemiconductors products in such equipment or applications and thereforesuch inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for thespecified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined inthe Absolute Maximum Ratings System of IEC 60134) may cause permanentdamage to the device. Limiting values are stress ratings only and operation ofthe device at these or any other conditions above those given in theCharacteristics sections of this document is not implied. Exposure to limitingvalues for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are soldsubject to the general terms and conditions of commercial sale, as publishedat http://www.nxp.com/profile/terms, including those pertaining to warranty,intellectual property rights infringement and limitation of liability, unlessexplicitly otherwise agreed to in writing by NXP Semiconductors. In case ofany inconsistency or conflict between information in this document and suchterms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpretedor construed as an offer to sell products that is open for acceptance or thegrant, conveyance or implication of any license under any copyrights, patentsor other industrial or intellectual property rights.

17.4 TrademarksNotice: All referenced brands, product names, service names and trademarksare the property of their respective owners.

18. Contact information

For additional information, please visit: http://www .nxp.com

For sales office addresses, send an email to: salesad [email protected]

Document status [1] [2] Product status [3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.



http://www.nxp.com

http://www.nxp.com/profile/terms


19. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 12 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 12.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 13 Product comparison overview . . . . . . . . . . . . . 24 Ordering information . . . . . . . . . . . . . . . . . . . . . 34.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 35 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 67 Pinning information . . . . . . . . . . . . . . . . . . . . . . 87.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 108 Functional description . . . . . . . . . . . . . . . . . . 158.1 Special function registers . . . . . . . . . . . . . . . . 158.2 Enhanced CPU. . . . . . . . . . . . . . . . . . . . . . . . 278.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278.3.1 Clock definitions . . . . . . . . . . . . . . . . . . . . . . . 278.3.2 CPU clock (CCLK) . . . . . . . . . . . . . . . . . . . . . 278.4 On-chip RC oscillator option . . . . . . . . . . . . . . 278.5 Watchdog oscillator option . . . . . . . . . . . . . . . 288.6 External clock input option . . . . . . . . . . . . . . . 288.7 CCLK wake-up delay . . . . . . . . . . . . . . . . . . . 298.8 CCLK modification: DIVM register . . . . . . . . . 298.9 Low power select . . . . . . . . . . . . . . . . . . . . . . 298.10 Memory organization . . . . . . . . . . . . . . . . . . . 298.11 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298.11.1 External interrupt inputs . . . . . . . . . . . . . . . . . 308.12 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318.12.1 Port configurations . . . . . . . . . . . . . . . . . . . . . 318.12.2 Quasi-bidirectional output configuration . . . . . 328.12.3 Open-drain output configuration . . . . . . . . . . . 328.12.4 Input-only configuration . . . . . . . . . . . . . . . . . 328.12.5 Push-pull output configuration . . . . . . . . . . . . 328.12.6 Port 0 analog functions . . . . . . . . . . . . . . . . . . 328.12.7 Additional port features. . . . . . . . . . . . . . . . . . 328.13 Power monitoring functions. . . . . . . . . . . . . . . 338.13.1 Brownout detection . . . . . . . . . . . . . . . . . . . . . 338.13.2 Power-on detection . . . . . . . . . . . . . . . . . . . . . 338.14 Power reduction modes . . . . . . . . . . . . . . . . . 338.14.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338.14.2 Slow-down mode using the DIVM register . . . 348.14.3 Power-down mode . . . . . . . . . . . . . . . . . . . . . 348.14.4 Total Power-down mode . . . . . . . . . . . . . . . . . 348.15 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348.16 Timers 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . 358.16.1 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.16.2 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358.16.3 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358.16.4 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358.16.5 Mode 6 (P89LPC9102/9107) . . . . . . . . . . . . . 358.16.6 Timer overflow toggle output

(P89LPC9102/9107) . . . . . . . . . . . . . . . . . . . 368.17 RTC/system timer. . . . . . . . . . . . . . . . . . . . . . 368.18 UART (P89LPC9103/9107) . . . . . . . . . . . . . . 368.18.1 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368.18.2 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368.18.3 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368.18.4 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378.18.5 Baud rate generator and selection . . . . . . . . . 378.18.6 Framing error . . . . . . . . . . . . . . . . . . . . . . . . . 378.18.7 Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . 378.18.8 Double buffering . . . . . . . . . . . . . . . . . . . . . . . 378.18.9 Transmit interrupts with double buffering

enabled (Modes 1, 2 and 3) . . . . . . . . . . . . . . 388.18.10 The 9th bit (bit 8) in double buffering

(Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . 388.19 Analog comparators . . . . . . . . . . . . . . . . . . . . 388.20 Internal reference voltage. . . . . . . . . . . . . . . . 388.21 Comparator interrupt . . . . . . . . . . . . . . . . . . . 398.22 Comparator and power reduction modes . . . . 398.23 Keypad interrupt (KBI) . . . . . . . . . . . . . . . . . . 398.24 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 398.25 Additional features . . . . . . . . . . . . . . . . . . . . . 408.25.1 Software reset . . . . . . . . . . . . . . . . . . . . . . . . 408.25.2 Dual data pointers . . . . . . . . . . . . . . . . . . . . . 408.26 Flash program memory . . . . . . . . . . . . . . . . . 418.26.1 General description . . . . . . . . . . . . . . . . . . . . 418.26.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418.26.3 Flash organization . . . . . . . . . . . . . . . . . . . . . 418.26.4 Flash programming and erasing. . . . . . . . . . . 418.26.5 In-circuit programming . . . . . . . . . . . . . . . . . . 428.26.6 In-application programming (IAP-Lite) . . . . . . 428.26.7 Using flash as data storage . . . . . . . . . . . . . . 428.26.8 User configuration bytes. . . . . . . . . . . . . . . . . 428.26.9 User sector security bytes . . . . . . . . . . . . . . . 429 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . 439.1 General description . . . . . . . . . . . . . . . . . . . . 439.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439.3 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . 449.4 A/D operating modes . . . . . . . . . . . . . . . . . . . 449.4.1 Fixed channel, single conversion mode . . . . . 449.4.2 Fixed channel, continuous conversion mode . 449.4.3 Auto scan, single conversion mode . . . . . . . . 449.4.4 Auto scan, continuous conversion mode . . . . 44



continued >>


9.4.5 Dual channel, continuous conversion mode . . 459.4.6 Single step mode . . . . . . . . . . . . . . . . . . . . . . 459.5 Conversion start modes . . . . . . . . . . . . . . . . . 459.5.1 Timer triggered start . . . . . . . . . . . . . . . . . . . . 459.5.2 Start immediately . . . . . . . . . . . . . . . . . . . . . . 459.6 Boundary limits interrupt. . . . . . . . . . . . . . . . . 459.7 DAC output to a port pin with high output

impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . 459.8 Clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 459.9 Power-down and Idle mode . . . . . . . . . . . . . . 4610 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 4711 Static characteristics. . . . . . . . . . . . . . . . . . . . 4812 Dynamic characteristics . . . . . . . . . . . . . . . . . 5012.1 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 5213 Other characteristics . . . . . . . . . . . . . . . . . . . . 5313.1 Comparator electrical characteristics . . . . . . . 5313.2 A/D converter electrical characteristics. . . . . . 5314 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 5415 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 5716 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 5817 Legal information. . . . . . . . . . . . . . . . . . . . . . . 5917.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 5917.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5917.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 5917.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 5918 Contact information. . . . . . . . . . . . . . . . . . . . . 5919 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

© NXP B.V. 2007. All rights reserved.For more information, please visit: http://www.nxp.comFor sales office addresses, please send an email to: [email protected]

Date of release: 10 July 2007

Document identifier: P89LPC9102_9103_9107_3

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.

Date post:	26-Jul-2020
Category:	Documents
Upload:	others
View:	1 times
Download:	0 times

P89LPC9102/9103/9107 8-bit microcontrollers with two-clock ... · The P89LPC9102/9103/9107 are...

Documents