IEEE International High Speed Interconnects Symposium, April 30, 2013 IEEE International High Speed Interconnects Symposium, April 30, 2013
Packaging Challenges for High Speed Analog Devices
Ben Sutton, Matt Romig, Souvik Mukherjee, Sreenivasan Koduri
Texas Instruments
April 30, 2013
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IEEE International High Speed Interconnects Symposium, April 30, 2013 IEEE International High Speed Interconnects Symposium, April 30, 2013
Agenda
• What is high speed Analog?
• What is packaging?
• Co-design of Die, Package, and System
• Specific Example: 7 GHz QFN
• Summary
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IEEE International High Speed Interconnects Symposium, April 30, 2013 IEEE International High Speed Interconnects Symposium, April 30, 2013
What is Analog?
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Embedded
Processing
IEEE International High Speed Interconnects Symposium, April 30, 2013 IEEE International High Speed Interconnects Symposium, April 30, 2013
What is High Speed Analog?
High
Speed
ADC
High
Speed
DAC
RF
Optics
uWaves
RF
Optics
uWave
SERDES
HDMI
USB3.0
Thunderbolt
DDR3/4
Switches
SATA
ESD
Embedded
Processing
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High-Speed
Current Switching
IEEE International High Speed Interconnects Symposium, April 30, 2013
WHAT IS PACKAGING?
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IEEE International High Speed Interconnects Symposium, April 30, 2013
• Old Days
– R is small
– ωL is small since frequency is low
– 1/(ωC) is large
– Package behaves like a small resistor
Simple RLC Section
• Nowadays
– R ∝ 𝑓
– ωL is large
– 1/ (ωC) is small
– Package behaves like a waveguide
– Package reflects signals if mismatched
What is Packaging, Electrically Speaking?
At 1 MHz:
- R ~ 4 mΩ
- L ~ j5 mΩ
- C ~ -j3 MΩ
At 10 GHz:
- R ~ 350 mΩ
- L ~ j50 Ω
- C ~ -j300 Ω
IEEE International High Speed Interconnects Symposium, April 30, 2013 IEEE International High Speed Interconnects Symposium, April 30, 2013
Practical Challenges
Same Physics Challenge in Different Applications Different Solutions
VS
New Packaging Technologies
High Complexity
Long Development Cycle
Existing Packaging Technologies
Low Complexity
Short Development Cycle
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IEEE International High Speed Interconnects Symposium, April 30, 2013 IEEE International High Speed Interconnects Symposium, April 30, 2013
Broad Range of Packaging Most Popular Packaging Options
MicroStar Ultra Thin™ Land
Grid Array
Chip Scale Package
(u*UT LGA)
MicroStar JR ™
Chip Scale Pkg
(u*JR BGA)
MicroStar BGA ™
Chip Scale Tape BGA
(u*BGA)
Laminate Chip Scale BGA
(nFBGA) QFN
Heat Sink Thin
Quad Flatpack
(HTQFP)
Small Outline
No Leads
(SON)
Small Outline
Transistor Package
(SOT23)
Thin Quad
Flatpack
(TQFP)
Transistor
Outline
(TO236)
Mini Small
Outline
Package
(MSOP)
Shrink
Small Outline
Package
(SSOP)
Small Outline
Transistor
(SOT223)
Thin Shrink
Small Outline
Package
(TSSOP)
Surface Mount
Header
(DDPak)
Small
Outline
Integrated
Circuit
(SOIC)
Heat Slug Small
Outline
Integrated Circuit
Plastic Dual-In-Line
Package
(PDIP)
PowerPad
Small Outline
Package
(HSOP)
Transistor
Outline
(TO220)
Power
Small Outline
Package
(PSOP3)
Thermally Enhanced
BGAs
Wafer Scale
Package
(WSP)
Flip-Chip
Power Packages
Analog Mirror
Packages
Power Modules SOT-23 SC-70
ESV SON LLGA
U*BGA
WCSP
Miniature Plastic Packages
Multi-Row
QFN Multi-Die QFN
Stacked-Die
QFN
Chip-on-Lead QFN
Flip-Chip QFN
2 Stacked Dies +
6 Passives
2 Dies + 2Passives
Stacked Passives An LDO stacked on a
Passive 8
IEEE International High Speed Interconnects Symposium, April 30, 2013 IEEE International High Speed Interconnects Symposium, April 30, 2013
Two Emerging Packaging Types
Pb-Free
Solder
Backside Coat
Silicon Die
Routing Layer
Die Metal
WCSP: Wafer Chip Scale Package QFN: Quad Flat No-Lead Package 9
IEEE International High Speed Interconnects Symposium, April 30, 2013
CO-DESIGN OF DIE, PACKAGE, AND SYSTEM
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IEEE International High Speed Interconnects Symposium, April 30, 2013
Electrical Co-Design
Methodology of concurrently optimizing the system (viz. Die + Package +
PCB), early in the design phase, to:
Meet electrical performance in customer end-system
Enable use of off-the shelf packaging technology for the product/system thru
better product/system spec definition
Reduce physical design spins of Si/Package/PCB faster time-to-market
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Signal Path
Integrity
Power
Management EMI/EMC
Compliance
Electrical Co-Design Applications
High-speed SerDes,
DDRs, Re-timers
Consumer interfaces (USB3/HDMI/DSI)
Signal Path Switches
RF Transceiver paths
Switched Mode Power ICs
Isolated Power ICs
High-Speed SerDes
Memory Interfaces (DDRs)
Integrated Digital-RF SOCs
Switched Mode Power Supplies
Consumer Analog
MEMS
IEEE International High Speed Interconnects Symposium, April 30, 2013 IEEE International High Speed Interconnects Symposium, April 30, 2013
3D current density Analysis in
RF Test-vehicle
Static IR drop analysis
of FCCSP Package
Model-to-Hardware Correlation
3D Modeling of Multi-layer WB
PBGA Package
3D Modeling of Package +PCB
Electrical Modeling Capabilities
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Scalability Accuracy Breadth
IEEE International High Speed Interconnects Symposium, April 30, 2013
Model-to-Hardware Correlation for WB BGA
Custom Die Package
Extensive efforts and collaboration constantly calibrate modeling flows/tools against
measurements. 13
IEEE International High Speed Interconnects Symposium, April 30, 2013
CASE STUDY – 7 GHZ IN A QFN
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IEEE International High Speed Interconnects Symposium, April 30, 2013 IEEE International High Speed Interconnects Symposium, April 30, 2013
Design Challenge
• Bandwidth Goal: 3dB >5GHz
• Application: FET Switch, 2-Ch
• Design Cycle: 3 Months
Despite low device complexity,
design challenge is significant:
– Package size limits
optimization of wire length
– Differential signaling requires
good coupling between P/N
– Design cycle drives single-pass
success
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IEEE International High Speed Interconnects Symposium, April 30, 2013 IEEE International High Speed Interconnects Symposium, April 30, 2013
Design Process
1. Reduce Parasitics
– Bondpad Geometry:
– Bondpad Placement:
– Moving bondpads toward the center of the die reduces capacitance and
resistance on the die while improving flexibility for reducing P/N skew
2. Package Modeling
– Full-wave package modeling captures package behavior out past 7th
harmonic of the signal
• Capturing references and return path properly is key for accuracy
– Design of the leadframe has a major impact on performance
3. Tune Silicon Design
4. Repeat
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IEEE International High Speed Interconnects Symposium, April 30, 2013 IEEE International High Speed Interconnects Symposium, April 30, 2013
Leadframe Contribution
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Design on Left: ~75% larger bandwidth!
IEEE International High Speed Interconnects Symposium, April 30, 2013 IEEE International High Speed Interconnects Symposium, April 30, 2013
Probe Measurement Performance
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RSE RLS
Leadframe Bandwidth
RSE 6.8 GHz
RLS 6.2 GHz
IEEE International High Speed Interconnects Symposium, April 30, 2013 IEEE International High Speed Interconnects Symposium, April 30, 2013
Summary
• Analog semiconductor devices face a significant challenge when it
comes to packaging interconnect as frequencies push towards 10’s of
GHz
• Miniaturization and aggressive market schedules drive re-use of simple,
existing packaging technologies, and place physical design constraints
on the package internals
• These challenges can be met through precise package modeling and
co-design with the silicon – a system-level, coupled approach.
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