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PADSPower Aware Distributed SystemsMiddleware Techniques and Tools
USC Information Sciences InstituteBrian Schott, Bob Parker
UCLAMani Srivastava
Rockwell Science CenterCharles Chien
PADS Project
Q: How can you extend the dynamic power range of sensor networks from quiescent months of monitoring to frenetic minutes of activity?
Architectural Approaches Power Aware Research Platform Testbed Deployable Power Aware Sensor Platform
Middleware, Tools, and Techniques Power Aware Resource Scheduling in RTOS Techniques for Network-Wide Power Management
Power Aware Algorithms Multi-Resolution Distributed Algorithms
UCLA
Introduction to UCLA PADS Team
PI Mani Srivastava
Other faculty Rajesh Gupta
Students Sung Park, Pavan Kumar, Paleologos Spanos, Vijay Raghunathan,
Cristiano Ligieri, and Ravindra Jejurikar
Research Agenda
Broad goals Middleware techniques for “JIT” power through coordinated scheduling and
power management of computing and communication resources locally at a sensor node (RTOS) as well as globally in a sensor network (protocols)
Tools for evaluating and designing the power management techniques Target 10-30x gain in power efficiency
Specific subtasks Power management within a sensor node
Power-aware RTOS scheduling under timing constraints Resource management with energy-speed and energy-accuracy control knobs Tools for RTOS power management evaluation, and power-aware kernel synthesis
Network-wide power management Network resource allocation for global power management Power-aware network protocols Hybrid sensor network simulation framework for power vs. quality evaluation of
network level power management techniques and protocols Power management with multimedia sensor data
Power characterization, extension of PADS techniques to streaming multimedia Integration with sensor nodes (Rockwell nodes, research platform)
Accomplishments Since Last Review
I. Power measurement, analysis, and modeling Power models for SensorSim Power analysis of various nodes in the lab
II. Power management of sensor node processor via RTOS Adaptive power-fidelity trade-off via prediction of run-time Implementation on eCos Validation on multimedia and sensor processing tasks Development of generic API to power-aware OS (on-going) Tools to evaluate power management strategies (on-going)
III. Power management of sensor node radio Development of the “dynamic modulation scaling” concept Various energy-aware wireless packet scheduling techniques
IV. Power-aware sensor node architecture Energy-efficient packet forwarding architecture for sensor nodes Experimental validation via lab prototype
V. Publications One at International Conference on VLSI Design (published) Three at ISLPED (accepted) One at Sigmetrics (accepted) One at Winter Simulation Conference (accepted) Some more submitted
I. Sensor Network Power Measurement, Analysis & Modeling
Data from SensITExperiments
DAQ
Power Measurements
SensorSimSimulator
SensorViz
Node LocationsTarget TrajectoriesSensor ReadingsUser TrajectoriesQuery Traffic
Power Models
SensorSim Architecture
Target Node
Sensor Layer
Physical Layer
Sensor Stack
Sensor Channel
Target Application
Wireless Channel
User ApplicationUser Node
Network Layer
Physical Layer
Network Stack
MAC Layer
Sensor Layer
Physical Layer
Sensor Stack3
Sensor Layer
Physical Layer
Sensor Stack2
Functional Model Sensor Node
SensorWarePower Model
Battery Model
Radio
CPU
ADC(Sensor)
Wireless Channel
Sensor Channel1
Network Layer
MAC Layer
Physical Layer
Network Stack
Sensor Layer
Physical Layer
Sensor Stack1
Sensor App
Sensor Channel2
Sensor Channel3Sensor Node
Sensor NodeSensor
Node
WirelessChannel
SensorChannel
UserNode
TargetNode
Power analysis of sensor nodes: Where does the power go?
High-end sensor node: Rockwell WINS nodes StrongARM processor Connexant’s RDSSS9M 900MHz DECT radio (128 kbps, ~ 100m) Seismic sensor
Low-end sensor node: Experimental node similar to Berkeley’s COTS motes Atmel AS90LS8535 microcontroller RF Monolithic’s DR3000 radio (2.4, 19.2, 115 kbps, ~ 10-30m) No sensors (but microcontroller has ADC)
Power Analysis of Rockwell’s WINS Nodes (Measurements)
Processor Seismic Sensor Radio Power (mW)Active On Rx 751.6Active On Idle 727.5Active On Sleep 416.3Active On Removed 383.3Sleep On Removed 64.0Active Removed Removed 360.0Active On Tx (36.3 mW) 1080.5
Tx (27.5 mW) 1033.3Tx (19.1 mW) 986.0Tx (13.8 mW) 942.6Tx (10.0 mW) 910.9Tx (3.47 mW) 815.5Tx (2.51 mW) 807.5Tx (1.78 mW) 799.5Tx (1.32 mW) 791.5Tx (0.955 mW) 787.5Tx (0.437 mW) 775.5Tx (0.302 mW) 773.9Tx (0.229 mW) 772.7Tx (0.158 mW) 771.5Tx (0.117 mW) 771.1
Summary Processor
Active = 360 mW doing repeated
transmit/receive Sleep = 41 mW Off = 0.9 mW
Sensor = 23 mW Processor : Tx = 1 : 2 Processor : Rx = 1 : 1 Total Tx : Rx = 4 : 3 at
maximum range comparable at lower Tx
Power Analysis of Experimental Node (Measurements)
Mode Power Level OOK @ 2.4 kbps OOK @ 19.2kbps ASK @ 2.4 kbps ASK @ 19.2kbpsTx 0.7368 14.88 15.67 16.85 17.76Tx 0.5506 13.96 14.62 15.80 16.85Tx 0.3972 12.76 13.56 14.75 15.54Tx 0.3307 12.23 13.16 14.35 15.15Tx 0.2396 11.43 12.23 13.43 14.35Tx 0.0979 9.54 10.35 11.56 12.36Rx 12.5 12.50 12.50 12.50Idle 12.36 12.36 12.36 12.36Sleep 0.016 0.016 0.016 0.016
8
10
12
14
16
18
20
1 2 3 4 5 6
Tx Pow er Level
Co
nsu
med
Po
wer
(m
W)
2.4kpbs OOK
2.4kbps ASK
19.2kbps OOK
19.2kbps ASK
Receive Mode
Note All powers in mW Microcontroller (with
ADC) Active = 8.7 mW Idle = 5.9 mW Off = 3 W
Some Observations from Power Analysis
In WINS node, radio consumes 33 mW in “sleep” vs. “removed” Argues for module level power shutdown
Tx and Rx power Rx power within 40% of maximum Tx power Under certain circumstances, Tx power < Rx power! Argues for:
MAC protocols that do not “listen” a lot Low-power paging (wakeup) channel
Processor power fairly significant (30-50%) share of overall power
Sensor transducer power negligible Use sensors to provide wakeup signal for processor and radio
Understanding Battery Lifetime & Impact of DC-DC Regulator
O perating Mode
Total Lifetime
Capacity (in mAh) consumed from Battery
Capacity (in mAh) delivered to Sensor
Energy (in Joules) consumed from Battery
Energy (in Joules) delivered to Sensor
DC/DC converter efficiencyTx .33 hr 8.1 4.1 70.0 49.1 70%
Rx .88 hr 15.8 7.9 135.2 96.1 71%
Idle 1.2 hr 18.0 9.0 154.0 109.0 71%
Sleep 7.0 hrs 59.1 28.8 505.1 350.7 69%
++ ++ - - - -
Chan 2Chan 1 Chan 3 Chan 4
DR 3000Sensor
AS90LS8535
DC/DCConverter
Rtest
Battery
Rtest
II. Power Management for Wireless Sensor Node Processor
Sensors RadioCPU
(Minimalist) Real Time Operating System
Power Manager
Dynamic Voltage Scaling
Scalable Signal
Processing
Dynamic Modulation
Scaling
Coordinated Power Management
Predictive DVS for Adaptive CPU Power-Fidelity Tradeoff
Power aware RTOS for embedded applications
Wireless systems resilient to packet loss
Time varying computational load Proactive DVS strategy involving
prediction of task instance runtime
Up to 75% reduction in energy over worst case based voltage scheduling with negligible loss in fidelity (up to 4% deadline misses) on variety of multimedia and signal processing tasks
0
0.1
0.2
0.3
0.4
0.5
0.6
0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
Shutdown
Non-predictive DVS
Predictive DVS
Nor
mal
ized
en
ergy
Average Exec. Time / Worst Case Exec. Time
Implementation
Implemented under eCoS using Intel’s Assabett board DVS-enabled eCoS on iPaQ to be ready soon
Power-aware API
eCoS
Application Threads
Power-Management Functions
DVS HAL
Normal eCoS System Calls
PowerRelated
Task DataStructures
Hardware
Power-awareTask Scheduler
To OS:task: set period, set deadline, set WCET, set actual remaining execution time, set hard/soft, create task instanceinterrupt handler: create task instance
To Task Instance:get remaining execution time, kill
Why? Ease of porting to different processors
Allow apples-to-apples comparison on the same set of applications
Tool to Evaluate PowerManagement Strategies
Current approach: simulation Simulation framework using PARSEC to compare different power
management strategies under various types of task schedulers Problem: long simulations, biased by choice of specific task set
Ongoing: analysis-based tool Based on “competitive analysis” to derive worst case bounds on
improvement yielded by a power management strategy metric: competitive ratio = how much worse than optimal off-line strategy
Take into account transition cost (power, time) Implementation based on formal model checking tool which is used as
a simulator for power management policy Problems: excessive memory hog, only a bound
Future: integrate analysis and simulation
III. Dynamic Power Management of Sensor Node Radios
Sensors RadioCPU
(Minimalist) Real Time Operating System
Power Manager
Dynamic Voltage Scaling
Scalable Signal
Processing
Dynamic Modulation
Scaling
Coordinated Power Management
Tbit (s)
RS (MHz)
b
Ebit (J)
RS (MHz)b
Dynamic Modulation Scaling
Energy and delay of data transmission depend on modulation settings
Tradeoffs for QAM adapt b (number of bits per
symbol) Operate at maximum RS that can
be implemented efficiently
Similar tradeoffs are possible for other scalable modulation schemes PSK, DPSK ASK OFDM
bitESbit TPPE
Analogy Between Dynamic Voltage and Modulation Scaling
Scaling modulation on the fly results in energy awareness
Strong analogy between modulation scaling and voltage scaling Low power techniques, like parallelism Packet scheduling like task scheduling Other power management techniques
Ebit (J)
Tbit (s)
b = 6
b = 4
b = 2
leakageP selectronicP
switchingP transmitP
operationE bitE
V b
f Rb
Voltage scaling
Modulation scaling
Analogy Between Dynamic Voltage and Modulation Scaling
b
RGCPb
BSSS
12
b
RCCP B
REE
maxmax
11
TRb
TR
SB
B
ES RPPE
1
2VfCP LS
TnV
V
L eIVP 0
f
k
C
V
VVf
tLT
d
21
f
PPE LS
1
Radio Digital Hardware
Tav (s)
Eav (J)
Queue-Based Dynamic Modulation Scaling
Radio Dynamic Power Management (R-DPM) for best-effort data packet service
Adapt modulation based on number of packets in the queue
RadioQueue
Processor
R-DPM
Different {queue, b}-settings result in different points on the energy-delay tradeoff
Energy Aware Real Time Packet Scheduling
Analogous to RTOS task scheduling
Exploit variation in packet length to perform aggressive DMS
Up to 69% reduction in transmission energy
Framework for coordinated power management of computing and communication sub-systems
Lavg/Lmax
En
ergy
sav
ings
(%
)
staticdyn stretch
staticdyn static
Data Combining versus Modulation Scaling
Data combining Gains depend on correlation in time or space Reduction in packet size or increase in reliability
Modulation scaling
Overall tradeoff
escaling (J/packet.hop)
tscaling (s/packet.hop)
Modulation scaling tradeoff
0
0.5
1
0 1 2
ecomb
tcomb
Data combining tradeoff
Combining
scalingcombnode eeE
scalinghopscombcyclepacket tNtTT
IV. Power-aware Sensor Node Architecture
Problem: radio often simply relays packets in multihop network NS-2 simulation: 1000x1000 terrain, 30 nodes, DSR, CBR traffic from
random SRC and DEST
Traditional approach: main CPU woken up, packets sent to it across serial bus power hungry computing and communication operations
CommunicationSubsystem
RadioModem
GPS
MicroController
Rest of the Node
CPU Sensor
MultihopPacket
Traditional Approach
Action % of received packets
ACCEPT 34.300
FORWARD 65.567
DROP 0.133
…zZZ
Energy Impact of Our Packet Forwarding Architecture
Simple packet processor in the radio
Packets are redirected as low in the protocol stack as possible Measured + simulated results using Atmel AVR and Triscend E520 with
Rockwell Nodes Lower latency (44 ms)
once PrFW > 3% PrAC
Lower energy (savings) Average of 17.5 mJ/packet with Atmel AVR Average of 7.5 mJ/packet with Triscend E520
CommunicationSubsystem
RadioModem
GPS
MicroController
Rest of the Node
CPU Sensor
MultihopPacket
Our Approach
Energy Savings
Difference in Energy consumption is also dominated by the Serial port crossing penalty and the relation () of the power consumption of the Microcontroller and the Sensor CPU
FWMCUMCUFWCPUFWSR
ACMCUMCUACCPUAC
FNFdiff
PDDD
PDD
EEE
Pr12
Pr
Energy difference due to ACCEPT
Energy difference due to FWD
Serial Port crossover penalty
MCUCPU PP CPU MCU
WINS (351mW) Atmel AVR (15mW) 23.4
WINS (351mW) E520 (470mW) 0.747
Ediff 1167*PMCU
16*PMCU
For Simulation Data
Near-term (Summer) Plans
Power-management of CPUs Power analysis of SA-2 with variable voltage
Soon getting SA-2 board being donated by Intel Finish power-aware API
Power-management of radios Further development of energy-aware packet scheduling Better understanding its utility So far power management under traffic variations only
Next: combine traffic and channel variations Some validation using prototype, perhaps using FPGA
Coordinated CPU& radio power management Modeling
ARL sensor data and algorithms Incorporate into sensorsim
Combined modeling of CPU and radio power consumption(Joulestrack + Sensorsim?)
Node architecture SA-2 and TMS320C55