PAN1321 Application Note DesignGuide - Panasonic Devices, Inc. SIRIUS of Sirius Sattelite Radio Inc....

Wireless Solut ions

PAN1321 A p p l i c a t i o n N o t e D e s i g n G u i d e Version 2.2

PAN1321

Template: central_a4_template_20090126.dot / 3.00 / 2009-01-26

PAN13x1

Revision History: 2011-11-1, Revision 2.2

Revision History: 2009-08-06, Revision 2.1

Previous Revision: 2009-04-08, Revision 2.0

Page Subjects (major changes since last revision)

9 Added: The size of the EEPROM is 256 kbit.

12 Section 3.2: Important hints for using ONOFF pin to power down the device.

13 Footnotes about the usage of ONOFF pin.

14 Reference design schematic: VDDPCM -> VDD1.

Trademarks of Infineon Technologies AG

APOXI™, BlueMoon™, COMNEON™, CONVERGATE™, COSIC™, C166™, CROSSAVE™, CanPAK™, CIPOS™, CoolMOS™, CoolSET™, CORECONTROL™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, EUPEC™, FCOS™, FALC™, GEMINAX™, GOLDMOS™, HITFET™, HybridPACK™, ISAC™, ISOFACE™, IsoPACK™, my-d™, MIPAQ™, ModSTACK™, NovalithIC™, OmniTune™, OmniVia™, OPTIVERSE™, OptiMOS™, ORIGA™, PROFET™, PRO-SIL™, PrimePACK™, RASIC™, ReverSave™, SCEPTRE™, SEROCCO™, SICOFI™, SMARTi™, SMINT™, SOCRATES™, SatRIC™, SensoNor™, SINDRION™, SmartLEWIS™, SIEGET™, TrueNTRY™, TEMPFET™, TriCore™, thinQ!™, TRENCHSTOP™, VINAX™, VINETIC™, X-GOLD™, XMM™, X-PMU™, XPOSYS™, XWAY™.

Other Trademarks

AMBA™, ARM™, MULTI-ICE™, PRIMECELL™, REALVIEW™, THUMB™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO. OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Sattelite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.

The information in this document is subject to change without notice.

Last Trademarks Update 2009-05-27

PAN1321

Application Note 3 Revision 2.12, 2009-08-06 Design Guide

Table of Contents

1 Introduction ........................................................................................................................................6

2 Interfaces ............................................................................................................................................7

2.1 UART Interface.....................................................................................................................................7

2.2 EEPROM / I2C Interface ....................................................................................................................10

2.3 GPIO Interface ...................................................................................................................................10

2.4 JTAG Interface ...................................................................................................................................10

3 Power Supply....................................................................................................................................11

3.1 Power up Sequence...........................................................................................................................11

3.2 Power down through ONOFF Pin ......................................................................................................12

4 Reference Design Schematic..........................................................................................................14

5 Layout................................................................................................................................................18

5.1 Phase1: Layer Assignment ...............................................................................................................18

5.1.1 Via Holes ............................................................................................................................................19

5.2 Phase 2: Components Placement.....................................................................................................19

5.3 Phase 3: Routing...............................................................................................................................20

5.3.1 Basic Hints .........................................................................................................................................20

5.3.2 Layout Specific Hints..........................................................................................................................21

6 Antenna .............................................................................................................................................25

7 FAQs..................................................................................................................................................29

7.1 Preparation for RF Tests....................................................................................................................29

7.2 Crystal Trimming ................................................................................................................................31

7.2.1 Osc_Trim Parameter..........................................................................................................................31

7.2.2 Crystal Trimming Procedure ..............................................................................................................31

7.2.2.1 Crystal Trimming for RF Tests ...........................................................................................................32

7.2.2.2 Crystal Trimming with SPP-AT Application........................................................................................34

7.3 Connection to CMU/CBT through Antenna Link ................................................................................35

7.4 Frequency Modulation and DEVM Failures .......................................................................................37

8 References ........................................................................................................................................40

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List of Figures

Figure 1 Simplified Block Diagram of PAN13x1 Module ....................................................................................7

Figure 2 UART Interface.....................................................................................................................................8

Figure 3 Host Initiates Low Power Mode Entry and Exit ....................................................................................9

Figure 4 Host Initiates Low Power Mode Entry, PAN13x1 Initiates Exit ............................................................9

Figure 5 EEPROM Access at Start-up .............................................................................................................12

Figure 6 Reference Design...............................................................................................................................18

Figure 7 Stackup of PAN13x1 USB Dongle .....................................................................................................18

Figure 8 Via Types ...........................................................................................................................................19

Figure 9 3W Rule for Microstrip........................................................................................................................20

Figure 10 Use of Guard Traces..........................................................................................................................21

Figure 11 Example of Good Grounding: Mid Layer 1 of UniStone CF Card ......................................................22

Figure 12 Poor Grounding on Mid Layer 1 .........................................................................................................23

Figure 13 Example: Dead Copper on Inner Layer .............................................................................................24

Figure 14 Layers of the PAN13x1 USB Dongle .................................................................................................25

Figure 15 Geometry of IFA Antenna ..................................................................................................................26

Figure 16 Printed IFA on PAN13x1 USB Dongle ...............................................................................................27

Figure 17 Dimensions of the Printed IFA on the USB Dongle ...........................................................................28

Figure 18 Download of HCI Application via UART.............................................................................................30

Figure 19 Crystal Trimming using HCI Lite Tool ................................................................................................32

Figure 20 Infineon Write BD-Data Window ........................................................................................................33

Figure 21 Crystal Trimming using eBMU SPP Toolbox .....................................................................................35

Figure 22 Start Transmission of CW Unmodulated Signal using HCI Lite .........................................................36

Figure 23 Start Frequency Modulation using HCI Lite .......................................................................................38

Figure 24 CW TX with All 1s Modulation Spectrum ...........................................................................................39

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List of Tables

Table 1 Default Pin Configuration ...................................................................................................................14

Table 2 Register for Switching Capacitances .................................................................................................31

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1 Introduction

The PAN1311 and PAN1321 are modules based on Intel’s PMB 8753/2 (eBMU), an integrated BT radio transceiver and baseband, with a band filter and EEPROM. The PAN1311 is designed to be operated with an antenna externa to the module, while the PAN1321 includes and integrated ceramic antenna. The PAN1311 and PAN1321 are automoms modules that include a Bluetooth stack and Serial Port Profile (SPP), no external components are needed for operation.

PAN13x1 supports the following Bluetooth features

• Bluetooth v2.0 + EDR compliant.

• Device A and B support 1 ACL link with stream or command mode.

• Device A and B - Visible while connected.

• Device A and B - Visible/connectable when not connected.

• Device A and B - Device Discovery capable after receiving OK on data transfer.

• Sniff mode is supported with above capabilities.

• 5 trusted devices stored in EEPROM.

• Enable DUT.

• Crystal calibration.

• H4 with UART HW flow control (RTS/CTS).

• Security modes 1 and 3.

The construction of the PAN13x1 module is shown in the block diagram below.

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Figure 1 Simplified Block Diagram of PAN13x1 Module

2 Interfaces

2.1 UART Interface

The UART interface is the main communication interface between the host and PAN13x1. For the SPP application, communication between the host and the PAN13x1 is through AT commands over the UART interface.

The interface consists of four UART signals for the AT interface and two GPIOs for additional low power mode control, as shown in Figure 2.

The use of low power mode (LPM) control is optional. If not used, P0.14 should be tied to VDDUART.

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Figure 2 UART Interface

The low power mode protocol for PAN13x1 is based on hardware signaling only. No SPP commands or responses are required for the low power mode protocol. The two GPIOs are used to tell the other device (host or controller) when it may enter low power mode, when it should wake up and when it cannot transmit because the other device is in low power mode.

To allow the PAN13x1 to enter low power mode, the host sets PIN P0.14 low. When PAN13x1 is ready, it will also allow the host to enter LPM by setting P0.0 low. Before entering LPM, the host shall set UART CTS of PAN13x1 high. Before entering LPM, PAN13x1 will set its own UART RTS high.

The host can wake up PAN13x1 by setting UARTCTS of PAN13x1 low again and setting P0.14 high again, whereas the PAN13x1 can wake up the host by setting its own UART RTS low again and setting P0.0 high again.

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Figure 3 shows shows a case where the host initiates low power mode entry and exit.

Host PAN13x1

Host Output

GPIO 0.14

Host RTS UARTCTS

Host Input GPIO 0.00

Host CTS UARTRTS

Figure 3 Host Initiates Low Power Mode Entry and Exit

1. The host allows PAN13x1 to enter low power mode 2. PAN13x1 enters low power mode 3. PAN13x1 allows the host to enter low power mode, the host may, if it can, enter low power mode 4. The host requests the PAN13x1 to wake up 5. PAN13x1 wakes up

Figure 4 shows shows a case where the host initiates low power mode and the controller wakes up the host.

Host PAN13x1

Host Output

GPIO 0.14

Host RTS UARTCTS

Host Input GPIO 0.00

Host CTS UARTRTS

Figure 4 Host Initiates Low Power Mode Entry, PAN13x1 Initiates Exit

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1. The host allows PAN13x1 to enter low power mode 2. PAN13x1 enters low power mode 3. PAN13x1 allows the host to enter low power mode 4. The host enters low power mode 5. PAN13x1 requests the host to wake up 6. The host wakes up

2.2 EEPROM / I2C Interface

As shown in the block diagram ( Figure 1), the PAN13x1 module is equipped with an EEPROM for storage of the non-volatile information. The size of the EEPROM is 256 kbit.

The EEPROM contains the following partitions:

• The Bluetooth Device Data (BD_DATA) Storage

• The Application and patches to the firmware

• Application data (any application specific data)

• Production default values

On the module, the communication between the eBMU PMB 8753/2 and the EEPROM is carried through a standard I2C bus. The I2C bus is also accessible from external, which is useful in the development or debug phase in case the EEPROM gets corrupted.

2.3 GPIO Interface

Most digital pins on PAN13x1 can be used as general purpose I/Os (GPIOs). The GPIO pins are grouped into two ports: P0 and P1. P0 has 16 pins (P0.0 - P0.15) and P1 has nine pins (P1.0 - P1.8).

2.4 JTAG Interface

The pins used for the JTAG interface (TDI, TDO, TMS, TCK and RTCK) can also be used as general purpose I/Os. The operative interface (JTAG or GPIO) on these pins can be selected through the mode selection pin JTAG#. When JTAG# is connected to low, the pins are used for JTAG interface. When JTAG# is connected to high, the pins serve as GPIO pins.

JTAG# has an internal pullup. If the JTAG functionality is not needed, leave this pin open.

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3 Power Supply

• Main supply voltages (VSUPPLY1, VSUPPLY2 and VSUPPLY3) are required in the range from 2.9V to 4.1V. All these supplies are internally connected. It is only necessary to supply one of them.

• VDDUART defines the reference level for UART interface. It can be − supplied externally. In this case voltages between 1.35 and 3.6 V are required. − connected to the internal regulator, voltage “Internal 2” on pin VREG (pin No. C1), if 2.5 V is enough for

UART operation (of course, voltage levels of the digital signals on the UART interface depends from this supply voltage). Ultimately, this depends on the host. Note: The state of UART pins is not defined while VDDUART is not supplied. The host shall not drive any

UART pin before the reference levels are stable.

• VDD1 defines the reference level for ports P0.0-P0.3. It can be − supplied externally. In this case voltages between 1.35 and 3.6 V are required. − connected to the internal regulator, voltage “Internal 2” on pin VREG (pin No. C1), if not used.

Note: The state of pins P0.0-P0.3 is not defined while VDD1 is not supplied. The host shall not drive any of these pins before the reference levels are stable.

3.1 Power up Sequence

The eBMU accesses the EEPROM to load the BD-Data and the application data during startup. The EEPROM access starts at 22 ms after the RESET# pin is pulled high. Power dropouts within the first 27 ms of the start-up phase can cause EEPROM data corruption. If power falls below the EEPROM’s minimum supply level during the startup phase, a reset shall be applied immediately.

The eBMU accesses the EEPROM to load the BD-Data and the application data during startup. The EEPROM access starts at 22 ms after the RESET# pin is pulled high. The sequence of the EEPROM accesses at start-up is shown in Figure 5. During the EEPROM access, UARTRTS stays high. When the EEPROM access has finished, the UARTRTS signal is pulled down and a startup response “ROK” is sent via UART to the host. After receiving the startup response, the host is informed that the PAN13x1 module is ready to work.

The range for the startup time is indiated for each application SW release in the Release Notes [3].

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Figure 5 EEPROM Access at Start-up

3.2 Power down through ONOFF Pin

If VSUPPLY, VDDUART and VDD1 are supplied by the same source, it is not possible to switch off the module with the ONOFF signal.

When the ONOFF pin is driven low, the reference levels VDDUART and VDD1 must also be switched off. Otherwise the module would draw current from VDDUART and VDD1, and the output pins would be “undefined”, i.e. they could drive high or low levels or vary periodically.

One option is to supply VDDUART and VDD1 by pin C1 VREG which connects to the “Internal2” voltage. Internal2 is switched off when ONOFF goes low. VSUPPLY can remain always on. Precondition for this is that the host’s UART pins are compatible with the logical levels for Internal2 driven pins indicated in the data sheet: Input Low max 0.45 V, Output High min 2.1 V. See “Table 18 Internal2 (2.5 V) Supplied Pins” in the data sheet [4] for full spec.

RESET#

SCL0

UARTRTS

UARTTXD

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If ONOFF is not used, it should be connected to VSUPPLY.

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4 Reference Design Schematic

The reference design schematic is shown in Figure 6.

• VSUPPLY1, VSUPPLY2, VSUPPLY3, VDDUART and VDD1 can be supplied by the same 3.3 V voltage.1

• C1, C4 and C5 are not placed. They only need to be placed in case noise is present from the power supply.

• Pins VSS1 to VSS11 must be connected to ground.

• Pins NC1 to NC7 are internally not connected and can be left open.

• Since the internal LPO (low power oscillator) is used by the module then the CLK32 pin can be left open.

• Is strongly suggested having test point on SDA and SCL. These can be useful for debugging purpose.

• A test point on P0.1 or P0.8 is needed for crystal calibration in case the pre-stored value is lost and for the HCI application for RF Testing.

• The line UARTRXD and UARTCTS must remain high during low power mode. If the host can not drive them all the time, a pull-up might be needed. For debugging, test points on the UART lines can be helpful. .

• If JTAG interface is not used, JTAG# pin can be kept open (internal pull up). In this case GPIO port 1

(configurable GPIO) is available on JTAG pins. To enable JTAG interface, a 4.7 kΩ pull down resistor must be put on this pin.

• RESET# pin should be driven by the host.

• ONOFF pin must be connected to VSUPPLY, if it is not used.2

• If LPM wakeup input P0.14 is not used, it must be pulled up to VDDUART.

• If LPM wakeup output P0.0 is not used, it can be left open.

• An impedance matching circuit using a series and a shunt component is placed on antenna trace. This can be useful for antenna matching and for the issue described in paragraph 7.4.

These points are summarized in Table 1.

Table 1 Default Pin Configuration

Interface Pin Name Note

UART F4 P0.14 If LPM is not used, this pin must be pulled up to VDDUART.

UART E4 P0.0 If LPM is not used, this pin can be left open.

UART E6 UARTRXD A 4.7 kΩ pull up resistor may be needed to keep level in LPM.

UART F6 UARTCTS A 4.7 kΩ pull up resistor may be needed to keep level in LPM.

A8 CLK32 Internal LPO is used; this pin can be left open.

B9 SLEEPX Not used. Leave open.

B5 ONOFF If not used, connect to VSUPPLY. 2

A3 RESET# Must be controlled by host I/O.

JTAG C3 JTAG# If JTAG interface is not used, this pin can be kept high; otherwise a

1 In that case the ONOFF pin can not be used and must be connected to VSUPPLY.

2 No reference level or input signal shall be applied to the module while ONOFF is low. Output signal levels are

not defined while ONOFF is low.

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4.7 kΩ pull down resistor must be used to enable JTAG.

JTAG B3 TMS / P1.0 If JTAG enabled: 4.7 kΩ pull up; otherwise: leave open.

JTAG D3 TCK / P1.1 If JTAG enabled: 4.7 kΩ pull up; otherwise: leave open.

JTAG F2 TDI / P1.2 If JTAG enabled: 4.7 kΩ pull up; otherwise: leave open.

JTAG B3 TDO / P1.3 If JTAG enabled: 4.7 kΩ pull up; otherwise: leave open.

JTAG B4 RTCK / P1.4 If JTAG enabled: 4.7 kΩ pull down; otherwise: leave open.

JTAG C4 TRST# If JTAG enabled: 4.7 kΩ pull down; otherwise: leave open.

The JTAG pull resistors are only needed during JTAG operation.They should be placed on the JTAG connector.

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Figure 6 Reference Design

5 Layout

Layout design can be devided into the following phases:

− Phase 1: layers assignment. − Phase 2: components placement. − Phase 3: routing.

5.1 Phase1: Layer Assignment

A correct assignment of the layers can avoid many RF issues. And can make the routing a lot easier.

Figure 7 shows the layer’s stackup of the PAN13x1 USB dongle. In this case, because the number of connections is very small, no special care is required in this phase:

− The top layer is reserved for components' placement, microstrip, antenna. If any needed, also for matching components.

− Mid layer 2 is used for power planes. − Mid layer 1 is used as RF ground. And to route some traces − Bottom layer is used for general grounding and to route the rest of the traces

Figure 7 Stackup of PAN13x1 USB Dongle

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5.1.1 Via Holes

Before to start with routing, the layouter must know what kinds of vias are available. The choice depends from budget considerations: microvias are the most expensive, through vias are the cheapest, the others are in the middle.

Figure 8 Via Types

Micro vias: they have a diameter between 50 µm and 100 µm and can be placed directly into the pads of BGA and similar components. The availability of this technology must be verified with the manufacturing factory. Because of the small diameter much PCB’s space can be saved and power and ground planes are less discontinuous.

Buried vias: they are connecting two or more inner layers (for example from 2nd

to 3rd

layer). The diameter is

≥ 100 µm. Since is not required to drill all the PCB they can help to save space for routing. They are also useful to design striplines. A stripline is an RF traces which has ground in the layers above and below the trace. To improve isolation between stripline a “wall” of vias between the two layers can be placed.

Blind vias: they are drilled from an outer layer to one of the inner layers. Blind vias are most efficient if used with

buried vias. The diameter is ≥ 100 µm.

Through vias: they are drilled from the top layer to the bottom layer, and have a typical diameter of 200-300 µm, all the inner layers can be connected to the via. Often are used to connect all the ground areas in the different layers.

When a trace that carry high current moves from one layer to another, more parallel vias are required. Placing more vias reduce the resistance of the overall connection.

Too high resistance in the power trace might lead to a not constant supply in TDMA system where the TX section is switched on only during the TX slot: when the power section is on, the IC is drawing high current, which produce a voltage drop in the trace, the supply is AM modulated, which ultimately might effects all the performances of the IC.

5.2 Phase 2: Components Placement

Placement of the components must be done following the order:

1. Place the connectors in the most rational way. For example, would be strange to have the USB connector in the longest side of the PCB.

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2. Place antenna and SMA connector. In general you want to keep the antenna away from other metal parts (for example the USB connector), and both antenna and SMA connector should be connected with the shortest path to the module. See paragraph 7 for hints on the antenna design.

3. Place all the other components in order to minimize track length and -if possible- keeping separate RF and baseband sections.

5.3 Phase 3: Routing

5.3.1 Basic Hints

Here are some basic hints on routing to avoid crosstalk. These are golden rules not only aplliable to PAN13x1, but to all designs:

• Group and route traces according to their functionality. Start routing RF lines and other sensitive lines.

• Minimize the length of parallel routed traces, in the same layers and in adjacent layer. In adjacent layers orthogonal routing - alternating horizontal and vertical routed layer - is helpful to avoid capacitive coupling between traces on different layers.

• Keep enough separation between traces. For RF traces the separation (edge to edge measured) should be at least one time the width of the microstrip (see Figure 9). By the way, simulation to analyze the coupling effects is suggested any time that RF traces are closely placed.

Figure 9 3W Rule for Microstrip

• Decoupling between RF traces can be provided also by placing ground vias between traces.

• Guard traces should be placed around high-threat traces (clock and periodic signals); guard traces must be connected to ground with the shortest path possible (see Figure 10).

• Try to minimize the length of connections, but only after all other requirements are fulfilled.

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Figure 10 Use of Guard Traces

5.3.2 Layout Specific Hints

1. Antenna trace must be a 50 Ω microstrip routed on Top layer with the RF return current path (usually called “ground layer”) on mid layer 1. Ground fill should not be placed too close to the microstrip (3W rule); otherwise also the effect of ground must be taken into account calculating the impedance (as a coplanar line).

2. Mid layer 1 should be used as a ground plane: a) Ground plane must be a continuous plane as large as possible, avoid to just “bring” the ground where is

needed. Figure 11 shows the Mid-layer 1 of a Unistone CF card. Here the ground is continuous and is interrupted only by via holes. Figure 12 shows the Mid-layer 1 of a bad routed board: the thick green trace is the ground connection. There the ground is brought where is needed a connection to ground, for example in the middle of the BT IC. Of course this is not acceptable, poor ground reference lead to poor performances.

b) PAN13x1 has several pins that must be connected to ground. Ideal would be to connect each pin with the ground underneath through via directly on pin. In case this cannot be done a trade-off must be found.

c) Remove dead copper. Small ground filling area, not connect to ground through vias, can have unwanted effect. They can behave as antenna, or like a coupling filter or other kind of unwished effects. For this reasons, if it is not possible to connect to ground with enough vias (in the example in Figure 13 one via on each side and one in the middle), it is suggested to be removed.

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Figure 11 Example of Good Grounding: Mid Layer 1 of UniStone CF Card

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Figure 12 Poor Grounding on Mid Layer 1

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Figure 13 Example: Dead Copper on Inner Layer

On the end of the layouting process the layers looks like in Figure 14.

As can be seen no impedence matching have been used on the dongle design as this have been proven to work effectively without it.

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Figure 14 Layers of the PAN13x1 USB Dongle

6 Antenna

The most important criteria for selection of the antenna are the following:

− Bandwidth − Efficiency − Size − Cost − Number of external parts required for matching

The antenna used in the CF card is a printed Inverted F Antenna (IFA). The IFA can be represented like in Figure 15.

Even if design of the IFA requires electromagnetic modeling/simulation, which are beyond the purpose of this text, a few considerations can be helpful for a practical approach to the design of the antenna:

1. In the extreme point right of the horizontal arm the current is zero because it is an open circuit; in the point connected to ground in the vertical arm the current is at maximum. This suggests the view of this antenna like a quarter wavelength transmission line. Tune the length (L+h) to center the resonant frequency on BT band. Increasing the length the resonant frequency decreases and vice versa.

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2. The tap point, where the antenna is fed, changes the impedance of the antenna viewed by the generator, but

also affects the center frequency. Change Lt to get a resistive 50 Ω antenna; after changing Lt a new fine-tuning on (L+h) is necessary.

3. An alternative approach is to view the antenna like a small loop inductor, consisting of the feed probe and the inverted L on the left of the feed, resonating with a capacitor, consisting of the horizontal wire (on the right of the feed) exposed to the ground plane.

Figure 15 Geometry of IFA Antenna

Advantages of IFA are:

− It does not cost any extra expense, because it is printed on the PCB board. The only impact on the cost of the antenna is the space on the PCB.

− Up to 5% BW can be achieved with IFA. Bluetooth BW is 3.3%. − The free space radiation efficiency is quite high (is possible to achieve up to 70% efficiency).

− It is quite easy to tune. No external components are required to match to 50 Ω.

The disadvantage of IFA is its sensitivity to detuning when in proximity of human body/head or plastic case of the device. A good design must take into account the detuning effect of the case; of course, it is more tough to take into account the effect of human body/head because of his discontinuous presence (on the other side can be decided a priori to optimize in presence of human body/head).

Figure 16 shows the printed IFA used on the PAN13x1 USB dongle. Left is the top layer of the PAN13x1 dongle whereas the bottom layer is on the right side. In order to increase the bandwidth, the antenna is printed on both the top and bottom layers. The top and bottom layers are connected by a row of through vias.

In Figure 17 the relevant dimensions of the antenna are demonstrated.

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Figure 16 Printed IFA on PAN13x1 USB Dongle

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Figure 17 Dimensions of the Printed IFA on the USB Dongle

It is important that the ground filling in proximity of the IFA is connected to the RF ground with via holes, otherwise it will act as a coupled component, drawing energy from the antenna.

Behavior of antenna is highly depending on surrounding metal part:

− Closeness of the ground plane (the capacitor of the horizontal arm change with ground plane). − Screws (can lower the efficiency). − Enclosure of the end device.

But is also dependant, in less evident way, from the size of the entire PCB. This happens because RF currents which circulate on the ground of the PCB contribute to the EM field as well.

Two important conclusions about the antenna design are to be summarized:

1. Infineon provides a reference design (antenna and microstrip) which can be copied. However because of all these dependencies of the antenna from the surrounding factors the complete design procedure for optimized results includes: a) EM simulations (the more complete is the model the more accurate are the results the more simulation

time/power is required). b) Prototyping and cut-and-try tuning approach.

2. Antenna performances must be tuned with all the parts (ICs, plastic support, device enclosure…) mounted to see the behavior in the real environment.

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7 FAQs

This chapter is aimed to clarify some common issues from the customers.

7.1 Preparation for RF Tests

To perform the RF tests, the eBMU device on the module has to be configured through HCI commands, which can only be executed on the eBMU HCI application. To use the HCI commands, the HCI application must be downloaded into the EEPROM of the PAN13x1 module.

Note: Once the HCI application as been loaded to the module, it can not be reprogrammed over the UART any more. An I2C programmer is needed to restore the module with the standard SPP application then.

The HCI application can be downloaded in 2 ways.

1. Via UART interface (if the SPP-AT application is downloaded in prior): a) Open eBMU SPP Toolbox and connect to device. b) Click “Testing” panel c) Switch production mode on. d) Click “Download Image”. e) Select image of HCI application and click “Download” (See Figure 18).

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Figure 18 Download of HCI Application via UART

2. Via I2C interface: Connect the AARDVARK Programmer and follow the instructions in [1].

When the HCI application is downloaded into EEPROM, issue a HW reset to load the HCI application into the eBMU RAM.

Note: It is important to read out and note the OSC_Trim value before download of the HCI application. Since the download procedure will overwrite the calibrated OSC_Trim value, the original OSC_Trim must be written back into the EEPROM after the download.

The HCI Lite tool provided by Infineon allows the configuration for RF transmission tests on the module.

After the RF tests are performed, the SPP-AT application must be downloaded into EEPROM again to enable the usage of eBMU SPP Toolbox. Since the SPP Toolbox can not work with the HCI application, the SPP-AT application can only be downloaded via I2C interface. This requires a specific I2C bridge. Please follow the instructions in [1].

PAN1321


7.2 Crystal Trimming

The parameter Osc_Trim in BD_Data is calibrated during production in factory. It is used to tune the crystal on the module at the right frequency. It makes use of parallel capacitors switched in and out in order to decrease or increase the clock frequency.

A wrong Osc_Trim value cause problem in

− UART communication with the host − Shifted TX frequency, which at the end can cause the failure of TX frequency accuracy test (TRM/CA/08/C

initial carrier frequency tolerance).

If the calibrated OSC_Trim value has been lost, the internal crystal must be calibrated again before performing any RF tests with the module or putting the module into any real application.

7.2.1 Osc_Trim Parameter

The Osc_trim parameter in the BD_Data is 10 Bits long and the bits 0 to 5 switch binary weighted capacitances from 1xLSB to 32xLSB, where LSB is 40fF. The bits 6 to 9 all have the same value of 2.56 pF each, which is 64xLSB each.

The following table shows the capacitance switched by each bit and how to get the value in hexadecimal notation.

Table 2 Register for Switching Capacitances

2560 2560 2560 2560 1280 640 320 160 80 40 Cap in fF

9 8 7 6 5 4 3 2 1 0 Bit

0 0 0 = 0 pF

1 9 F = 6.36 pF

3 F F = 12.76 pF

There are 10 internal capacitances between the pins LOAD and VSS and every bit of the array represents one of the capacitances. All of them are switchable so it is possible control whether they are connected or not. With setting a bit to 1 the capacitance is connected.

Table 2 shows 3 examples of a value for the Osc_Trim and the real capacitance. The first example is the minimum, the second the proposed start value for the tuning algorithm and the last the maximum achievable value. The frequency gets lower with a higher value of the capacitance array.

7.2.2 Crystal Trimming Procedure

A 32 MHz clock is derived internally from the crystal oscillator. It can be switched to the GPIO pin P0.1 or P0.8.

The reference signal must be adjusted with a precision that is determined by the total acceptable deviation of ±20 ppm for the Bluetooth reference clock. The sum of adjustment precision, variation over temperature and ageing must remain within this range. The best achievable precision for the reference clock adjustment is ±2 ppm (±64 Hz).

A frequency counter is needed that has a sufficient precision, for example the Agilent 53131A Universal counter.

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7.2.2.1 Crystal Trimming for RF Tests

After the download of the HCI application, the calibrated OSC_Trim value is overwritten with the default value. If the calibrated value has not been noted before the download, an additional crystal trimming must be performed before any RF tests.

A HCI tool named “HCI Lite” is provided by Infineon, with that the crystal trimming can be performed easily. The 32 MHz clock signal can be switched to GPIO pin P0.1 or P0.8 using the HCI Lite tool (see in Figure 19). Then the clock frequency can be measured by a frequency counter connected to the test pin.

Figure 19 Crystal Trimming using HCI Lite Tool

The crystal trimming procedure using a frequency counter and the HCI Lite tool is as following:

1. Make the 32 MHz clock available at P0.1 or P0.8 using the HCI_Lite tool. (See in Figure 19) f) Select P0.1 or P0.8 pin for output of the 32 MHz clock g) Click “Open port for 32 MHz”

2. Connect the frequency counter to the appropriate test pin P0.1 or P0.8. 3. The 32 MHz clock signal can now be measured by the frequency counter.

PAN1321


4. Write the trimming value to the Osc_Trim register through the HCI Lite tool. The start value is 0x19F. (See in Figure 19) a) Enter the Osc_Trim value in the text box for Osc_Trim b) Click “Write Osc_Trim”

5. Now the frequency has to be adjusted by repeating step 4 with different values. The frequency will be lower with a higher value of the capacitance array.

6. When the desired accuracy of the 32 MHz clock is obtained, store the corresponding trim value to the parameter Osc_Trim of the BD-data. This can be done by clicking the button “Write BD-Data” in HCI Lite tool. In the pop-up window, only change the parameter OSC_Trim to the calibrated value and give the module an individual BD_ADDR. (See in Figure 20)

7. Issue a HW reset of the device.

Figure 20 Infineon Write BD-Data Window

PAN1321


7.2.2.2 Crystal Trimming with SPP-AT Application

When the SPP-AT application is loaded into the EEPROM, the crystal trimming can be performed via AT commands using the eBMU SPP Toolbox provided by Infineon.

This is only necessary if the original calibration value, which is programmed during module production at Infineon, has been lost.

1. Connect a frequency counter to the test point P0.1 or P0.8. 2. Enable the production mode using the command AT+JPRO=1. 3. Issue the following command that makes the internal reference clock available at the test point (32 MHz

generated by the 26 MHz crystal oscillator): AT+JCAC = <osc_trim_value>,<GPIO>

Where: − <Osc_trim_value>: Range from 0x000 to 0x3FF − <GPIO>:

0x0002 to output 32 MHz on pin P0.1 0x0100 to output 32 MHz on pin P0.8

4. Measure the frequency of the signal on pin P0.1/P0.8 with the counter. 5. Trim the 32 MHz frequence to be within ±2ppm (±64 Hz) of accuracy changing the field <osc_trim_value>. 6. When the desidered accuracy is obtained, write the corresponding trim value to the parameter Osc_Trim in

the BD_Data using the command AT+JCBD=<bd_data>. 7. Issue a HW reset of the device.

The SPP Toolbox provides a friendly user interface which enables the user to execute the AT commands simply by clicking several buttons (see in Figure 21).

PAN1321


Figure 21 Crystal Trimming using eBMU SPP Toolbox

7.3 Connection to CMU/CBT through Antenna Link

This is the procedure to run a production test via the antenna. The test is carried out with a BT tester like CBT or CMU200.

1. Set the CMU in spectrum analyzer mode and set a center frequency of 2441 MHz. 2. Enable PAN13x1 to transmit CW unmodulated signal in channel 39 using the HCI Lite tool with the following

steps (see in Figure 22): a) Select “RF Test” tab. b) In “Test Continuous Wave Mode” field, select channel 39 and “No Modulation”. c) In “Output Power Step” field, select “Nominal”. d) In “Output Power Fine-Tuning Step” field, select “-2 dB”. e) Click “Start Test”.

PAN1321


HCI_Lite_RF_CW_No_Mod.vsd

b)

d)

c)

a)

e)

Figure 22 Start Transmission of CW Unmodulated Signal using HCI Lite

3. Change the attenuation on CMU, till the peak power is around 0.5 dBm. Using the IFA antenna of the CF card

and a whip antenna connected to the CMU, with 2cm spacing, an attenuation of 24 dB was found. 4. Note that the attenuation on CMU is a positive figure. 5. Reset the Unistone board. 6. Set CMU in Bluetooth signaling mode. 7. Set the attenuation found before. 8. Set RF max. level at 10 dBm to avoid overload in case of wrong settings and make sure that the CMU is

always able to be connected . New software releases of CBT have an automatic setting of RF Max Level. To change RF Max Level, from the initial screen press Connect Control >> Power >> Analyzer Level >> RF Max Level. From CBT software release v4.60 onwards the level is adapted automatically.

9. Establish the link between PAN13x1 board and CMU in the usual way, the power must be around 3.5 dBm.

PAN1321


7.4 Frequency Modulation and DEVM Failures

The PAN13x1 module is sensitive to the load impedance at 2nd

harmonic frequency (range 4.8-4.96 GHz). The presence of a disturbing 2

nd harmonic can be easily revealed by running the Unistone in TX continuous mode with

all 1s modulation. The effect of these sideband spurs is visible in modulation performances of the device, in terms of frequency drift, frequency deviation, FM noise, and DEVM failures or degraded performancies.

It is fundamental to run this test at the early stage of the development, in order to understand if the loading impedance is correct. The safest approach to have the correct 2

nd harmonic load impedance is to use the same

antenna and same microstrip to the antenna of the reference design.

The critical condition is when the RF output of the module is connected to the antenna. For this reason the test must be performed with an antenna link between the Unistone and a spectrum analyzer.

The test is to be started by doing the following settings using HCI Lite tool (see in Figure 23).

a) Select “RF Test” tab. b) In “Test Continuous Wave Mode” field, select the TX channel and the modulcation mode “GPSK”. c) In “Bit-Pattern” field, select “All One”. d) In “Output Power Step” field, select “Nominal”. e) In “Output Power Fine-Tuning Step” field, select “-2dB”. f) Click “Start Test”.

PAN1321


HCI_Lite_RF_CW_GFSK.vsd

b)

e)

d)

a)

f)c)

Figure 23 Start Frequency Modulation using HCI Lite

After starting the test with HCI Lite tool, visualize the output spectrum on a spectrum analyzer centered on the Tx center frequency (2441 MHz for channel 39, 2402 MHz (ch.0), 2480 MHz (ch.78)) with 1 MHz span. The spectrum looks like the one in Figure 24.

To guarantee the transmission, the quantity called ∆ in Figure 24 must be around -30 dBc or lower. If |∆| is smaller, we would suggest you to call your technical Infineon contact to receive more indications on how to get in spec.

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Figure 24 CW TX with All 1s Modulation Spectrum

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8 References

[1] Instructions_SPP_HCI_download.pdf

[2] eBMU_SPP_AT_V1.01_V1.1_UM_SD_Rev3.0.pdf (User’s Manual Software Description)

[3] eBMU_SPP_AT_V1.01_V1.2_RN_Rev1.1.pdf (Release Notes for SPP-AT application)

[4] PAN13x1_V1.01_UM_HD_Rev1.11.pdf (User’s Manual Hardware Description)

Date post:	16-Jun-2018
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