PANIMALAR ENGINEERING COLLEGE DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGG QUESTION BANK (2017-2018) II YEAR THIRD SEMESTER ECE INDEX PAGE S.NO SUBJECT CODE / NAME PAGE NO. 1. MA6351- TRANSFORMS & PARTIAL DIFFERENTIAL EQUATIONS 1.1-1.73 2. EC6301- OOPS AND DATA STRUCTURE 2.1-2.21 3. EC6302- DIGITAL ELECTRONICS 3.1-3.40 4. EC6303- SIGNALS AND SYSTEMS 4.1-4.41 5. EC6304- ELECTRONIC CIRCUITS-1 5.1-5.29 6. EE6352- ELECTRICAL ENGINEERING & INSTRUMENTATION 6.1-6.45
Transcript
PANIMALAR ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGG
QUESTION BANK (2017-2018)
II YEAR THIRD SEMESTER ECE
INDEX PAGE
S.NO SUBJECT CODE / NAME PAGE NO.
1. MA6351- TRANSFORMS & PARTIAL DIFFERENTIAL
EQUATIONS 1.1-1.73
2. EC6301- OOPS AND DATA STRUCTURE 2.1-2.21
3. EC6302- DIGITAL ELECTRONICS 3.1-3.40
4. EC6303- SIGNALS AND SYSTEMS 4.1-4.41
5. EC6304- ELECTRONIC CIRCUITS-1 5.1-5.29
6. EE6352- ELECTRICAL ENGINEERING &
INSTRUMENTATION 6.1-6.45
BLOOM’S TAXONOMY LEVELS
(BTL)
LEVEL 1 - REMEMBERING(R)
LEVEL 2 - UNDERSTANDING (U)
LEVEL 3 - APPLYING (A)
LEVEL 4 - ANALYZING (AZ)
LEVEL 5 - EVALUATING (E)
LEVEL 6 - CREATING(C)
1.1
PANIMALAR ENGINEERING COLLEGE
MA6351 TRANSFORMS AND PARTIAL DIFFERENTIAL
EQUATIONS
SOLVED TWO MARKS & PART - B QUESTIONS
(FOR THIRD SEMESTER)
1.2
UNIT-I
PARTIAL DIFFERENTIAL EQUATIONS
PART-A
1. Form a partial differential equation by eliminating the arbitrary constants from 22 ybxaz . [N/D13] [C]
Solution:
Given 22 ybxaz ----------------- (1)
Differentiating (1) partially with respect to x , we have
xax
z2
==> xap 2 ==>
x
pa
2 ------------------- (2)
Differentiating (1) partially with respect to y , we have
yby
z2
==> ybq 2 ==>
y
qb
2 ---------------------------- (3)
using (2) and (3) in (1), we have
22
22y
y
qx
x
pz
==> yqxpz
2
1
yqxpz 2 , which is the required partial differential equation.
2. Form a partial differential equation by eliminating the arbitrary constants from 33 ybxaz . [M/J14] [C]
Solution:
Given 33 ybxaz ----------------- (1)
Differentiating (1) partially with respect to x , we have
23 xax
z
==> 23 xap ==>
23 x
pa ------------------- (2)
Differentiating (1) partially with respect to y , we have
23 yby
z
==> 23 ybq ==>
23 y
qb ---------------------------- (3)
using (2) and (3) in (1), we have
3
2
3
2 33y
y
qx
x
pz
==> yqxpz
3
1
yqxpz 3 , which is the required partial differential equation.
3. Form the partial differential equation by eliminating the arbitrary constants a and b from
byaxza 1log . [A/M15] [C]
1.3
Solution: Given byaxza 1log …………..(1)
Differentiating (1) partially with respect to x , we have
11
1
x
za
za ==> 1
1
za
pa…………………(2)
Differentiating (1) partially with respect to y , we have
ay
za
za
1
1
aza
qa
1…………………(3)
Dividing (2) by (3), we have
a
za
qa
za
pa
1
1
1
p
qa
aq
p
1
Substituting the value of a in (2), we have
1
1
zp
q
pp
q
1
p
pzq
q pzqqp
pzq
qp
1
zqqpzqqpp 1
which is the required partial differential equation.
4. Form the partial differential equation by eliminating a and b from
byaxaz 22 .[N/D15] [C]
Solution: Given byaxaz 22
Differentiating (1) partially with respect to x , we have
2a
x
z
2ap ……….(2)
Differentiating (1) partially with respect to y , we have
yay
z2
y
qayaq
22 ………(3)
Using (3) in (2) , we have 22
2
22
442
qypy
qp
y
qp
which is the required
partial differential equation.
1.4
5. Form the PDE by eliminating the arbitrary constants ‘ a ’, ‘b ’ from the relation
2214 byaxza . [A/M15] [C]
Solution: Given 2214 byaxza ……………(1)
Differentiating (1) partially with respect to x , we have
byaxx
za
214 2
byaxpa 214 2 ……….(2)
Differentiating (1) partially with respect to y , we have
abyaxy
za
214 2 byaxaqa 214 2 ………(3)
Dividing (2) by (3), we have p
qa
aq
p
1 ……….. ..(4)
From (2), we have
2
14 2 pabyax
……….(5)
Using (5) in (1), we have 22
2
2
1414
paza
4
11614
2222 pa
za
221 paz
Using (4) in (6), we have 222
2
222
2
1 qpzpp
qpzp
p
qz
which is the required partial differential equation.
6. Form the partial differential equation from 2222rzbyax . [M/J13] [C]
Solution: Given 2222rzbyax ----------------(1)
Differentiating (1) partially with respect to x , we have
022
x
zzax ==> 022 pzax ==> 02 pzax
0 pzax ==> pzax ------------ (2)
Differentiating (1) partially with respect to y , we have
022
y
zzby ==> 022 qzby ==> 02 qzby
0 qzby ==> qzby ----------------- (3)
Using (2) and (3) in (1), we have
2222rzqzpz ==> 222222 rzqzpz
2222 1 rqpz , which is the required partial differential equation.
1.5
7. Form the partial differential equation by eliminating a and b from 2222 byaxz .
[A/M10]. [C]
Solution: Given 2222 byaxz --------------------- (1)
Differentiating (1) partially with respect to x , we have
222 byxx
z
==> 222 byxp ==>
x
pby
2
22 ------------ (2)
Differentiating (1) partially with respect to y , we have
yaxy
z222
==> 222 axyq ==>
y
qax
2
22 ---------------- (3)
using (2) and (3) in (1) , we have
x
p
y
qz
22
qpzyx 4 , which is the required partial differential equation.
8. Form the partial differential equations of all planes passing through the origin.[M/J16] [C]
Solution: Let the equation of the plane be
0 dzcybxa --------------------- (1) where a ,b , c and d are constants.
Since plane (1) passes through the origin, we have
0000 dcba ==> 0d
substituting 0d in (1), we have
0 zcybxa -------------------(2)
Differentiating (2) partially with respect to x , we have
0
x
zca ==> 0 pca ==> pca ----------------- (3)
Differentiating (2) partially with respect to y , we have
0
y
zcb ==> 0 qcb ==> qcb -------------- (4)
using (3) and (4) in (2), we have
0 zcyqcxpc ==> 0 zcyqcxpc
0 zyqxpc ==> 0 zqypx
zqypx , which is the required partial differential equation.
9. Construct the partial differential equation of all spheres whose centres lie on the z -axis, by
the elimination of arbitrary constants. [N/D11 , N/D15]. [A]
Solution: Let the centre of the sphere be c,0,0 a point on the z -axis and r be its
radius. Hence, its equation is
222200 rczyx
1.6
2222 rczyx ------------------- (1)
Differentiating (1) partially with respect to x , we have
022
x
zczx ==> 022 pczx ==> 02 pczx
0 pczx ==> xpcz ==> p
xcz -----------------(2)
Differentiating (1) partially with respect to y , we have
022
y
zczy ==> 022 qczy ==> 02 qczy
0 qczy ==> yqcz ==> q
ycz -----------------(3)
From (2) and (3), we have
q
y
p
x ==> pyqx
0 ypxq , which is the required partial differential equation.
10. Find the PDE of all spheres whose centers lie on the x-axis. [N/D16] [A]
Solution: Let the centre of the sphere be 0,0,a a point on the x axis and r be its
radius. Hence, its equation is
222200 rzyax
2222rzyax ------------------- (1)
Differentiating (1) partially with respect to x , we have
022
x
zzax ==> 022 pzax ==> 02 pzax
0 pzax ==> pzax -----------------(2)
Differentiating (1) partially with respect to y , we have
022
y
zzy ==> 022 qzy ==> 02 qzy
0 qzy ==> qzy -----------------(3)
Using (2) and (3) in (1), we have
2222rzqzpz ==> 222222 rzqzpz
2222 1 rqpz , which is the required partial differential equation.
11. By eliminating the arbitrary constants, form the partial differential equation from the relation byaxz 22 . [A/M11]. [C]
Solution: Given byaxz 22 --------------------- (1)
1.7
Differentiating (1) partially with respect to x , we have
byxx
z
22 ==> byxp 22 ==> x
pby
2
2 ----------------- (2)
Differentiating (1) partially with respect to y , we have
yaxy
z22
==> axyq 22 ==>
y
qax
2
2 ------------------ (3)
using (2) and (3) in (1) , we have
x
p
y
qz
22
qpzyx 4 , which is the required partial differential equation.
12. Form partial differential equation by eliminating the arbitrary function from yxfz . [C]
Solution: Given yxfz --------------- (1)
Differentiating (1) partially with respect to x , we have
yyxfx
z
==> yxfyp ------------------ (2)
Differentiating (1) partially with respect to y , we have
xyxfy
z
==> yxfxq --------------- (3)
Equations 3
2 implies
yxfx
yxfy
q
p
==>
x
y
q
p ==> qypx
0 qypx , which is the required partial differential equation.
13. .Form the partial differential equation by eliminating f from the relation
yxyxfz 22 . [C]
Solution: Given yxyxfz 22 -------------------(1)
Differentiating (1) partially with respect to x , we have
5. Find the complex form of the Fourier series of xe , lxl . Deduce that when is
constant other than an integer
n
l
xni
ne
nl
llx
1sincos
2222. [U]
UNIT-III
APPLICATIONS OF PARTIAL DIFFERENTIAL EQUATIONS
1. An uniform elastic string of length cms60 is subjected to a constant tension of Kg2 . If
the ends fixed and the initial displacement 600,600, 2 xxxxy , while the initial
velocity is zero, find the displacement function txy , . [U]
2. A tightly stretched string with fixed end points 0x and lx is initially displaced to the
form
l
x
l
x 2cos
3sin2 and then released. Find the displacement of the string at
any distance x from one end at any time t .[U]
3. The ends A and B of a rod lcm long have their temperatures kept at c30 and c80 ,
until steady state conditions prevail. The temperature of the end B is suddenly reduced to
c60 and that of A is increased to c40 . Find the temperature distribution in the rod
after time t.[A]
4. A square plate is bounded by the lines 1010,0,0 yandxyx . Its faces are
insulated. The temperature along the upper horizontal edge is given by
100,1010, xxxxu while the other edges are kept at C0 . Find the
temperature distribution in the plate.[A]
5. A rectangular plate with insulated surfaces is cm8 wide and so long compared to its
width that it may be considered as an infinite plate. If the temperature along short edge
0y is 80,8
sin1000, xx
xu
, while two long edges 0x and 8x as well as the
other short edge are kept at C0 . Find the steady state temperature at any point of the
plate.[A]
1.73
UNIT-IV
FOURIER TRANSFORMS
1. Find the Fourier cosine transform of
otherwise
xxxf
;0
10;1)(
2
. Hence prove that
16
3
2cos
cossin
0
3
dxx
x
xxx.[U]
2. Find the Fourier cosine transform of 2xe.[U]
3. Find the Fourier transform of the function defined by
1;0
1;1)(
2
x
xxxf . Hence prove
that
0
3 16
3
2cos
cossin ds
s
s
sss and
15
cossin2
0
3
dss
sss . [U]
4. Find the Fourier transform of x
xf1
[U]
5. Find the Fourier sine transform of
x
xxxf
;0
0;sin)( .[U]
UNIT-V
Z-TRANSFORMS AND DIFFERENCE EQUATIONS
1. Find
21
32
nn
nZ .[U]
2. Find the Z-transforms of
4sin 2 n
and
42cos
nn. [A]
3. Find the inverse Z-transform of 42
203
3
zz
zz. [U]
4. Using convolution theorem, find the inverse Z-transform of
3
4
z
z . [A]
5. Using Z-transform, solve 82454 12 nyyy nnn given that 30 y and
51 y .[A]
PANIMALAR ENGINEERING COLLEGE
DEPARTMENTOFELECTRONICS&COMMUNICATION
ENGINEERING
EC6301 OBJECTORIENTEDPROGRAMMING and
DATASTRUCTURES
SOLVED TWOMARKS&PART-B
QUESTIONS(FOR THIRD SEMESTER ECE)
2.2
EC6301 - OBJECT ORIENTED PROGRAMMING AND DATA STRUCTURES
UNIT-I DATA ABSTRACTION AND OVERLOADING
PART - A1. What is the output of the following program, if it is correct? Otherwise indicate the mistake: [May2006] (E)int l=10;void main [ ]int l=20; intl=30;cout<<l<<::l;The program is in correct due to syntax error. Within the main function, there is no need of anotheropening braces in the int l=20; and also closing braces.
2. Difference between Class and structure? [April -2010, Dec-2012] (R)Class is the ADT where as structure is user defined datatype.Class needs access specifier such as private, public & private where as structuremembers can be accessed by public by default & don t need any access specifiers.Class is oops where structure is borrowed from traditional structured [pop] concept.
3. What is abstract Class? [Nov-2009] (R)An abstract class is a class that is designed to be specifically used as a base class. An abstract classcontains at least one pure virtual function. You declare a pure virtual function by using a pure specifier [= 0] in the declaration of a virtual member function in the class declaration.
4. List out the advantages of new operator over malloc[] [Dec-2012] (R)It automatically computes the size of the data object.It automatically returns the correct pointer typeIt is possible to initialize the objects while creating the memory space. It can be overloaded.
5. What are the basic concepts of OOS? [ April -2011][Nov 2009] (R)Objects.Classes.Data abstraction and Encapsulation.Inheritance.Polymorphism.Dynamic binding.Message Passing
6. What is the difference between local variable and data member? [Nov-2011] (U)A data member belongs to an object of a class whereas local variable belongs to its currentscope.A local variable is declared within the body of a function and can be used only from the pointat which it is declared to the immediately following closing brace.A data member is declared in a class definition, but not in the body of any of the classmember functions.Data members are accessible to all member function of the class.
2.3
7. What is the function parameter? Difference between parameter and Argument. [Nov-2011](R)
A function parameter is a variable declared in the prototype or declaration of a function:void foo[int x]; // prototype -- x is a parametervoid foo[int x] // declaration -- x is a parameterAn argument is the value that is passed to the function in place of a parameter.
8. What is data hiding? [April -2011,Nov-2010] (R)The insulation of data from direct access by the program is called as data hiding orinformation binding.The data is not accessible to the outside world and only those functions, which are wrapped in theclass, can access it.
9. What are the advantages of Default Arguments? [Nov-2010] (U)The function assigns a default value to the parameter which does not have a matching argumentin the function call. They are useful in situations where some arguments always have the same value.e.g., float amt [float P, float n, float r = 0.15];
10. What are abstract classes? [Nov 2009, Apr 2013] (U)Classes containing at least one pure virtual function become abstract classes. Classes inheriting abstract classes must redefine the pure virtual functions; otherwise the derived classes also will become abstract. Abstract classes cannot be instantiated.
11. Define abstraction and Encapsulation [Apr 2011] (U)Data AbstractionAbstraction refers to the act of representing the essential features without including the background details or explanations.Data EncapsulationThe wrapping up of data and functions into a single unit is known as data encapsulation.
12. What is the Need for Static Members [April 2011] (U)Class members can be declared using the storage class specifier static in the class member list.Only one copy of the static member is shared by all objects of a class in a program. When youdeclare an object of a class having a static member, the static member is not part of the class object.
13. Define Polymorphism. [Apr 2013] (U)Polymorphism is another important oops concept. Polymorphism means the ability to take more than one form. For example, an operation may exhibit different behavior in different instances. Behavior depends upon the types of data used in the operation.
14. What do you mean by pure virtual functions? [Dec2008] (U)A pure virtual member function is a member function that the base class forces derived classes to provide. Any class containing any pure virtual function cannot be used to create object of its own type.
15. What is function Prototype? [DEC 2011] (U)A function prototype or function interface in C, Perl, PHP or C++ is a declaration of a function that omits the function body but does specify the function's return type, name and argument types. While a function definition specifies what a function does, a function prototype can be thought of as specifying its interface.
16. List out four Storage Classes in C++ [Nov 2008] (AZ)
2.4
Storage classes are used to specify the lifetime and scope of variables. How storage is allocated for variables and how variable is treated by complier depends on these storage classes.These are basically divided into 5 different types :1. Global variables2. Local variables3. Register variables4. Static variables5. Extern variables
17. What is an identifier? (R)Identifiers are names for various programming elements in c++ program. such as variables, arrays,function, structures, union, labels ect., An identifier can be Composed only of uppercase, lower caseletter, underscore and digits, but should start only with an alphabet or an underscore.
18. What is a keyword? (R)Keywords are word whose meanings have been already defined in the c compiler. They are alsocalled as reserved words.
(eg) main(), if, else, else, if, scanf, printf, switch, for, goto, while ect.,
19. List out the benefits of oops. (A) Can create new programs faster because we can reuse code Easier to create new data types Easier memory management Programs should be less bug-prone, as it uses a stricter syntax and type checking. `Data hiding', the usage of data by one program part while other program parts cannot access the data
20. List out the application of oops. (A) Client server computing Simulation such as flight simulations. Object-oriented database applications. Artificial intelligence and expert system Computer aided design and manufacturing systems.
21. Define data hiding. (AZ)The purpose of the exception handling mechanism is to provide a means to detect and report an
―exceptional circumstanceǁ so that appropriate action can be taken.22. What is the use of scope resolution operator? (U)In C, the global version of the variable cannot be accessed from within the inner block. C++ resolvesthis problem by introducing a new operator :: called the scope resolution operator. It is used to uncovera hidden variable.Syntax::: variable name
23. When will you make a function inline? (E)When the function definition is small, we can make that function an inline function and wecan mainly go for inline function to eliminate the cost of calls to small functions.
24. What is overloading? (U)Overloading refers to the use of the same thing for different purposes.There are 2 types of overloading: Function overloading Operator overloading
2.5
25. What is the difference between normal function and a recursive function? (U)∑A recursive function is a function, which call it whereas a normal function does not.∑Recursive function can t be directly invoked by main function
26. What are objects? How are they created? (U)Objects are basic run-time entities in an object-oriented programming system. The class variables are known as objects. Objects are created by using the syntax:classname obj1,obj2, ,objn; (or) during definition of the class:class classname-------obj1,obj2, ,objn;
27. List some of the special properties of constructor function. (E) They should be declared in the public section. They are invoked automatically when the objects are created. They do not have return types, not even void and cannot return values. Constructors cannot be virtual.Like other C++ functions, they can have default arguments
28. Describe the importance of destructor. (E)A destructor destroys the objects that have been created by a constructor upon exit from the programor block to release memory space for future use. It is a member function whose name is the same asthe class name but is preceded by a tilde. Syntax:~classname()
29. What do you mean by friend functions? (U)C++ allows some common functions to be made friendly with any number of classes, thereby allowing thefunction to have access to the private data of thse classes. Such a function need not be a member of any ofthese classes. Such common functions are called friend functions.
30. What are member functions? (U)Functions that are declared within the class definition are referred as member function.
31. Define dynamic binding.[ NOV/DEC 2015] (U)Dynamic binding means that the code associated with a given procedure call is not known until the time of the call at run-time.
32.Write any four properties of constructor.[DEC 2010) (U)Constructors should be declared in the public section.They are invoked automatically when the objects are created.They do not have return typesThey cannot be inherited.
33.List any four Operators that cannot be overloaded.(DEC 2010) (DEC 2009) (DEC 2011) ( E)Class member access operator (. , .*)Scope resolution operator (::)Size operator ( sizeof )Conditional operator (?:)
34.What is a Destructor? (DEC 2012)[ NOV/DEC 2015] (U)A destructor is used to destroy the objects that have been created by a constructor. It is a specialmember function whose name is same as the class and is preceded by a tilde ‗~ symbol. When anobject goes out from object creation, automatically destructor will be executed.
35.What is the Need for initialization of object using Constructor? (DEC 2012) (U)If we fails to create a constructor for a class, then the compiler will create a constructor by default in the name of class name without having any arguments at the time of compilation and provides the initial values to its data members. So we have to initialize the objects using constructor.
36. Give an example for a Copy Constructor (JUNE 2013) (C)#include<iostream>#include<conio.h>using namespace std;class Example //Variable Declarationint a,b;public://Constructor with ArgumentExample(int x,int y) // Assign Values In Constructor a=x;b=y;cout<<"\nIm Constructor";void Display() cout<<"\nValues :"<<a<<"\t"<<b;;int main() Example Object(10,20); //Copy ConstructorExample Object2=Object;// Constructor invoked. Object.Display(); Object2.Display();// Wait For Output Screen getch();return 0;
37. What is the Need for Destructors? (June 2013) (C) Destructor is used to destroy an object.By destroying the object memory occupied by the object is released.
38. Explain the functions of Default Constructor(MAY 2011) (E)The main function of the constructor is, if the programmer fails to create a constructor for a class, then the compiler will create a constructor by default in the name of class name without having any arguments at the time of compilation and provides the initial values to its data members. Since it is created by the compiler by default, the no argument constructor is called as default constructor.
39.What is the need for Overloading an operator(MAY 2011) (E)To define a new relation task to an operator, we must specify what it means in relation to theclass to which the operator is applied.This is done with the help of a special function called operator function.It allows the developer to program using notation closer to the target domain and allow usertypes to look like types built into the language.
2.7
The ability to tell the compiler how to perform a certain operation when its correspondingoperator is used on one or more variables.
40.What is the function of get and put function (MAY 2010) (U)Cin.get(ch) reads a character from cin and stores what is read in ch.Cout.put(ch) reads a character and writes to cout.
41. What is reference variable?(April/May 2015) (R)c++ references allow you to create a second name for the a variable that you can use to read or modify the original data stored in that variable.
42.What is friend function? ?(April/May 2015) (R)A friend function of a class is defined outside that class' scope but it has the right to access all privateand protected members of the class. Even though the prototypes for friend functions appear in the class definition, friends are not member functions.
PART - B
1) Classify the needs for object oriented paradigm? (U)2) Explain in detail of object oriented concepts. (U)3) Explain the characteristics of OOPS in detail. (U)4) List the features of object oriented programming. (A)5) Explain the structure of C++ program. (U)6) Explain various control statements used in C++. (U)7) Explain Do-While with an example. (U)8) Compare inline functions of C++ with ordinary functions and with macros. (U)9) Elaborate dynamic binding? How is it achieved? (C)10) Criticize short notes on call and Return Reference. (E)11) Distinguish New and Delete Operators. With and example. (AZ)12) Develop a C++ program to implement dynamic memory allocation. (A)13) Originate the concept of ADT with some illustrative example. (C)14)Explain in detail about data hiding. (U)15) Explain in detail about class, objects, methods and messages. (U)16) Explain friend function with an example. (U)17) Illustrate the concept of function overloading to find the maximum of two numbers.
(U)18) Justify about operator overloading with an example. (E)19)Evaluate the list of rules for overloading operators with one example. (E)
PART- C
1) Develop a C++ program that will ask for a temperature in Fahrenheit and display.(C)2) Design calculator using function overloading. (C)3) Develop a C++ program to implement C=A+B, C=A-B and C-A*B where A, B and C are objects containing a int value (vector). (C)
2.8
4)Develop a program to concatenate two strings using + operator overloading. (C)5) Develop a program using operator overloading to add two time values in the format HH:MM:SS to the resulting time along with rounding off when 24 hrs is reached. A time class is created and operator + is overloaded to add the two time class objects. (C)6) Develop a program to perform multiplication using an integer and object. Use friend function. (C)
2.9
Unit II INHERITANCE AND POLYMORPHISM
PART - A
1. What are templates? (AUC DEC 2009) (U)Template is one of the features added to C++.It is new concepts which enable us to define generic classes and functions and thus provides support for generic programming. A template can be used to create a family of classes or functions.
2. Illustrate the exception handling mechanism. (AUC DEC 2009) (E)C++ exception handling mechanism is basically upon three keywords, namely, try, throw,and catch.try is used to preface a block of statements which may generate exceptions.throw - When an exception is detected, it is thrown using a throw statement in the try block.Catch- A catch block defined by the keyword catch ‗catches the exception ‗thrown by thethrown statement in the try block and handles its appropriately.
3. What happens when a raised exception is not caught by catch block? (AUC MAY 2010)(AZ)If the type of object thrown matches the arg type in the catch statement, then catch block is executed for handling the exception.If they do not match the program is aborted with the help of abort() function which is invoked by default.When no exception is detected and thrown, the control goes to the statement immediately after the catch block. That is the catch block is skipped.
4. What is a template? What are their advantages(AUC DEC 2010/JUN 2012/DEC 2012) (U)A template can be used to create a family of classes or functions.A template is defined with a parameter that would be replaced by a specified data type atthe time of actual use of the class or functions.Supporting different data types in a single framework.The template are sometimes called parameterized classes or functions.
5. How is an exception handled in C++? (AUC DEC 2010) (A)Exceptions are run time anomalies or unusual conditions that a program may encounterwhile executing.1. Find the problem (Hit the exception)2. Inform that an error has occurred.( Throw the exception)3. Receive the error information. ( Catch the exception)4. Take corrective actions.( Handle the exception)
6. What is function template? Explain. (AUC MAY 2011) (A)Like class template, we can also define function templates that could be used to create afamily of functions with different argument types.The general format of a function template is:template<class T>returntypefunctionname ( arguments of type T)// // .Body of function with type T wherever appropriate// ..
7. List five common examples of exceptions. (AUC MAY 2011) (AZ)Division by zeroAccess to an array outside of its bounds
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Running out of memory or disk space.
8. What is class template? (AUC DEC 2011) (A)Templates allows to define generic classes. It is a simple process to create a generic classusing a template with an anonymous type.The general format of class template is:template<class T>classclassname// class member specification.// . with anonymous type T wherever appropriate// , ..
9. What are 3 basic keywords of exception handling mechanism? (AUC DEC 2011) (R)C++ exception handling mechanism is basically built upon three keywordstrythrowcatch
10. What are the c++ operators that cannot be overloaded? (U)Size operator (sizeof)Scope resolution operator (::)member access operators(. , .*)Conditional operator (?:)
11. What is a virtual base class? (U)When a class is declared as virtual c++ takes care to see that only copy of that class is inherited,regardless of how many inheritance paths exist between the virtual base class and a derived class.
12. What is the difference between base class and derived class? (U)The biggest difference between the base class and the derived class is that the derived class contains the data members of both the base and its own data members. The other difference is based on the visibility modes of the data members.
13.What are the rules governing the declaration of a class of multiple inheritance? (U) More than one class name should be specified after the : symbol. Visibility modes must be taken care of.If several inheritance paths are employed for a single derived class the base class must beappropriately declared.
14. Mention the types of inheritance. (R)1.Single inheritance.2. Multiple inheritance.3. Hierarchical inheritance.4. Multilevel inheritance.5. Hybrid inheritance.
15. Define dynamic binding. (APRIL MAY 2010) (U)Dynamic binding means that the code associated with a given procedure call is not knownuntil the time of the call at run-time.
16. What do you mean by pure virtual functions? (U)A pure virtual function is a function declared in a base class that has no definition relative to the base class. In such cases, the compiler requires each derived class to either define the function or redeclare
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it as a pure virtual function. A class containing pure virtual functions cannot be used to declare any objects of its own.
17. Mention the key words used in exception handling. (U)The keywords used in exception handling are throw try catch
18. List the ios format function. (U)The ios format functions are as follows: width() precision() fill() setf() unsetf()
19. List the manipulators. (U)The manipulators are: setw() setprecision() setfill() setiosflags() resetiosflags()
20. Define fill functions. (R)The fill( ) function can be used to fill the unused positions of the field by any desiredcharacter rather than by white spaces (by default). It is used in the following form: cout.fill(ch);where ch represents the character which is used for filling the unused positions.
21 .Give the syntax of exception handling mechanism. (E)The syntax of exception handling mechanism is as follows:try---------------------throw exception---------------------catch(type arguments)--------------------------------------------------------------------------------------
22. What is overloading(April/May 2015) (U)Overloading is the concept of Compile time Polymorphism. It does not need inheritance. Method canhave different data types. Two function having same name and return type, but with different typeand/or number of arguments is called as overloading.
23. Why there is need for operator overloading? (April/May 2015) (U)Most fundamental data types have pre-defined operators associated with them. For example, theC++ data type int, together with the operators +, -, *, and /, provides an implementation of the
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mathematical concepts of an integer. To make a user-defined data type as natural as a fundamental data type, the user-defined data type must be associated with the appropriate set of operators. It deals with overloading of operators to make Abstract Data Types(ADTS) more natural, and closer tofundamental data types.
24. Differentiate Private and protected members of a class . [NOV/DEC 2015] (U)Public variables, are variables that are visible to all classes.Private variables, are variables that are visible only to the class to which they belong.Protected variables, are variables that are visible only to the class to which they belong, and anysubclasses.
PART - B1) Discuss the characteristics of constructors and destructors. (C)2) What are constructors? Explain the concept of destructor with an example. (U)3) Explain the constructors and destructors in detail with an example program. (U)4) Explain data encapsulation and inheritance in detail. (U)5) Explain with examples, the types of inheritance in C++. (E)6)Examine how can you pass parameters to the constructors of base classes in multiple inheritances? (AZ)7) What is inheritance? List out the advantages of inheritance. (AZ)8) Explain the order in which the constructors are called when an object of derived class is created. (U)9) Explain about implementation of run time polymorphism in C++ with an example.
(U)10) What is an abstract class? What is dynamic binding? How is it achieved? (U)11) What is the difference between a virtual function and a pure virtual function? Give example of each. (U)12) What is multiple inheritances? Discuss the syntax and rules of multiple inheritances in C++. (U) 13) Explain about dynamic method dispatch with an example (U)
PART C1)Develop a program to illustrate multiple constructors and default argument for a single class. (C)2)Develop a C++ program to define overload constructor to perform string initialization, string copy and string destruction. (C)3)Write a C++ program to illustrate the concept of hierarchical inheritance. (C)4)Write a C++ program to implement multilevel inheritance (C)5)Write a C++ program to implement multiple inheritance (C)6)Write a C++ program to generate user defined exception user inputs odd numbers.(C)7)State the rules for virtual functions. Write a C++ program to declare a virtual function &demonstrate (C)
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UNIT IIILINEAR DATA STRUCTURES
PART A1. Write down the definition o f data structures? NOV DEC 2012A data structure is a mathematical or logical way of organizing data in the memory that consider not only the items stored but also the relationship to each other and also it is characterized by accessing functions.2. Binary Heap NOV DEC 2012, APRIL MAY 2009The implementation we will use is known as a binary heap. Its use is so common for priorityqueue implementations that when the word heap is used without a qualifierStructure PropertyA heap is a binary tree that is completely filled, with the possible exception of the bottom level, which is filled from left to right. Such a tree is known as a complete binary tree3. Define Algorithm?Algorithm is a solution to a problem independent of programming language. It consist of set of finite steps which, when carried out for a given set of inputs, produce the corresponding output and terminate in a finite time.4. What are the features of an efficient algorithm? Free of ambiguity Efficient in execution time Concise and compact Completeness Definiteness Finiteness5. List down any four applications of data structures?Compiler designOperating SystemDatabase Management systemNetwork analysis6. What is meant by an abstract data type (ADT)?An ADT is a set of operation. A useful tool for specifying the logical properties of a datatype is the abstractdata type.ADT refers to the basic mathematical concept that defines the datatype. Eg.Objects such as list, set and graph along their operations can be viewed as ADT's.7. What are the operations of ADT?Union, Intersection, size, complement and find are the various operations of ADT.8. What is meant by list ADT?List ADT is a sequential storage structure. General list of the form a1, a2, a3. ., an and the size of the list is 'n'. Any element in the list at the position I is defined to be ai, ai+1 the successor of ai and ai-1 is the predecessor of ai.9. What are the two parts of ADT? Value definition Operator definition10. What is a Sequence?A sequence is simply an ordered set of elements.A sequence S is sometimes written as the enumeration of its elements,such asS =If S contains n elements,then length of S is n.11. Define len(S),first(S),last(S),nilseq ?len(S) is the length of the sequence S.first(S) returns the value of the first element of S last(S)returns the value of the last element of Snilseq :Sequence of length 0 is nilseq .ie., contains no element.
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12. What are the two basic operations that access an array?Extraction:Extraction operation is a function that accepts an array, a ,an index,i,and returns an element of the array.Storing:Storing operation accepts an array , a ,an index i , and an element x.13. Define Structure?A Structure is a group of items in which each item is identified by its own identifier ,each of whichis known as a member of the structure.14. Define Union ?Union is collection of Structures ,which permits a variable to be interpreted in several different ways.15. Define Automatic and External variables?Automatic variables are variables that are allocated storage when the function is invoked. Externalvariables are variables that are declared outside any function and are allocated storage at the point atwhich they are first encountered for the remeinder of the program s execution.16. What is a Stack? NOV DEC 2008A Stack is an ordered collection of items into which new items may be inserted and from which itemsmay be deleted at one end, called the top of the stack. The other name of stack is Last-in -First-out list.17. What are the two operations of Stack? _ PUSH _ POP18. What is a Queue? APR/MAY 2015A Queue is an ordered collection of items from which items may be deleted at front end and inserted at rear end19. What is a Priority Queue? NOV DEC 2010Priority queue is a data structure in which the intrinsic ordering of the elements does determine the results of its basic operations. Ascending and Descending priority queue are the two types of Priority queue.20. What is a linked list?Linked list is a kind of series of data structures, which are not necessarily adjacent in memory. Eachstructure contain the element and a pointer to a record containing its successor.21. What is a doubly linked list?In a simple linked list, there will be one pointer named as 'NEXT POINTER' to point the next element,where as in a doubly linked list, there will be two pointers one to point the next element and the otherto point the previous element location.22. Define double circularly linked list?In a doubly linked list, if the last node or pointer of the list, point to the first element of the list,then it is a circularly linked list.23. What is a circular queue?The queue, which wraps around upon reaching the end of the array is called as circular queue.24. Define max and min heap?A heap in which the parent has a larger key than the child's is called a max heap. A heap in which the parent has a smaller key than the child is called a min heap25.What is ADT? (April/May 2015)A data type can be considered abstract when it is defined in terms of operations on it, and its implementation is hidden. is a mathematical model for data types where a data type is defined by itsbehavior (semantics) from the point of view of a user of the data, specifically in terms of possible values,possible operations on data of this type, and the behavior of these operations.
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PART B1. Explain the insertion and deletion operation in singly linked list. [Comprehension]
2. Explain array based implementation of list with an example program. [Comprehension]
3. Given singly linked list whose first node is pointed to by the pointer variable C formulate an algorithm to delete the first occurrence of X from the list and Insert the element X after the position P in the list. .[ Comprehension]
4. Write the ADT operation for insertion and deletion routine in stack. [Synthesis]
5. Explain the process of postfix, prefix, infix expression evaluation with an example. [Comprehension]
6. Give a procedure to convert an infix expression a+b*c+(d*e+f)*g to postfix notation.[ Comprehension]
7. Write a routine to insert an element in a linked list. [Synthesis]
8. Explain the process of conversion from infix expression to postfix using stack. [Comprehension]
9. Write the ADT operation for insertion and deletion routine in linked lists & Queue. [Synthesis]
PART C
1. Explain about Linked list, its Types, insertion and deletion routines with suitable example. [Comprehension]
2. Explain the process of postfix, prefix, infix expression evaluation with an example. [Comprehension]
3. What is a queue? Write an algorithm to implement queue.[ Knowledge]
4. Explain the implementation stack using linked list. [Comprehension]
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UNIT IVNON- LINEAR DATA STRUCTURES
PART A
1. Define non-linear data structure?Data structure which is capable of expressing more complex relationship than that of physical adjacency is called non-linear data structure.2. Define tree?A tree is a data structure, which represents hierarchical relationship between individual Data items.3. Define child and parent of a tree.The root of each subtree is said to be a child of ‗r and ‗r is the parent of each subtree root.4. Define leaf?In a directed tree any node which has out degree o is called a terminal node or a leaf.5. What is a Binary tree? NOV/DEC 2015A Binary tree is a finite set of elements that is either empty or is partitioned into three disjoint subsets. The first subset contains a single element called the root of the tree. The other two subsets are themselves binary trees called the left and right sub trees.6. What are the applications of binary tree?Binary tree is used in data processing.a. File index schemesb. Hierarchical database management system7. What is meant by traversing?Traversing a tree means processing it in such a way, that each node is visited only once.8. What are the different types of traversing?The different types of traversing area.Pre-order traversal-yields prefix form of expression.b. In-order traversal-yields infix form of expression.c. Post-order traversal-yields postfix form of expression.9. What are the two methods of binary tree implementation?Two methods to implement a binary tree are,a. Linear representation.b. Linked representation10. Define Graph?A graph G consist of a nonempty set V which is a set of nodes of the graph, a set E which is the set of edges of the graph, and a mapping from the set for edge E to a set of pairs of elements of V.It can also be represented as G=(V, E).11. Define adjacent nodes?Any two nodes which are connected by an edge in a graph are called adjacent nodes. For Example, if and edge xÎE is associated with a pair of nodes (u,v) where u, v Î V, then we say that the edge x connects the nodes u and v.12.Name the different ways of representing a graph?a. Adjacency matrixb. Adjacency list13. What are the two traversal strategies used in traversing a graph?a. Breadth first searchb. Depth first search14. What is an acyclic graph?A simple diagram which does not have any cycles is called an acyclic graph.
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15. Give some example of NP complete problems.Hamiltonian circuit. Travelling salesmen problems16. WhatAVL treares?the algorithms used to find the minimum spanning tree?An AVL Prim treeis algorithmbinarysearch tree with a balancing condition.For every node in the tree the height of the left and right subtrees can differ at most by 1.The height of Kruskal s algorithmof empty tree is defined to be -1.It ensures that the depth of the tree is O(log N)17.What is topological sort?A topological sort is an ordering of vertices in a directed acyclic graph,such that if there is a path from vi then vj appears after vi in the ordering.18.What is single source shortest path problem?Given as an input a weighted graph, G=(V,E) and a distinguished vertex, s find the shortest weighted path from ‗s to every other vertex in G.19.Mention some shortest path problemsUnweighted shortest pathsDijikstra s algorithmAll-pairs shortest paths20. Define complete binary tree.It is a complete binary tree only if all levels, except possibly the last level have the maximum number of nodes maximum.A complete binary tree of height ‗h has between 2h and 2h+1 1 node21.Define binary search tree. Why it is preferred rather than the sorted linear array andlinked list?Binary search tree is a binary tree in which key values of the left sub trees are lesser than the root value and the key values of the right sub tree are always greater than the root value. In linear array or linked list the values are arranged in the form of increasing or decreasing order. If we want to access any element means, we have to traverse the entire list. But if we use BST, the element to be accessed is greater or smaller than the root element means we can traverse either the right or left sub tree and can access the element irrespective of searching the entire tree.22. various implementations of trees.Linear implementationLinked list implementation23. List out the application of trees.Ordered tree―Cǁ representation of tree24 Show the maximum number of nodes in a binary tree of height H is 2H+1 1.Consider H = 3No. of nodes in a full binary tree = 2H+1 1= 23+1 1= 24 1= 15 nodesWe know that a full binary tree with height h=3 has maximum 15 nodes.Hence proved25. A + (B-C)*D+(E*F), if the above arithmetic expression is represented using a binary tree,Find the number of non-leaf nodes in the tree.Expression tree is a binary tree in which non leaf nodes are operators and the leaf nodesare operands. In the above example, we have 5 operators. Therefore the number of non-leaf nodes in the tree is 5.26. Write an algorithm to declare nodes of a tree structure. (AUC APR / MAY2010)Struct tree nodeint element;Struct tree *left;Struct tree *right;27 .How Graph is represented? (April/May 2015)Graph Data Structure. Vertex − Each node of the graph is represented as a vertex. A graph is a
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pictorial representation of a set of objects where some pairs of objects are connected by links. The interconnected objects are represented by points termed as vertices, and the links that connect the vertices are called edges.Formally, a graph is a pair of sets (V, E), where V is the set of vertices and E is the set of edges, connecting the pairs of vertices. Take a look at the following graph
In the above graph,V = a, b, c, d, e E = ab, ac, bd, cd, de28.What is a Tree? (April/May 2015)Tree represents nodes connected by edges. In computer science, a tree is a widely used abstractdata type (ADT) or data structure implementing this ADT that simulates a hierarchical tree structure, with a root value and subtrees of children with a parent node, represented as a set of linked nodes.
29. When a graph is said to be connected? NOV/DEC 2015A graph is connected when there is a path between every pair of vertices. In a connected graph, thereare no unreachable vertices. A graph that is not connected is disconnected. A graph with just one vertex is connected. An edgeless graph with two or more vertices is disconnected.30. How array elements are sorted using merge sort? NOV/DEC 2015A merge sort works as follows:1. Divide the unsorted list into n sublists, each containing 1 element (a list of 1 element isconsidered sorted).2. Repeatedly merge sublists to produce new sorted sublists until there is only 1 sublist remaining.This will be the sorted list
PART B1. Describe the insertion deletion with example. [Comprehension]
2. Draw the binary search tree for the following input list 60, 25,75,15,50,66,33,44. Trace an algorithm to delete the nodes 25, 75, 44 from the tree. [Analysis]
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3. Explain the operations of insertion of nodes into and deletion of nodes from, a binary search tree with code. [Comprehension]
4. Explain the two applications of trees with a neat example. [Comprehension]
5. How do you insert an element in a binary search tree? [ Knowledge]
6. What are the graph traversal methods? Explain it with example. [ Knowledge]
7. Give an algorithm to find minimum Spanning tree, explain it with suitable example.[ Comprehension]
8. Explain connected component. [Comprehension]
PART C1. Explain the operations of insertion of nodes into and deletion of nodes from, a binary search
tree with code. [Comprehension]
2. Write an algorithm for finding minimum spanning tree and explain application, illustrate the algorithm with typical data of yours own example. [Synthesis]
3. Give the analysis of insertion and deletion operations of nodes in binary search tree.[ Comprehension]
4. Explain the algorithm for depth first search and breadth first search with the following graph . [Comprehension]
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UNIT VSORTING AND SEARCHING
PART A1. What is maxheap? Apr/May,2010If we want the elements in the more typical increasing sorted order, we can change the ordering property so that the parent has a larger key than the child. it is called max heap.2. What is divide and conquer strategy?In divide and conquer strategy the given problem is divided into smaller problems and solved recursively. The conquering phase consists of patching together the answers. Divide and conquer is a very powerful use of recursion that we will see many times.3. Differentiate between merge sort and quick sort? Apr/May,2011Mergesort1. Divide and conquer strategy2. Partition by positionQuicksort1. Divide and conquer strategy2. Partition by value4. Mention some methods for choosing the pivot element in quicksort?1. Choosing first element2. Generate random number3. Median of three5. What are the three cases that arise during the left to right scan in quicksort?I and j cross each otherI and j do not cross each otherI and j points the same position6. What is the need of external sorting?External sorting is required where the input is too large to fit into memory. So external sorting isnecessary where the program is too large. It is a basic external sorting in which there are two inputs and two outputs tapes.7. What is replacement selection?We read as many records as possible and sort them. Writing the result to some tapes. This seems like the best approach possible until one realizes that as soon as the first record is written to a output tape the memory it used becomes available for another record. If the next record on the input tape is larger than the record we have just output then it can be included in the item. Using this we can give algorithm.This is called replacement selection.8. What is sorting? APR/MAY 2015Sorting is the process of arranging the given items in a logical order. Sorting is an example where the analysis can be precisely performed.9. What is mergesort?The mergesort algorithm is a classic divide and conquer strategy. The problem is divided into two arrays and merged into single array10. What are the p roperties involved in heapsort? Apr/May,20101. Structure property2. Heap order property11. D efine articulation points.If a graph is not biconnected, the vertices whose removal would disconnect the graph are known as articulation points12. What is time complexity? APR/MAY 2015
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The time complexity of an algorithm quantifies the amount of time taken by an algorithm to run as a function of the length of the string representing the input .
PART B1. Write the sequence of sorting on 3, 1, 4,7,5,9,2,6,5 using Insertion sort. [Synthesis]
2. Explain the operation and implementation of external sorting. [Comprehension]
3. Write down the merge sort algorithm and give its worst case, best case and average case analysis. [Synthesis]
4. Explain the Quick sort algorithm with example. [Comprehension]
5. Discuss in detail about quick sort algorithm. [Synthesis]
6. Explain linear search algorithm with an example. [Comprehension]
7. Discuss the differentiation of linear search algorithm with binary search algorithm. [Synthesis]
PART C
1. Write quick sort algorithm and explain. [Synthesis]
2. Explain linear search & binary search algorithm in detail. [Comprehension]
3. Explain the operation and implementation of merge sort. [Comprehension]
4. Write the quick sort algorithm for the following list of numbers. 90,77,60,99,55,88,66. [Synthesis]
PANIMALAR ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
EC6302 DIGITAL ELECTRONICS
SOLVED TWO MARKS AND PART B &C QUESTIONS
3.1
UNIT I - MINIMIZATION TECHNIQUES AND LOGIC GATES PART- A
1) What are the basic properties of Boolean algebra? (R)The basic properties of Boolean algebra are commutative property, associativeProperty and distributive property.
2) State the associative property of Boolean algebra. (R)The associative property of Boolean algebra states that the OR ing of several
variables results in the same regardless of the grouping of the variables. The associativeproperty is stated as follows: A+(B+C)=(A+B)+C.
3) State the commutative property of Boolean algebra. (R)The commutative property states that the order in which the variables are ORed
makes no difference. The commutative property is: A+B=B+A
4) State the distributive property of Boolean algebra. (R)The distributive property states that AND ing several variables and OR ing the result
with a single variable is equivalent to OR ing the single variable with each of the severalvariables and then AND ing the sums. The distributive property is:
A+BC= (A+B) (A+C)
5) State the absorption law of Boolean algebra. (R)The absorption law of Boolean algebra is given by X+XY=X, X(X+Y) =X.
6) Simplify the following using De Morgan's theorem [((AB)'C)'' D]' (AZ)[((AB)'C)'' D]' = ((AB)'C)'' + D' [(AB)' = A' + B']
= (AB)' C + D'
= (A' + B‟) C + D'
7) State De Morgan's theorem. (R)De Morgan suggested two theorems that form important part of Boolean algebra.
They are1) the complement of a product is equal to the sum of the complements.
(AB)' = A' + B'
2) The complement of a sum term is equal to the product of the complements.
11) Simplify AB + (AC)' + AB C (AB + C) (AZ)AB + (AC)' + AB‟C (AB + C) = AB + (AC)' + AAB'BC + AB'CC
= AB + (AC)' + AB'CC [A.A' = 0]
= AB + (AC)' + AB'C [A.A = 1]
= AB + A' + C' =AB'C [(AB)' = A' + B']
= A' + B + C' + AB'C [A + AB' = A + B]
= A' + B'C + B + C' [A + A'B = A + B]
= A' + B + C' + B'C
=A' + B + C' + B'
=A' + C' + 1
= 1 [A + 1 =1]
12) Simplify the following expression Y = (A + B) (A + C' )(B' + C' ) (AZ)
Y = (A + B)(A + C' )(B' + C' )
= (AA' + AC +A'B +BC) (B' + C') [A.A' = 0]
= (AC + A'B + BC) (B' + C‟)
= AB'C + ACC' + A'BB' + A'BC' + BB'C + BCC'
= AB'C + A'BC'
13) Show that (X + Y' + XY)( X + Y')(X'Y) = 0 (U)(X + Y' + XY) (X + Y')(X'Y) = (X + Y' + X)(X + Y' )(X' + Y) [A + A'B = A + B]
= (X + Y‟) (X + Y‟) (X'Y) [A + A = 1]
= (X + Y‟) (X'Y) [A.A = 1]
= X.X' + Y'.X'.Y
= 0 [A.A' = 0]
14) Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC (E)ABC + ABC' + AB'C + A'BC=AB(C + C') + AB'C + A'BC
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=AB + AB'C + A'BC
=A(B + B'C) + A'BC
=A(B + C) + A'BC
=AB + AC + A'BC
=B(A + C) + AC
=AB + BC + AC
=AB + AC +BC ...Proved
15) Convert the given expression in canonical SOP form Y = AC + AB + BC (C)Y = AC + AB + BC
=AC (B + B‟) + AB (C + C‟) + (A + A') BC
=ABC + ABC' + AB'C + AB'C' + ABC + ABC' + ABC
=ABC + ABC' +AB'C + AB'C' [A + A =1]
16) Define duality property. (R)Duality property states that every algebraic expression deducible from the postulates
of Boolean algebra remains valid if the operators and identity elements are interchanged. If the dual of an algebraic expression is desired, we simply interchange OR and AND operators and replace 1's by 0's and 0's by 1's.
17) Find the complement of the functions F1 = x'yz' + x'y'z and F2 = x (y'z' + yz). (R)
18) Simplify the following expression. (AZ)Y = (A + B) (A = C) (B + C)
= (A A + A C + A B + B C) (B + C)
= (A C + A B + B C) (B + C)
= A B C + A C C + A B B + A B C + B B C + B C C
= A B C
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19) What are the methods adopted to reduce Boolean function? (R)i) Karnaugh map
ii) Tabular method or Quine Mc-Cluskey method
iii) Variable entered map technique.
20) State the limitations of karnaugh map. (R)i) Generally it is limited to six variable map (i.e.) more then six variable
involving expression are not reduced.
ii) The map method is restricted in its capability since they are useful for
Simplifying only Boolean expression represented in standard form.
21) What is a karnaugh map? (R)A karnaugh map or k map is a pictorial form of truth table, in which the map
diagram is made up of squares, with each squares representing one minterm of the function.
22) Find the minterms of the logical expression Y = A'B'C' + A'B'C + A'BC + ABC' (R)
Y = A'B'C' + A'B'C + A'BC + ABC'
=m0 + m1 +m3 +m6
=Σm (0, 1, 3, 6)
23) Write the maxterms corresponding to the logical expression. (R)Y = (A + B + C' )(A + B' + C')(A' + B' + C)
= (A + B + C' )(A + B' + C')(A' + B' + C)
=M1.M3.M6
=∏M (1, 3, 6)
24) What are called don t care conditions? (R)In some logic circuits certain input conditions never occur, therefore the
Corresponding output never appears. In such cases the output level is not defined, it can be either high or low. These output levels are indicated by X‟ or d‟ in the truth tables and are called don‟t care conditions or incompletely specified functions.
25) What is a prime implicant? (R)A prime implicant is a product term obtained by combining the maximum possible
number of adjacent squares in the map.
26) What is an essential implicant? (R)If a min term is covered by only one prime implicant, the prime implicant is said to
be essential.
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27) What is a Logic gate? (R)Logic gates are the basic elements that make up a digital system. The electronic gate
is a circuit that is able to operate on a number of binary inputs in order to perform a particular logical function.
28) Give the classification of logic families. (R)Bipolar
i) Saturated 1. TTL 2. ECL 3. I I C 4. RTL
ii) Non Saturated 1. Schottky TTL 2. DTL
Unipolar
1. PMOS 2. NMOS 3. CMOS
29) What are the basic digital logic gates? (R)The three basic logic gates are
AND gate
OR gate
NOT gate.
30) Which gates are called as the universal gates? What are its advantages? (R)The NAND and NOR gates are called as the universal gates. These gates are used to
perform any type of logic application.
31) Classify the logic family by operation? (R)The Bipolar logic family is classified into
Saturated logic
Unsaturated logic.
The RTL, DTL, TTL, I2L, HTL logic comes under the saturated logic family.
The Schottky TTL, and ECL logic comes under the unsaturated logic family.
3.6
32) Mention the important characteristics of digital IC s? (R)Fan out
Power dissipation
Propagation Delay
Noise Margin
Fan In
Operating temperature
Power supply requirements.
33) Define Fan-out? (R)Fan out specifies the number of standard loads that the output of the gate can drive
without impairment of its normal operation.
34) Define power dissipation? (R)Power dissipation is measure of power consumed by the gate when fully driven by
all its inputs.
35) What is propagation delay? (R)Propagation delay is the average transition delay time for the signal to propagate
from input to output when the signals change in value. It is expressed in ns.
36) Define noise margin? (R)It is the maximum noise voltage added to an input signal of a digital circuit that does
not cause an undesirable change in the circuit output. It is expressed in volts.
37) Define fan in? (R)Fan in is the number of inputs connected to the gate without any degradation in the
voltage level.
38) What is High Threshold Logic? (R)Some digital circuits operate in environments, which produce very high noise
signals. For operation in such surroundings there is available a type of DTL gate which possesses a high threshold to noise immunity. This type of gate is called HTL logic or High Threshold Logic.
39) What are the types of TTL logic? (R)1. Open collector output
2. Totem-Pole Output
3. Tri-state output.
40) Mention the characteristics of MOS transistor? (R)
3.7
1. The n- channel MOS conducts when its gate- to- source voltage is positive.
2. The p- channel MOS conducts when its gate- to- source voltage is negative
3. Either type of device is turned of if its gate- to- source voltage is zero.
41) How schottky transistors are formed and state its use? (R)A schottky diode is formed by the combination of metal and semiconductor. The
presence of schottky diode between the base and the collector prevents the transistor from going into saturation. The resulting transistor is called as schottky transistor. The use of schottky transistor in TTL decreases the propagation delay without a sacrifice of power dissipation.
42) Why totem pole outputs cannot be connected together. (R)Totem pole outputs cannot be connected together because such a connection might
produce excessive current and may result in damage to the devices.
43) State advantages and disadvantages of TTL (R)
Adv:
Easily compatible with other ICs Low output impedance
Disadv: Wired output capability is possible only with tristate and open collector typesSpecial circuits in Circuit layout and system design are required.
44) What happens to output when a tristate circuit is selected for high impedance. (R)
Output is disconnected from rest of the circuits by internal circuitry.
45) Implement the Boolean Expression for EX OR gate using NAND Gates. (R)
46) Define Minterm & Maxterm. (R)A minterm of n variables is a product (logical AND) of the variables in which each
appears exactly once in true or complemented form.
A maxterm of n variables is a sum (Logical OR) of the variables in which each appears exactly once in true or complemented form.
47) List out the advantages and disadvantages of Quine-Mc Cluskey method? (R)The advantages are,
i) This is suitable when the number of variables exceed four. ii). Digital computers can be used to obtain the solution fast.
iii)Essential prime implicants, which are not evident in K-map, can be clearly seen in the final results.
3.8
The disadvantages are,i) Lengthy procedure than K-map. ii) Requires several grouping and steps as compared to K-map. iii) It is much slower. iv) No visual identification of reduction process. v) The Quine Mc Cluskey method is essentially a computer reduction method
48) What is the significance of high impedance state in tri-state gates? (R)In digital electronics three-state, tri-state, or 3-state logic allows an output port to
assume a high impedance state in addition to the 0 and 1 logic levels, effectively removing the output from the circuit. This allows multiple circuits to share the same output line or lines (such as a bus which cannot listen to more than one device at a time).
49) What is totem pole output? (R)Output stage consists of pull up transistors, diode resistor and pull down transistor. In
this output of two gates cannot be tied together. Whose operating speed is also high.
50) Draw the logic diagram of OR gate using universal gates. (R)
PART-B & C
1) Explain the operation of CMOS NAND and NOR Gate with the circuits and truth Table (16) [Nov/Dec‟11] (U)
2) Simplify the following Boolean function using 4 variable map
4. f(A,B,C,D) = Σ m(1,3,4,5,9,10,11) + Σd(6,8) and realize using NAND gates.(16) [Nov/Dec‟11]
5.F= Σ (0,1,2,8,10,11,14,15) (8) [May/June‟12]
6.F (A,B,C,D) = Σm (0,1,3,4,5,7,10,13,14,15)
5) Express the Boolean function in POS form and SOP form (C)
i. F = (A‟ + B‟)(B‟ + C‟) (4) [Apr/May‟10]
ii. F= A = B‟C (6) [Apr/May‟11]
6) Implement the following function using NOR gates. (AZ) (8) [Apr/May‟10]
Output = 1 when the inputs are Σm(0,1,2,3,4)
= 0 when the inputs are Σm(5,6,7)
7) Discuss the general characteristics of TTL and CMOS logic families.(8) [Apr/May‟10]U
8) Draw the schematic and explain the operation of a CMOS inverter. Also explain its characteristics. (8) [Apr/May‟11] U
9) Draw a TTL circuit with totem pole output and explain its working. (8) [Nov/Dec‟11] U
10)Simplify the following Boolean expression F = x‟y‟z‟ + x‟yz +xy‟z‟+xyz‟.(AZ)(8) [May/June‟12]
11) Differentiate between Min term and Max term . U (4) [May/June‟12]
12)Using K-map simplify the following expressions and implement using basic gates.
1. F = Σ (1,3,4,6)
2. F = Σ (1,3,7,11,15) + d(0,2,5) AZ [May/June‟12](12)
13)Simplify the given Boolean function using tabulation method
F=Σm(1,2,3,5,7,9,10,11,13,15) AZ [Nov/Dec‟12](16)
14) Draw the circuit diagram of a two input TTL NAND gate with tri-state output and explain its action ,clearly showing logic and voltage levels.(16) [Nov/Dec‟12] U
15)Prove that (x1+x2).(x1‟. x3‟+x3) (x2‟ + x1.x3) =x1‟x2 (8) E
16)Simplify using K-map to obtain a minimum POS expression: AZ
17)Reduce the following equation using Quine McClucky method of minimization
F (A,B,C,D) = Σm (0,1,3,4,5,7,10,13,14,15) AZ (16)18) Using a K-Map, Find the MSP from of F= Σ (0, 4, 8, 12, 3, 7, 11, 15) +d (5)
3.10
Using a K-Map, Find the MSP form of F= Σ (0-3, 12-15) + d (7, 11) U
19)Simplify the following using the Quine McClusky minimization technique D = f(a,b,c,d) = Σ(0,1,2,3,6,7,8,9,14,15).Does Quine McClusky take care of don‟t care conditions? In the above problem, will you consider any don‟t care conditions? Justify your answer AZ
20)List also the prime implicants and essential prime implicants for the above case (8) R
21)Determine the MSP and MPS focus of F= Σ (0,2,6,8,10,12,14,15) (8) E
22)State and Prove Demorgan‟s theorem (8) [May/June‟12] R
23) Determine the MSP form of the Switching function E
F( a,b,c,d) =Σ (0,2,4,6,8)+Σd(10,11,12,13,14,15)
24)Find the Min term expansion of f(a,b,c,d) =a‟(b‟+d)+acd‟ (8) R
25)Find a Min SOP and Min POS for f = b‟c‟d + bcd + acd‟ + a‟b‟c + a‟bc‟d (16) R
26) Find an expression for the following function using Quine McCluscky method
F= Σ (0, 2, 3,5,7,9,11,13,14,16,18,24,26,28,30) (16) R
27)Find the MSP representation for F(A,B,C,D,E) = Σm(1,4,6,10,20,22,24,26)+ Σd (0,11,16,27) using K- Map method, Draw the circuit of the minimal expression using only NAND gates (16) U
28)i. Show that if all the gates in a two level AND-OR gate networks are replaced by
NAND gates the output function does not change. (8) U
ii) Why does a good logic designer minimize the use of NOT gates? (8) U
29)Simplify the Boolean function F(A,B,C,D) = Σ m (1,3,7,11,15) + Σd (0,2,5) .if don‟t care conditions are not taken care, What is the simplified Boolean function .What are your comments on it? Implement both circuits (16) AZ
30) i.Implement Y = (A+C) (A+D‟) ( A+B+C‟) using NOR gates only (8) AZ
ii) Find a network of AND and OR gate to realize f(a,b,c,d) = Σ m (1,5,6,10,13 ,14) (8)
31) i) What is the advantages of using tabulation method? (8) E
ii) Determine the prime implicants of the following function using tabulation method
F(W,X,Y,Z) = Σ (1,4,6,7,8,9,10,11,15) (8 )
32)Explain the operation of3 I/P TTL NAND Gate with required diagram and truth table.(16) U
33)Convert the following function into product of Max terms.
F(A,B,C) = (A+B‟) (B+C) (A+C‟). (4) [Nov/Dec‟14]C
3.11
34) Using Quine McClusky method simplify the given function.
35)Draw the multiplicand two input NAND circuit for the following expression:
F = (AB‟ +CD‟)E + BC(A+B). (4) U
36) Draw and explain Tri state TTL inverter circuit diagram and explain its operation.(12) U
ASSISGNMENT
1. Define analog, discrete time and digital signals. R
2. What are some of the advantages digital systems compared to analog systems? R
3. Convert the following numbers as required in each case. 123410 = ( )2 25.62510 = ( )2
603.2310 = ( )2 ABCD16=( )2 15C.3816=( )2 R
4. Explain the difference between positive logic and negative logic. U
5. What are universal gates? Why are they called so? R
6. Use Boolean Algebra to show that A BC +AB C +AB C+ABC + ABC = A+BC AZ
7. Using 3-variable K - Map simplify the Boolean function given by AZ
F (a, b, c) = Σm (0, 2, 4, 5, 6, 7)
8. Using 4-variable K-Map simplify the Boolean function given by AZ
F (w, x, y, z) = Σm (2, 3, 10, 11, 12, 13, 14, 15)
9. Using K Map simplify in the product-of-sum form the function given by AZ
F(A,B,C,D = ΠM (0, 6, 10, 12)
10. In all digital systems and circuits two logic levels are defined, HIGH and LOW,
sometimes called 1 and 0 . Taking the example of two voltage levels, in positive logic,
HIGH level is denoted by higher voltage and LOW level is denoted by lower voltage, e.g., 5
volts and 0 volts. In negative logic, on the other hand, HIGH level is denoted by lower
voltage and LOW level by higher voltage, e.g., 0 volts and 5 volts. In other words, the two
are dual of each other. For example, an AND gate in positive logic will represent an OR
gate in negative logic. C
11. NAND and NOR gates are called universal gates. Normally any logic circuit will have
AND, OR, INVERT gates. These three gates are required to implement any logic function.
Individually either NAND or NOR gate can implement AND, OR, INVERT gates and hence
either one of them (NAND or NOR) can implement any logic function. C
3.12
UNIT II - COMBINATIONAL CIRCUITS PART-A
1) Define combinational logic. (R)When logic gates are connected together to produce a specified output for certain
specified combinations of input variables, with no storage involved, the resulting circuit is called combinational logic.
2) Explain the design procedure for combinational circuits. (R)The problem definition
Determine the number of available input variables & required O/P variables.
Assigning letter symbols to I/O variables
Obtain simplified Boolean expression for each O/P.
Obtain the logic diagram.
3) Define Half adder and full adder. (R)The logic circuit that performs the addition of two bits is a half adder. The circuit
that performs the addition of three bits is a full adder.
4) Define Decoder? (R)A decoder is a multiple - input multiple output logic circuit that converts
coded inputs into coded outputs where the input and output codes are different.
5) What is binary decoder? (R)A decoder is a combinational circuit that converts binary information from n input
lines to a maximum of 2n out puts lines.
6) Define Encoder? (R)An encoder has 2n input lines and n output lines. In encoder the output lines
generate the binary code corresponding to the input value.
7) What is priority Encoder? (R)A priority encoder is an encoder circuit that includes the priority function. In priority
encoder, if 2 or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence.
8) Define multiplexer? (R)Multiplexer is a digital switch. If allows digital information from several sources to be
routed onto a single output line.
9) What do you mean by comparator? (R)A comparator is a special combinational circuit designed primarily to compare the
relative magnitude of two binary numbers.
3.13
10) Give the applications of De-multiplexer. (R)De-multiplexers are used in digital processing, telecommunications, instrumentation
and computer architecture etc
11) Give other name for Multiplexer and Demultiplexer. (R)Multiplexer is a data selector, Demultiplexer is a data distributer.
12) List out the applications of multiplexer? (R)1. It can be used to realize a Boolean function 2. It can be used in communication systems e.g., time division multiplexing. 3. Data routing 4. Logic function generator 5. Control sequencer 6. Parallel-to-serial converter
13) What is multiplexer? (R)A multiplexer (or mux) is a device that selects one of several analog or digital input
signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output
14) Distinguish between a decoder and a demultiplexer. (U)A demux simply selects an output line, nothing more. It's a glorified switch. A
decoder takes n inputs, and uses those inputs to determine which of the 2n output lines is high. This is the difference, A decoder is designed to simply keep one line high. A demux is designed to set one output equal to the input (whether it be high, low, or a changing signal).
15) Write an expression for borrow and difference in a full subtractor circuit. (R) D = x‟y‟z + x‟yz‟ + xy‟z‟ + xyz
B = x‟z + x‟y + yz
16) Draw the circuit diagram for 4 bit Odd parity generator. (R)
17) Write an Expression for borrow and difference in a half subtractor circuit. (R) D = x‟y + xy‟
B = x‟y
18) Relate carry generate, carry propagate, Sum and carry out of a carry look ahead adder.(AZ)
19) Distinguish between decoder and encoder. (AZ)Decoder Encoder
One of the input lines is activated The input lines generate the binary code,corresponding to the binary input corresponding to the input value
Input of the decoder is an encoded Input of the encoder is a decoded
information presented as n‟ input information presented as 2n‟ inputs
producing 2n possible outputs producing n‟ outputs.
The input code generally has a fewer bits The input code generally has more bitsthan the output code. than the output code
20) Mention the uses of decoders. (R)1. Decoders are used in counter system. 2. They are used in analog to digital converter. 3. Decoder outputs can be used to drive a display system. 4. Used in code converters.
21) Give the applications of Demultiplexer. (R)1. It finds its application in Data transmission system with error detection. 2. One simple application is binary to Decimal decoder
22) What will be the maximum number of outputs for a decoder with a 6-bit data word? (R)For a 6-bit data word the maximum number of output for a decoder is, 26= 32
outputs.
23) Mention the uses of decoders. (R)1. Decoders are used in counter system. 2. They are used in analog to digital converter. 3. Decoder outputs can be used to drive a display system. 4. Used in code converters.
24) What is BCD adder? (R)A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum
digit also in BCD.
PART-B & C
1. Implement the switching function F= Σ (0,1,3,4,7) using a 4 input MUX and explain (16) AZ
2. Explain how will build a 64 input MUX using nine 8 inputMUXs (16) U
3. Implement the following function using suitable Multiplier
4. Explain how will build a 16 input MUX using only 4 input MUXs (16) U
5. Explain the operation of4 to 10 line decoder with necessary logic diagram (16)U
6. Design full adder and full sub tractor. (8) C
7. Design a 4 bit magnitude comparator to compare two 4 bit number (16) [May/June‟12] C
8. Design a 2 bit magnitude comparator and explain its operation in detail. (16) [Nov/Dec‟11] C
9. Construct a combinational circuit to convert given binary coded decimal number into an Excess 3 code for example when the input to the gate is 0110 then the circuit should generate output as1001 (16) C
10.Using a single 7483, draw the logic diagram of a 4 bit adder/sub tractor (8) U
11.Realize a Binary to BCD conversion circuit starting from its truth table (8) C
12.Design a combinational circuit which accepts 3 bit binary number and converts its equivalent excess 3 code (16) C
13.Explain carry look ahead adder. (8)[Apr/May‟10] U
14. Design a combinational circuit of 2-digit BCD adder. (8) [Apr/May‟11][May/June‟12] [Nov/Dec‟11] [Nov/Dec‟12].C
15.Draw and explain the block diagram of a 4 bit serial adder to add the contents of two registers.(10)[ Apr/May‟10] U
16. Design and implement conversion circuit for Binary to Gray code.(8)[Apr/May‟10]C
17.Multiply (1011)2 by (1101)2 using addition and shifting operation also draw block diagram of the 4 bit serial adder to add the contents of two registers.(8) [Apr/May‟10]U
18.Design a full adder using two half adder and an OR gate.(6) [Apr/May‟11] C
19.Draw the logic diagram of a 2 bit binary multiplier and explain its operation.(8) [Apr/May‟11] U
20.Design a combinational circuit that produces the product of 2 binary number
A= (A1, A0) x B =(B2,B1,B0). (10) [Nov/Dec‟10]C
21. Design 4 bit parallel adder/ subtractor and draw the logic diagram.(8) [Nov/Dec‟10] C
22.Design a 4bit BCD to excess -3 code converter. Draw the logic diagram.(16) [Nov/Dec‟11]. C
23.Construct a four bit even parity generator circuit using gates.(4) [Nov/Dec‟14] C
3.16
UNIT III SEQUENTIAL CIRCUITS PART A
1. Define Flip flop. (R)The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1
or 0 until directed by an input signal to change its state.
2. What are the different types of flip-flop? (R)There are various types of flip flops. Some of them are mentioned below they are,
i. RS flip-flopii. SR flip-flopiii. D flip-flopiv. JK flip-flopv. T flip-flop.
3. What is the operation of RS flip-flop? (R)∑ When R input is low and S input is high the Q output of flip-flop is set. ∑ When R input is high and S input is low the Q output of flip-flop is reset. ∑ When both the inputs R and S are low the output does not change. ∑ When both the inputs R and S are high the output is unpredictable.
4. What is the operation of D flip-flop? (R)
In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset.
5. What is the operation of JK flip-flop? (R)∑ When K input is low and J input is high the Q output of flip-flop is set. ∑ When K input is high and J input is low the Q output of flip-flop is reset. ∑ When both the inputs K and J are low the output does not change
∑ When both the inputs K and J are high it is possible to set or reset the flip-flop (ie) the output toggle on the next positive clock edge.
6. What is the operation of T flip-flop? (R)
T flip-flop is also known as Toggle flip-flop.
∑ When T=0 there is no change in the output. ∑ When T=1 the output switch to the complement state (ie) the output toggles.
7. Define race around condition. (R)In JK flip-flop output is fed back to the input. Therefore change in the output results
change in the input. Due to this in the positive half of the clock pulse if both J and K are high then output toggles continuously. This condition is called race around condition‟.
8. What is edge-triggered flip-flop? (R)
3.17
The problem of race around condition can solved by edge triggering flip flop. The term edge triggering means that the flip-flop changes state either at the positive edge or negative edge of the clock pulse and it is sensitive to its inputs only at this transition of the clock
9. What is a master-slave flip-flop? (R)A master-slave flip-flop consists of two flip-flops where one circuit serves as a master
and the other as a slave.
10. Define rise time. (R)The time required to change the voltage level from 10% to 90% is known as rise
time(tr).
11. Define fall time. (R)The time required to change the voltage level from 90% to 10% is known as fall
time(tf).
12. Define skew and clock skew. (R)The phase shift between the rectangular clock waveforms is referred to as skew and
the time delay between the two clock pulses is called clock skew.
13. Define setup time. (R)The setup time is the minimum time required to maintain a constant voltage levels
at the excitation inputs of the flip-flop device prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip flop. It is denoted as setup.
14. Define hold time. (R)The hold time is the minimum time for which the voltage levels at the excitation
inputs must remain constant after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip flop. It is denoted as thold .
15. Define propagation delay. (R)A propagation delay is the time required to change the output after the application of
the input.
16. Define registers. (R)A register is a group of flip-flops flip-flop can store one bit information. So an n-bit
register has a group of n flip-flops and is capable of storing any binary information/number containing n-bits.
17. Define shift registers. (R)The binary information in a register can be moved from stage to stage within the
register or into or out of the register upon application of clock pulses. This type of bit movement or shifting is essential for certain arithmetic and logic operations used in microprocessors. This gives rise to group of registers called shift registers.
18. What are the different types of shift registers? (R)3.18
There are five types. They are, _i. Serial In Serial Out Shiftii. Serial In Parallel Outiii. Shift Register Parallel Iniv. Serial Out Shift Registerv. Parallel In Parallel out Shift
vi. Bidirectional Shift Register.
19. Explain the flip-flop excitation tables for RS FF. (R) RS flip-flop
In RS flip-flop there are four possible transitions from the present state to the next state. They are,
i. _ 0_0 transition: This can happen either when R=S=0 or when R=1 and S=0.
ii. _ 0_1 transition: This can happen only when S=1 and R=0. iii. _ 1_0 transition: This can happen only when S=0 and R=1. iv. _ 1_1 transition: This can happen either when S=1 and R=0 or S=0 and
R=0.
20. Explain the flip-flop excitation tables for JK flip-flop. (R)
In JK flip-flop also there are four possible transitions from present state to next state. They are,
i. _ 0_0 transition: This can happen when J=0 and K=1 or K=0. ii. _ 0_1 transition: This can happen either when J=1 and K=0 or when
J=K=1. iii. _ 1_0 transition: This can happen either when J=0 and K=1 or when
J=K=1. iv. _ 1_1 transition: This can happen when K=0 and J=0 or J=1.
21. Define sequential circuit? (R)
In sequential circuits the output variables dependent not only on the present input variables but they also depend up on the past history of these input variables.
22. Give the comparison between combinational circuits and sequential circuits. U
Combinational circuits Sequential circuits
Memory unit is not required Memory unity is required
Parallel adder is a combinational Serial adder is a sequential circuitcircuit
3.19
23. Define synchronous sequential circuit. (R)In synchronous sequential circuits, signals can affect the memory elements only at discrete instant of time.
24. Define Asynchronous sequential circuit? (R)In asynchronous sequential circuits change in input signals can affect memory element at any instant of time.
25. Give the comparison between synchronous & Asynchronous sequential circuits?(R)
Synchronous sequential circuits Asynchronous sequential circuits. Memory elements are clocked flip-flops Memory elements are either unlocked flip -flops or time delay elements. Easier to design More difficult to design.
26. Draw the logic diagram for SR latch using two NOR gates. (U)
27. The following wave forms are applied to the inputs of SR latch. Determine the Q waveform Assume initially Q = 1. (U)
Here the latch input has to be pulsed momentarily to cause a change in the latchOutput state and the output will remain in that new state even after the input pulse is over.
28. Give the comparison between synchronous & Asynchronous counters. (U)
Asynchronous counters Synchronous counters
In this type of counter flip-flops are In this type there is no connectionconnected in such a way that output of between output of first flip-flop and
1st flip-flop drives the clock for the next clock input of the next flip - flopflipflop
All the flip-flops are Not clockedsimultaneously simultaneously
3.20
29. The t pd for each flip-flop is 50 ns. Determine the maximum operating frequency for MOD 32 ripple counter.(E)
f max (ripple) = 5 x 50 ns = 4 MHZ
30. What is a ripple counter? (R)A register that goes through a prescribed sequence of states upon the application of input pulse called a counter. A flip flop output transition serves as a source for triggering other flip flops is called ripple counter.
31. Define state diagram. (R)State diagram is a graphical representation of state table. A state is represented by a circle, and the transitions between states are indicated by direct line connecting the circles. This line is labeled by two binary numbers (Input /Output) separated by a slash.
32. What is the use of state diagram? (R)It gives a pictorial view of state transitions and is the form more suitable for human
interpretation of the circuit‟s operation.
33. What is state table? (R)The time sequence of inputs, outputs ,and flip flop states can be enumerated in a
state table. It consists present state, input, next state and output sections
34. What is a state equation? (R)The behavior of a clocked sequential circuit can be described algebraically by means
of state equations. It specifies the next state as a function of the present state and inputs.
35. What is the classification of sequential circuits? (R)Synchronous sequential circuit and Asynchronous sequential circuit
36. Mention any two differences between the edge triggering and level triggering. (R)In level trigger mode, the input signal is sampled when the clock signal is either high
or low whereas in edge trigger mode the input signal is sampled at rising or at the falling edge, level triggering is sensitive to glitches whereas edge trigger is non sensitive
37. Write down the characteristic equation of JK Flip flop. (R)Q(t+1) = JQ‟ + K‟Q
38. Realize T-FF from JK FF. (R)J and K are having a complement input (with each other) means that is called Toggle
(T) Flip flop. J = x : K = x‟
39. Draw the logic diagram of T flip flop using JK flip flop. (U)
3.21
40. How do you eliminate the race around condition in a JK Flip flop? (R)Race around condition in a JK FF is eliminated by using either edge triggered flip
flop or master slave flip flop.
41. Draw the state table and excitation table of T Flip flop. (R)
PART-B & C
1) Explain the operation of JK and clocked JK flip-flops with suitable diagrams (16)U
2) Draw the state diagram of a JK flip- flop and D flip flop (16) U
3) Design and explain the working of a synchronous mod 3 counter (16) C
4) Design and explain the working of a synchronous mod 7 counter (16) C
5) Design a synchronous counter with states 0,1, 2,3,0,1 . Using JK FF (8) C
6) Using SR flip flops, design a parallel counter which counts in the sequence (8)C
000,111,101,110,001,010,000 .
7) Using JK flip flops, design a parallel counter which counts in the sequence (8)C
000,111,101,110,001,010,000 .
8) Draw and explain Master-Slave JK flip-flop (8) [Nov/Dec‟09] U
9) Draw as asynchronous 4 bit up-down counter and explain its working (16) U
10) Using D flip flop ,design a synchronous counter which counts in the sequence (16) C
000, 001, 010, 011, 100, 1001,110,111,00011)Design a binary counter using T flip flops to count in the following sequences
(i) 000,001,010,011,100,101,110,111,000 (ii) 000,100,111,010,011,000 (16) C
12)Design a 3 bit synchronous counter using JK Flip flop (8) [Nov/Dec‟14] C
13)Draw and explain the operation of four bit Johnson counter (8) U
14)How will you convert a D flipflop into JK flipflop? (8) [Nov/Dec‟09] U
3.22
15)Explain in detail the operation of a 4 bit binary ripple counter. (16) U
16)Design a sequence detector which detect the sequence 01110 using D flip flops (one bit over lapping.(16) [Nov/Dec‟12] C
17) Design a 4 bit bi-directional shift register. (8) [Nov/Dec‟12] C
18) Explain the difference between a state table, a characteristic table and an excitation
table,(4) [Nov/Dec‟14] AZ
19) Design a 3 bit Johnson counter and explain its operation.(8) [Nov/Dec‟12] C
20)Explain in detail the operation of a 4 bit binary ripple counter.(16) [Nov/Dec‟09] U
21)Construct a clocked JK flip flop which is triggered at the positive edge of the clock pulse
from a clocked SR flip flop consisting of NOR gates (6) [Apr/May‟11] C
22)What is meant by Universal Shift Register? Explain the principle of operation of 4 bit universal shift register.(16) [Apr/May‟10] [Nov/Dec‟10] U
23)How will you convert a D flipflop into T flipflop? (6) [Nov/Dec‟09] U
24)Design a serial binary adder (8) [Apr/May‟11] C
25) Explain the operation of a BCD ripple counter with JK flip flops(8) [Apr/May‟10] U
26)Design and draw the output waveform of UP/DOWN counter using JK FF.(16) [May/Jun‟12] C
27)Explain the design steps of Mod n counter.(8) [May/Jun‟12] C
28)Explain the operation of shift and ring counters.(8) [May/Jun‟12] U
29) Draw the logic diagram of master slave SR flip flop and explain the working with truth table.(10) [Nov/Dec‟11]U
30)Design a D flip flop using JK FF and explain with its truth table.(6) [Nov/Dec‟11]C
31)Draw the logic diagram of 4 bit binary UP?DOWN synchronous counter and explain with its truth table. Also draw the timing diagram.(16) [Nov/Dec‟11]U
32)Provide the characteristic table, characteristic equation and excitation table of D flip flop and JK flip flop.(6) [Nov/Dec‟10]C
33)With a neat state diagram and logic diagram, design and explain the sequence of states of BCD counter.(16) [Nov/Dec‟10]C
34)Design a 3 bit ring counter and find the mod of the designed counter (6) [Nov/Dec‟10]C
3.23
35) Design a clocked sequential machine using T FF for the following state diagram.(use straight binary assignment)C
ASSIGNMENT
1. Implement the following Boolean function using a single 4 to 1 Multiplexer. F (A,B,C,D) = Σ m ( 0, 1, 2, 4, 6, 9, 12, 14 ) AZ
2. Implement a Full Subtractor using a 3 to 8 Decoder. AZ
3. If Ai and Bi are the two bits to be added in the ith stage of a multi-bit adder, Gi = Ai . Bi and Pi = Ai EXOR Bi These parameters are used to predict Co of each stage if A and B of the stage is known using the Ci of the first stage. The equation Ci+1 = Gi + Pi Ci is used to predict the carry out of ith stage if the carry in of that stage is known, which in turn can be predicted recursively from the first stage. U
4. Design a circuit to generate odd parity if the data is represented with 4 bits. 12. Design a 1-bit full adder with two half adders and minimum number of additional gates. C
5. A 4-bit Serial-in, Parallel-out left shift-Shift Register is loaded with an initial bit pattern 1100. Write the sequence of bit patterns as the clock is applied to the Shift Register if bits b0 and b1 are connected to the serial input through an EXOR gate. b) After how many clock cycles will the initial pattern 1100 return? U
6. A universal shift register can be used a) as a delay element to delay a serial bit stream by a fixed number of clock cycles, b) as serial to parallel converter of a it stream, c) as a parallel to serial converter of a bit stream. d) All of the above. U
3.24
UNIT- IV MEMORY DEVICES PART -A
1. Explain ROM.(U)A read only memory (ROM) is a device that includes both the decoder and the OR
gates within a single IC package. It consists of n input lines and m output lines. Each bit combination of the input variables is called an address. Each bit combination that comes out of the output lines is called a word. The number of distinct addresses possible with n
input variables is 2n.
2. What are the types of ROM? 1.PROM
2.EPROM
3.EEPROM
3. Explain PROM. (U)PROM (Programmable Read Only Memory)
It allows user to store data or program. PROMs use the fuses with material like nichrome and polycrystalline. The user can blow these fuses by passing around 20 to 50 mA of current for the period 5 to 20μs.The blowing of fuses is called programming of ROM. The
PROMs are one time programmable. Once programmed, the information is stored permanent.
4. Explain EPROM. (U)EPROM(Erasable Programmable Read Only Memory) EPROM use MOS circuitry.
They store 1‟s and 0‟s as a packet of charge in a buried layer of the IC chip. We can erase the stored data in the EPROMs by exposing the chip to ultraviolet light via its quartz window for 15 to 20 minutes. It is not possible to erase selective information. The chip can be reprogrammed.
5. Explain EEPROM. (U)EEPROM(Electrically Erasable Programmable Read Only Memory) EEPROM also use
MOS circuitry. Data is stored as charge or no charge on an insulated layer or an insulated floating gate in the device. EEPROM allows selective erasing at the register level rather than erasing all the information since the information can be changed by using electrical signals.
6. What is RAM?(R)Random Access Memory. Read and write operations can be carried out.
7. Define ROM. (R)A read only memory is a device that includes both the decoder and the OR gates
within a single IC package.
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8. Define address and word. (R)In a ROM, each bit combination of the input variable is called on address. Each bit
combination that comes out of the output lines is called a word.
9. What are the types of ROM. (R)1. Masked ROM.
2. Programmable Read only Memory
3. Erasable Programmable Read only memory.
4. Electrically Erasable Programmable Read only Memory.
10. What is programmable logic array? How it differs from ROM? (R) In some cases the number of don‟t care conditions is excessive, it is more economical
to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM.
11. What is mask - programmable? (R)With a mask programmable PLA, the user must submit a PLA program table to the
manufacturer.
12. What is field programmable logic array? (R)The second type of PLA is called a field programmable logic array. The user by means
of certain recommended procedures can program the EPLA.
13. List the major differences between PLA and PAL. (R)PLA: Both AND and OR arrays are programmable and Complex Costlier than PAL
PAL: AND arrays are programmable OR arrays are fixed Cheaper and Simpler
14. Define PLD. (R)Programmable Logic Devices consist of a large array of AND gates and OR gates that
can be programmed to achieve specific logic functions.
15. Give the classification of PLDs. (R)PLDs are classified as PROM(Programmable Read Only Memory), Programmable
Logic Array(PLA), Programmable Array Logic (PAL), and Generic Array Logic(GAL)
16. Define PROM. (R)PROM is Programmable Read Only Memory. It consists of a set of fixed AND gates
connected to a decoder and a programmable OR array.
17. Define PLA (R)PLA is Programmable Logic Array(PLA). The PLA is a PLD that consists of a
programmable AND array and a programmable OR array.
18. Define PAL (R)
3.26
PAL is Programmable Array Logic. PAL consists of a programmable AND array and a fixed OR array with output logic.
19. What is CPLD ? (R)CPLDs are Complex Programmable Logic Devices. They are larger versions of PLDs
with a centralized internal interconnect matrix used to connect the device macro cells together.
20. How many words can a 16x8 memory can store ? (R)A 16x8 memory can store 16,384 words of eight bits each.
21. Why RAMs are called as Volatile ? (R)RAMs are called as Volatile memories because RAMs lose stored data when the
power is turned OFF.
22. Define Static RAM and dynamic RAM. (R)Static RAM use flip flops as storage elements and therefore store data indefinitely as
long as dc power is applied.
Dynamic RAMs use capacitors as storage elements and cannot retain data very long without capacitors being recharged by a process called refreshing.
23. List the basic types of DRAMs. (R)Asynchronous DRAM FPM DRAM , EDO DRAM, BEDO DRAM, SDRAM, RDRAM
24. List the two categories of RAMs. (R)Static RAM and dynamic RAM
25. List the two types of SRAM. (R)Non-volatile SRAM, Asynchronous SRAM
26. Define Cache memory. (R)It is a relatively small, high-speed memory that can store the most recently used
instructions or data from larger but slower main memory.
27. Give the feature of flash memory. (R)The ideal memory has high storage capacity, non-volatility; in-system read and write
capability, comparatively fast operation. The traditional memory technologies such as ROM, PROM, EEPROM individually exhibits one of these characteristics, but no single technology has all of them except the flash memory.
28. List the three major operations in a flash memory. (R)Programming, Read and Erase operation.
29. List basic types of programmable logic devices. (R)1. Read only memory 2. Programmable logic Array 3. Programmable Array Logic
30. What is mask - programmable? (R)
3.27
With a mask programmable PLA, the user must submit a PLA program table to the manufacturer.
31. List the major differences between PLA and PAL. (R)PLA has Programmable AND Gate linked with Programmable OR Gate. PAL is an
combinational PLD that was developed to overcome certain disadvantage of PLA. PLA shows longer delay due to additional fusible links which results from using two programmable array and increase circuit complexity. Thus, PAL is used which is less complex and fast to implement. PAL consists of programmable AND linked with fixed OR.
32. Define FPGA. (R)FPGA is a field programmable gate array, which is the next generation in the
programmable logic devices. The word field refers to the ability of the gate arrays to be program for a specific function by the end user. The word array indicates a series of columns and roes of gates that can be programmed.
33. Comparison between SRAM & DRAM. (U)SRAM DRAM
SRAM is static DRAM is dynamic
Internal latches are used to store the capacitors store the binary information in theinformation form electrical charges which is provided inside
the chip by MOS transistors.
Stored information is valid till the It needs continuous refreshing.power is applied to the unit. So No needof refreshment.
SRAM is more expensive DRAM is cheap.
Storage capacity is less Storage capacity is more
SRAM is commonly used in cache Cheaper DRAM is used in main memorymemory
34. Comparison between PROM, PAL, PLA. (U)PROM consists of set of AND gates connected to a decoder and a programmable OR
array. In PAL AND array is programmable and OR array is fixed. But PLA , Both array are programmable.
35. What is PAL? How does it differ from PLA? (U)PAL consists of programmable AND linked with fixed OR. PAL is a combinational
PLD that was developed to overcome certain disadvantage of PLA. PLA shows longer delay due to additional fusible links which results from using two programmable array and increase circuit complexity. Thus, PAL is used which is less complex and fast to implement.
3.28
36. What is access time and cycle time of a memory? (R)Access time of memory is the time required to select a word and read it.
Cycle time of memory is the time required to complete a write operation.
37. What is the difference between PAL and PLA? (R)PLA is a kind of programmable logic device used to implement combinational logic
circuit. It has Programmable AND Gate linked with Programmable OR Gate.
38. Give the difference between RAM and ROM. (U)Random Access Memory Read and write operation are performedRead Only Memory -- It performs only the read operation
39. Mention few applications of PLA and PAL. (R)It is used as mux and demux , used for implement half adder & full adder, by
program it.
40. How the memories are classified? (R)Memories are classified as Random access memory and Read only memory.
RAM are further classified as Static RAM and Dynamic RAM.
ROM are further classified as PROM, EPROM , EEPROM
PART-B & C
1. Draw a RAM cell and explain its working. (8) U
2. Write short notes on (i) RAM (ii) Types of ROM‟s (8) U
3. List the PLA programmable for BCD to Excess -3-code convertor circuits and show its implementation for any two output functions (16) U
4. Generate the following Boolean functions with PAL with 4inputs and 4outputs
Y3 = A‟BC‟D+A‟BCD‟+A‟BCD+ABD‟
Y2 = A‟BCD‟+A‟BCD+ABCD
Y1 = A‟BC‟+A‟BC+AB‟C+ABC‟
Y0 = ABCD (16)C
5. Implement the following functions using PLA. (16) AZ
F1=Σm(1,2,4,6); F2=Σm(0,1,6,7) F3=Σm(2,6)
6. Implement the given functions using PROM and PAL (16) AZ
F1=Σm(0,1,3,5,7,9); F2=Σm(1,2,4,7,8,10,11)) Implement the given functions using PLA F1=Σm(0,1,2,4,6,7); F2=Σm(1,3,5,7); F3=Σm(0,2,3,6) (16)U
3.29
7. Draw the block diagram of a PLA device and briefly explain each block. (8) U
8. Write short note on Field Programmable Gate Array (FPGA) (8) U
9. Design a 16 bit ROM array and explain the operation (8) C
10.Write short note on Field Programmable Gate Array (FPGA) (8) U
11.Implement the following Boolean functions with a PLA (16) [Nov/Dec 09]. AZ
a. F1 ( A, B,C ) = Â (0,1, 2, 4 )
b. F2 ( A, B,C ) = Â (0,5, 6, 7 )
c. F3 ( A, B,C ) = Â (0,3,5, 7 ).
12.Design a combinational circuit using a ROM. The circuit accepts a three bit number and outputs a binary number equal to the square of the input number. (16) [Nov/Dec 09]. C
13. We expand the word size of a RAM by combining two or more RAM chips. For instance, we can use two 32 ¥ 8 memory chips where the number 32 represents the number of
words and 8 represents the number of bits per word, to obtain 32 ¥ 16 RAM. In this case the number of words remains the same but length of each word will two bytes long. Draw a block diagram to show how we can use two 16 ¥ 4 memory chips to obtain a 16 ¥8 RAM. (8) [Apr/May 10].C
14.Explain the principle of operation of Bipolar SRAM cell. (8)[Apr/May 10].U
15.A combinational circuit is defined as the functions
F1 = A B¢C¢+ A B¢C + A B C
F2 = A¢ B C + A B¢C + A B C
Implement the digital circuit with a PLA having 3 inputs, 3 product terms, and 2 outputs. (8) [Apr/May 10].AZ
16. Draw a PLA circuit to implement the functions
F1 = A¢ B + A C¢+ A¢ B C¢ ; F2 = ( AC + A B + BC )¢
. (8) [Nov/Dec 10].AZ
17.Write a note on FPGA. (8) [Nov/Dec 10]. U
18.Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and generates an output binary number equal to the square of the input number.(10) [Apr/May‟11]. C
19. Briefly explain the EPROM and EEPROM technology. (6) [Apr/May 11]. U
20. Implement the following functions using 3 input, 4 product term and 2 output PLA
3.30
F1 = A B¢+ AC + A¢ B C¢
F2 = (AC + B C )¢
(8) [Apr/May 11].AZ
21. With logic diagram, explain the basic macrocell. (8) [Apr/May 11]. U
22. Draw the basic block diagram of PLA device and explain each block. List out its application. Implement a combinational circuit using PLA by taking a suitable Boolean function. (16) [Nov/Dec 11]. U
23.Explain the operations of static and dynamic MOS RAM cell with necessary diagrams. (12) [Nov/Dec 11]. U
24.What are advantages of FPGA? (4) R
25.Discuss the classification of ROM and ROM memories. (8) [May/Jun 12]. AZ
26.Explain Memory decoding and Memory expansion of Digital System. (8) [May/Jun 12].U
27.Write short notes on :
(i) FPGA and its application (8)
(ii) Programme Logic Array (8) [May/Jun 12]. U
28.Implement a 3-bit up/down counter using PAL devices. (8) [Nov/Dec 12]. AZ
29.Implement binary to Gray code converter using PROM devices. (8) [Nov/Dec 12]. AZ
30.Write short notes on :
(i) Memory decoding (8)
(ii) Memory expansion (8) [Nov/Dec 12]. U
31.Using eight 64x8 ROM chips with an enable input and a decoder, construct a 512x8 ROM. (10) [Nov/Dec 14] AZ
32.Compare and contrast PAL and PLA (4). [Nov/Dec 14]. U
3.31
UNIT V - SYNCHRONOUS AND AYNCHRONOUS SEQUENTIAL CIRCUITS
PART-A
1) What is the classification of sequential circuits? (R)i. Synchronous sequential circuit ii. ASynchronous sequential circuit
2) Give the comparison between synchronous & Asynchronous sequential circuits? (U)S.No Synchronous sequential circuits Asynchronous sequential circuits
1 Memory elements are clocked flip- Memory elements are either unclockedflops flip-flops or time delay elements.
2 The change in input signals can The change in input signals can affectmemory element at any instant of time.
activation of clock signal.
3 The maximum operating speed of Because of the absence of clock, it canclock depends on time delays operate faster than synchronousinvolved. circuits.
4 Easier to design More difficult to design
3) Define Asynchronous sequential circuit? (R)
Asynchronous sequential circuit output depends on the input and present state . It does not use clock pulse, the change of internal states depend on the change in input variables. The memory elements in asynchronous sequential circuit are time delay elements.
4) What is fundamental mode? (R)
In fundamental mode circuit, all of the input signals are considered to be levels. Fundamental mode operation assumes that the input signals will be changed only when the circuit is in a stable state and that only one variable can change at a given time.
5) What are the problems involved in asynchronous circuits? (R)Timing problem involved in the feedback path
9) What are secondary variables? (R)
Present state variables in asynchronous sequential circuits are called secondary variables
3.32
10) What are excitation variables? (R)Next state variables in asynchronous sequential circuits.
11) What is fundamental mode sequential circuit? (R)
-input variables changes if the circuit is stable. -inputs are levels, not pulses.-only one input can change at a given time.
12) What are pulse mode circuit? (R)-inputs are pulses. -width of pulses are long for circuit to respond to the input. -pulse width must not be so long that it is still present after the new state is reached.
13) What are the significance of state assignment? (R)
In synchronous circuits-state assignments are made with the objective of circuit reduction.
Asynchronous circuits-its objective is to avoid critical races.
14) When the race condition occurs? (R)
Two or more binary state variables change their value in response to the change in i/p variable.
15) What is non critical race? (R)
-final stable state does not depend on the order in which the state variable changes. -race condition is not harmful.
16) What is critical race? (R)
-final stable state depends on the order in which the state variable changes. -race condition is harmful.
17) When does a cycle occur? (R)In asynchronous circuit makes a transition through a series of unstable state.
18) What are the different techniques used in state assignment? (R)Shared row state assignment. And One hot state assignment.
19) What are the steps for the design of asynchronous sequential circuit? (R) i. Construction of primitive flow table. ii. Reduction of flow table. iii. State assignment is made. iv. Realization of primitive flow table.
20) What is hazard? (R)
3.33
In an unwanted switching transients occurs in the sequential circuit is called hazards.
21) What is static 1 hazard? (R)-output goes momentarily 0 when it should remain at 1.
22) What is static 0 hazard? (R)-output goes momentarily 1 when it should remain at 0.
23) What is dynamic hazard? (R)-output changes 3 or more times when it changes from 1 to 0 or 0 to 1.
24) What is the cause for essential hazards? (R)Unequal delays along 2 or more path from same input introduce a essential hazard.
25) What is flow table? (R)In a state table of a synchronous sequential network is called flow table
26) What is SM chart? (R)
Chart which describes the behavior of a state machine is called SM Chart. It is used in hardware design of digital systems.
27) What are the advantages of SM chart? (R)i. Easy to understand the operation. ii. Easy to convert to several equivalent forms.
28) What is primitive flow chart? (R)Only one stable state per row.
29) What is combinational circuit? (R)Output depends on the given input. It has no storage element.
30) What is state equivalence theorem ? (R)
Two states SA and SB, are equivalent if and only if for every possible input X sequence, the outputs are the same and the next states are equivalent i.e., if SA (t + 1) = SB (t + 1) and ZA = ZB then SA = SB.
31) What do you mean by distinguishing sequences? (R)
Two states, SA and SB of sequential machine are distinguishable if and only if their exist at least one finite input sequence which, when applied to sequential machine causes different output sequences depending on whether SA or SB is the initial state.
32) Define merger graph. (R)
3.34
The merger graph is defined as follows. It contains the same number of vertices as the state table contains states. A line drawn between the two state vertices indicates each compatible state pair. It two states are incompatible no connecting line is drawn.
33) Explain the procedure for state minimization. (U)
1. Partition the states into subsets such that all states in the same subsets are 1 -equivalent.
2. Partition the states into subsets such that all states in the same subsets are 2 -equivalent.
3. Partition the states into subsets such that all states in the same subsets are 3 -equivalent.
34) Define state table. (R)
For the design of sequential counters we have to relate present states and next states. The table, which represents the relationship between present states and next states, is called state table.35) What are the steps for the design of asynchronous sequential circuit? (R)
1. Construction of a primitive flow table from the problem statement.
2. Primitive flow table is reduced by eliminating redundant states using the state reduction. 3. State assignment is made 4. The primitive flow table is realized using appropriate logic elements.
36) Define primitive flow table. (R)
It is defined as a flow table which has exactly one stable state for each row in the table. The design process begins with the construction of primitive flow table.
37) What are the types of asynchronous circuits? (R)1. Fundamental mode circuits 2. Pulse mode circuits.
38) What are races? (R)
When 2 or more binary state variables change their value in response to a change in an input variable, race condition occurs in an asynchronous sequent ial circuit. In case of unequal delays, a race condition may cause the state variables to change in an unpredictable manner.
39) Define non critical race.
If the final stable state that the circuit reaches does not depend on the order in which the state variable changes, the race condition is not harmful and it is called a non critical race.
40) Define critical race? Give an Example. (R)
3.35
If the final stable state depends on the order in which the state variable changes, the race condition is harmful and it is called a critical race.
41) What is a cycle? (R)
A cycle occurs when an asynchronous circuit makes a transition through a series of unstable states. If a cycle does not contain a stable state, the circuit will go from one unstable to stable to another, until the inputs are changed.
42) Define flow table in asynchronous sequential circuit. (R)
In asynchronous sequential circuit state table is known as flow table because of the behaviour of the asynchronous sequential circuit. The stage changes occur in independent of a clock, based on the logic propagation delay, and cause the states to .flow. from one to another.
43) Write short note on shared row state assignment. (R)
Races can be avoided by making a proper binary assignment to the state variables. Here, the state variables are assigned with binary numbers in such a way that only one state variable can change at any one state variable can change at any one time when a state transition occurs. To accomplish this, it is necessary that states between which transitions occur be given adjacent assignments. Two binary are said to be adjacent if they differ in only one variable.
44) Write short note on one hot state assignment. (R)
The one hot state assignment is another method for finding a race free state assignment. In this method, only one variable is active or hot for each row in the original flow table, ie, it requires one state variable for each row of the flow table. Additional row are introduced to provide single variable changes between internal state transitions.
45) Compare the ASM chart with a conventional flow chart. (U)
A conventional flow chart describes the procedural steps and decision paths of an algorithm in a sequential manner, without taking into consideration their time relationship.
The ASM chart describes the sequence of events ,as well as timing relationship between the states of a sequential controller and the events that occur whilke going from one state to the next.46) Draw the block diagram for Moore model. (U)
47) What are hazard free digital circuits? (R)
3.36
Hazard in combinational circuits can be removed by covering any two minterms that may produce a hazard with a product term common to both. The removal of hazards are require the addition of redundant gates to the circuit.48) Differentiate Moore machine from Mealy machine.(U)
In Mealy model , the output is a function of both present state and the input. In Moore model, the output is a function of only the present state.
49) What are the basic building blocks of a Algorithmic state machine chart. (R)The basic building blocks of ASM chart are State box, decision box and conditional box.50) What is meant by hazard and how it could be avoided? (R)
In an unwanted switching transients occurs in the sequential circuit is called hazards. I t could be avoided by adding extra gate.
51) What is state Table? (R)
The time sequence of inputs, outputs ,and flip flop states can be enumerated in a state table. It consists present state, input, next state and output sections52) Differentiate fundamental mode and pulse mode asynchronous sequential circuits.(U)
fundamental mode circuit pulse mode circuits
All of the input signals are considered to The inputs are pulses rather than levelsbe levels.
Fundamental mode operation assumes In this mode of operation the width ofthat the input signals will be changed the input pulses is critical to the circuitonly when the circuit is in a stable state operation The input pulse must be long
enough for the circuit to respond to theinput but it must not be so long as to bepresent even after new state is reached.
3.37
Only one variable can change at a given The state of the circuit may maketime. another transition.
PART B & C
1) What is the objective of state assignment in asynchronous circuit? (16) R
2) Realization for the following Boolean function f(A,B,C,D) = Σm(0,2,6,7,8,10,12) (16)R
3) Summarize the design procedure for asynchronous sequential circuit Discuss on Hazards and races.U
4) Develop the state diagram and primitive flow table for a logic system that has 2 inputs, x And y and an output z. And reduce primitive flow table. The behavior of the circuit is stated as follows. Initially =y=0. Whenever x=1 and y = 0 then z=1, whenever x = 0 and y = 1 then z = 0.When x=y=0 or x=y=1 no change in z to remains in the previous state. The logic system has edge triggered inputs without having a clock the logic system changes state on the rising edges of the 2 inputs. Static input values are not to have any effect in changing the Z output. (16) C
5) A pulse mode asynchronous machine has two inputs. It produces an output whenever two consecutive pulses occur on one input line only . The output remains at 1‟ until a pulse has occurred on the other input line. Draw the state table for the machine (16) C
6) Construct the state diagram and primitive flow table for an asynchronous network that has two inputs and one output. The input sequence X1X2 = 00,01,11 causes the output to has two inputs and one output. C
7) Discuss on the different types of Hazards that occurs in asynchronous sequential circuits. (16) U
8) Write short note on races and cycles that occur in fundamental mode circuits. (16)U
9) Design an asynchronous sequential circuit with two inputs X and Y and with one output Z. Whenever Y is 1,(16) input X is transferred to Z.
When Y is 0,the output does not change for any change in X. (16)C
10) Draw the ASM chart for the following state diagram.(8) [Apr-May 2011]R
3.38
11) Design the following sequential circuit using D Flip flop and logic gates. (8)C
12)What is an Hazard? What are the types of hazards? Check whether the following circuit contains an hazard or not
Y= x1 x2 + x2‟ x3 If the hazard is present, demonstrate its removal. (16)AZ
13)Design a three bit binary counter using T flipflops. (16) [Nov/Dec 09].C
14)Design a negative-edge triggered T flipflop‟. (16) [Nov/Dec 09]. C
15)What are called as essential hazards? How does the hazard occur in sequential circuits? How can the same be eliminated using SR latches? Give an example. (16) [Apr/May 10]. U
16)Differentiate critical races from non-critical races. (6) [Nov/Dec 10].U
17)Explain the steps involved in the reduction of state table. (10) [Nov/Dec 10]. U
18)What is an Hazard? What are the types of hazards? Check whether the following
circuit contains an hazard or not Y = x x + x ¢x . If the hazard is present,1
demonstrate its removal. (16) [Apr/May 11].U
19)Write short notes on shared row state assignment with an example. (8) [Nov/Dec 11]. U
20)Explain the method to eliminate static hazard in an asynchronous circuit with an example. (10) [Nov/Dec 11]. U
21)Write short notes on VERILOG. (6) [Nov/Dec 11] U
22)A sequential circuit has three D flip flops. A, B and C and one input x . It is desired by the following flip flop input functions
DA = ( B C¢+ B¢C )x + ( B C + B¢C¢ )x¢
DB = A , DC = B
Derive the state table for the circuit and draw two state diagrams for x = 0 , and other for x = 1 . (8) [Nov/Dec 11]C
23)With an example, explain the use of algorithmic state machines. (8) [May/Jun 12]. U
24)Describe the method to analyze the behavior of a synchronous sequential circuit. (8) [May/Jun 12]. AZ
3.39
25)Write short notes on:
(i) Incompletely specified state machines (8)
(ii) Hazard free switching circuits (8) [May/Jun 12]. U
26)Design the following circuits using verilog
(i) 4 to 1 multiplexer (8)
(ii) 2 bit up/down counter. (8) [Nov/Dec 12]. C
27)Write short notes on races and hazards that occur in asynchronous circuits. Discuss a method used for race free assignment with example. U
28)For the state diagram shown in fig (1), design a synchronous sequential circuit using JK flip-flop. C
29)Design an asynchronous sequential circuit with inputs A an B and an output
Y. Initially and at any time if both the inputs are 0, the output, Y is equal to 0.
When A or B becomes 1, Y becomes 1. When the other input also becomes 1, Y
becomes 0. The output stays at 0 until the circuit goes back to initial state. C
ASSIGNMENT
1. List the PLA programming table for following Boolean functions. Aa) W = A+BC+BD b) X = B‟C + B‟D + BC‟D‟ c) Y = CD + C‟D‟ d) Z = D‟
2. What is the size specification of PLA that could implement one digit BCD adder? Give the number of inputs, outputs, and product terms required. R
3. Construct the ROM table to implement the following functions using 24 x 4 ROM assuming all inputs and outputs are active high. AZ
a) Y1 (a,b,c,d) = Σm(0,1,2,5,7,8,10,14,15) b) Y2 (a,b,c,d) = Σm(0,2,4,5,6,7,8,10,12)c) Y3 (a,b,c,d) = Σm(0,1,2,3,4,6,8,9,10,11)
4. How many 32x16 ROMs with enable will be required to construct a 128x16 ROM? What type of decoder will you need for this design? 10. You are asked to build a digital lock‟ which opens ONLY with the combination 0111. Design a
synchronous digital system that the electronic system of this lock would comprise, using: a) D flip-flops b) J-K flip-flops
5. Design a synchronous 3-bit Up/Down counter having Gray code sequence. 12. How many 256x8 RAM chips are needed to provide a memory capacity of 4096 bytes? a. How many address lines must be used to access 4096 bytes? How many of these lines are connected to the address inputs of all chips? b. How many lines must be decoded for the chip-select inputs? C
6. Implement the following function with 8x1 multiplexer. F(A,B,C,D) = Σ(0,1,3,4,8,9,15) with A,B,C connected to S0, S1, S2 respectively. AZ
7. Find the Boolean function that a 8x1 multiplexer implement with A,B,C connected to select lines S2,S1,S0 respectively, if I0=0, I1=D, I2=0, I3=D‟, I4=I5=D, I6=0, I7=1. AZ
8. Specify the no of address lines, no of data lines and total memory size in bytes for following chips specifications. a. 2K x 16 b. 64K x 32. U
9. Obtain the excitation table of the JK' flip-flop, i.e. A JK flip-flop with an inverter between external input K' and internal input K. U
10. A set-dominate flip-flop has set and reset inputs. It differs from a conventional RS flip-flop in that an attempt to simultaneously set and reset results in setting the flip-flop. Obtain the excitation table of such a flip-flop? U
11. Design a binary counter having the following repeated binary sequence. Use JK flip-flops. 0, 1, 2 .... C
12. How many flip-flops will be complemented in a 10-bit binary ripple counter to reach the next count after the following count: 1001100111. A
3.40
4.1
PANIMALAR ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS & COMMUNICATION
ENGINEERING
EC6303 SIGNALS & SYSTEMS
SOLVED TWO MARKS & PART - B QUESTIONS
(FOR THIRD SEMESTER ECE)
4.2
EC6303 SIGNALS AND SYSTEMS L T P C 3 1 0 4OBJECTIVES:
∑ To understand the basic properties of signal & systems and the various methods of classification
∑ To learn Laplace Transform &Fourier transform and their properties ∑ To know Z transform & DTFT and their properties ∑ To characterize LTI systems in the Time domain and various Transform domains
UNIT I CLASSIFICATION OF SIGNALS AND SYSTEMS 9Continuous time signals (CT signals) - Discrete time signals (DT signals) - Step,
Ramp, Pulse, Impulse, Sinusoidal, Exponential, Classification of CT and DT signals -Periodic & Aperiodic signals, Deterministic & Random signals, Energy & Power signals -CT systems and DT systems- Classification of systems Static & Dynamic, Linear & Nonlinear, Time-variant & Time-invariant, Causal & Noncausal, Stable & Unstable.
UNIT II ANALYSIS OF CONTINUOUS TIME SIGNALS 9 Fourier series analysis-spectrum of Continuous Time (CT) signals- Fourier and
Laplace Transforms in CT Signal Analysis - Properties.
UNIT III LINEAR TIME INVARIANT- CONTINUOUS TIME SYSTEMS 9 Differential Equation-Block diagram representation-impulse response, convolution
integrals-Fourier and Laplace transforms in Analysis of CT systems.
UNIT IV ANALYSIS OF DISCRETE TIME SIGNALS 9Baseband Sampling - DTFT Properties of DTFT - Z Transform Properties of Z
Transform.
UNIT V LINEAR TIME INVARIANT-DISCRETE TIME SYSTEMS 9Difference Equations-Block diagram representation-Impulse response - Convolution
sum- Discrete Fourier and Z Transform analysis of Recursive & Non-Recursive systems
TOTAL (L: 45+T:15): 60 PERIODS
OUTCOMES: Upon the completion of the course, students will be able to: ∑ Analyze the properties of signals & systems.∑ Apply Laplace transform, Fourier transform, Z transform and DTFT in signal
analysis.∑ Analyze continuous time LTI systems using Fourier and Laplace Transforms.∑ Analyze discrete time LTI systems using Z transform and DTFT.
TEXT BOOK: 1. Allan V.Oppenheim, S.Wilsky and S.H.Nawab, Signals and Systems , Pearson, 2007. REFERENCES: 1. B. P. Lathi, Principles of Linear Systems and Signals , Second Edition, Oxford, 2009. 2. R.E.Zeimer,W.H.Tranter and R.D.Fannin, Signals & Systems - Continuous and Discrete , Pearson, 2007. 3. John Alan Stuller, An Introduction to Signals and Systems , Thomson, 2007.
4.3
4. M.J.Roberts, Signals & Systems Analysis using Transform Methods & MATLAB , Tata McGraw Hill, 2007.
FORMULASFinite summation
1.
2.
3.
4.
5.
6.
Infinite summation
7. |a|< 1
7(a). |a|<1
8. |a|<1
9. |a|<1
10. Energy of continuous time signal, E=
11. Energy of discrete time signal, E=
12. Power of continuous time signal, P=
13. Power of discrete time signal, P=
Note: Energy signal: E= finite, P=0Power signal: E= , P=finite
14. Periodic Signal:
1,1
1
1
1 11
0
|<--
--=
++
=Â |a
a
aor
a
aa
NNN
n
n
wherea
an
n
-=Â
•
= 1
a
1
4.4
CT signal x(t+T) = x(t)DT signal x(n+N) = x(n)
15. Even and Odd Signal:CT signal: Even signal x(-t) = x(t)
Odd Signal x(-t) = -x(t)DT signal: Even signal x(-n) = x(n)
Odd Signal x(-n) = -x(n)16. Even and Odd Component:
DT System 18. Condition for Causality of signal: CT signal: x(t)=0, t<0 i.e.,t= negative values
DT signal: x(n)=0, n<0 i.e.,n= negative values19. Condition for Causality of system: CT system: h(t)=0, t<0 i.e.,t= negative values
DT system: h(n)=0, n<0 i.e.,n= negative values
20. Time domain operation: 1. time reversal 2. Time shifting 3. Time scaling.
Fourier series
1. Sin =-sin
2. Sin =sin
3. Sin =cos
4. Cos =-Cos5. Cos =Cos
6. Cos =-Sin
7. tan =tan
8. tan =tan
9. Sin(n )=0, Cos(n )=(-1)
Sin ‡ Cos, Cos‡ Sin, tan ‡Cot, Sec ‡ Cosec , Cosec‡ Sec
•<Ú•
•-
dtth )(
•<•
-•=n
nh )(
4.5
10. SinC+SinD=2Sin( )Cos( )
11. SinC-SinD=2Cos( )Sin( )
12. CosC+CosD=2Cos( )Cos( )
13. CosC-CosD=2Sin( )Sin( )
14. SinACosB=
15. SinASinB=
16. CosACosB=
17. CosASinB=
18. Trignometric series:
a0=
an=
bn=
x(t)= a0 +
19. Cosine representation:
A0=a0=
an=
bn=
An=
Or
4.6
x(t)= A0+
An --> amplitude coefficient of FS.‡ Phase coefficient of FS.
20. Exponential FS:
C0=
Cn=
X(t)=
21. Existance of Fourier series:The condition under which periodic signal can be represented by Fourier series are Dirichlet conditiona. The function x(t) have only finite number of maxima and minima.b. The function x(t) have a finite number of discontinuities.c. The function x(t) is absolutely integrable over one period
Point of discontinuity: x(td) =
Fourier Transform1. F[1]
2. F[e ]
3. F[e ]
4. F[sgn(t)]
5. F[u(t)]
6. F[
7. F[
8. F[x(t-t0)] e X(j
9. F[x(t)e ] X(j( ))
10. F[ ] (j X(j )
4.7
11. F[tx(t)] j
12. F[e u(t)]
13. F[e u(-t)]
14. F[e u(-t)]
15. F[e ]=
16. F[e ] e
17. F[e ] e
18. F[ 1Laplace Transform
1. X(S) = (bilateral non-causal system)
2. X(S) = (unilateral causal system)
3. L[e u(t)] ROC: s>-a
4. L[e u(-t)] ROC: s<-a
5. L[ 1
6. L(u(t)]=
7. L[r(t)]=
8. L[cos( )]=
9. L[sin( )]=
10. L[Cosh(at)]=
11. L[sinh(at)]=
Z-Transform1. [ 1 All Z plane
4.8
2. [ Z ,
3. u(n) or
4. Z(-u(-n-1)] or
5. nu(n) or
6. a u(n) or
7. (-a u(-n-1)] or
8. (na u(n)]
9. (-na u(-n-1)]
10. [e ] or
11. a u(n-m) z -m( )
12. (n+1)anu(n)
13. a u(n-1)
14. na u(n)
UNIT-I CLASSIFICATION OF SIGNALS AND SYSTEMSPART-A
1. Define Signal. (R)A signal is defined as physical Quantity that varies with time, space or any
other independent variables which contain some information.Eg: Radio signal, TV signal, Telephone signal etc.
2. Give some examples of CT and DT signals. (R)CT example : AC waveform, ECG,Temperature recorded over an interval of
time etc.DT example : Amount deposited in a bank per month.
3. Define deterministic and random signals. (R)A deterministic signal is one which can be completely represented by
Mathematical equation at any time .In a deterministic signal there is no uncertainty with respect to its value at any time.
Eg : x(t)= coswtA random signal is one which cannot be represented by any mathematical
equation.
4.9
Eg: Noise generated in electronic components, transmission channels, cables etc.
4. Define periodic and Aperiodic signals. (R)A signal is said to be periodic signal if it repeated itself every fundamental
period. Aperiodic signals do not repeat at regular intervals.A CT signal which satisfies the equation x(t)=x(t+T) is said to be periodic
and a DT signal which satisfies the equation x(n)=x(n+N)is said to be periodic
5. Compare Energy and Power signals. (AZ)
S.No Power signal Energy signal
1The normalized averagepower is finite and non-zero
Total normalized energy isfinite and non- zero.
2periodic signalsare power signals
Aperiodic signalsare energy signals.
6. Define step function and delta function. (May/June 09) (R)CT unit step function, u(t) = 1 , for t 0
0 , for t<0DT unit step function, u[n] = 1 , for n 0
0 , for n<0CT delta function, (t)=1 , for t=0
= 0, for tπ 0DT delta function, [n] =1 , for n=0
= 0, for nπ 0
7. Show that the complex exponential signal x(t)= e is periodic and that
fundamental period is . (May/June 09) (A)
A Continuous time signal x(t) is said to be periodic with period T if there is a positive nonzero value of T for which x(t+T)=x(t) for all t. Therefore given x(t) will be periodic if
e = eProof:
e = e e
we know e =1
If T=m2 (Or) T=m , where m= positive integer.
then e =1
e = e
4.10
Thus the complex exponential signal x(t)= e is periodic with fundamental period
is
8. Find average power of the signal u[n]-u[n-N]. (A)
P=
=
= =
9. What is the total energy of the discrete time signal x[n] which takes the value of unity at n=-1,0,1. (Nov/Dec 03) (A)Energy of the signal is given by
E= =
= |x[-1]| + |x[0]| +|x[1]|= 1+1+1 =3
10. Classify the following signals as,a. Periodic or non periodic andb. Energy or power signal
i) e , >1
ii) e (Nov/Dec 04) (AZ)i) Periodicity
i)e is Aperiodic since it is real exponential signal.
ii) e is periodic signal since it is Complex exponential signal with w=2pf.
ii) Energy or power
i) E= =
This signal is neither energy nor power.
ii) e is power signal.
P=T = T
= T = 1
Power is finite, therefore power signal.
4.11
11. Find the Fundamental period of the signal x[n]= (Nov/Dec 04) (A)
N= m = m = 2/3 (rational number, so periodic)
Fundamental period of the signal x[n]=2/3 sec
12. Is diode linear device? Give your reason. (Nov/Dec 04) (U)Diode is non linear device since it operates only when forward biased. For
negative bias, diode does not conduct.
13. Find the even part and odd part of x(t)= e (Nov/Dec 08) (A)Let x(t)= cost +j sin t
x(-t)= cos(-t) +j sin(-t)=cos t j sin t
xe(t)= 1/2x(t)+x(-t)=1/2 cos t +j sin t+ cos t j sin t=cos tx0(t)= 1/2x(t)-x(-t)=1/2 cos t +j sin t- cos t +j sin t=j sin t
14. Is the system y(t)=y(t-1)+2ty(t-2) time invariant? (Nov/Dec 02) (AZ)Response for delayed input, y(t,t0)= y(t-1-t0)+2ty(t-2-t0)Delayed response, y(t-t0)= y(t-t0-1)+2(t-t0)y(t-t0-2)
y(t,t0) π y(t-t0), This is time variant system.
15. Check whether the system having input- output relation y(t)= is
linear Time invariant or not. (April/May 04) (U)This is an integration of input. Integration is always independent of time shift.
Hence this is time invariant system.16. Check whether the system is dynamic or not. Y[n]=x[n]+nx[n+1] (U)
The output depends on the present input and future input. Hence the system is dynamic.
17. State condition for causal system and non-causal system.(April/May 08) (R)
Causal system: A causal system is one for which the output at any time t depends on the present and past inputs but not future inputs. These systems are also known as non-anticipative systemsNon-causal system: A non-causal system is one whose output depends on future values.
18. Determine whether the signal is periodic or not.(April/May 08)(A)
N takes smallest positive integer value when m=1, N=20 and sequence is periodic.19. Is the signal periodic (Nov/Dec 08) (A)
4.12
(
N=2For any value of m, N is not an integer.
It is aperiodic sequence.20. Define linear time invariant system. (April/May 10) (R)
The time shift in input signal results in an identical time shift in output signal.For CT ‡ x(t-t0) = y(t-t0) and For DT ‡ x(n-n0) = y(n-n0)
21. When is a system said to be memoryless ? Give an example.(April/May 10) (R)A system is said to be memeoryless or static if its output for each value of
independent variable at a given time is dependent only on the input at that same time (depends only on present value) Example: Resistor is a memoryless system with the input x(t) taken as current and output y(t) taken as voltage y(t)=Rx(t).
PART B1. Check for linearity, time invariance, causality and stability.
3. Compare energy signal and power signal. (Nov/Dec 10) (AZ)
4. Determine whether x(t)= rect (t/10)cos t is energy signal or power signal.
(Nov/Dec 10) (AZ)
5. Derive the relationship between unit step and delta function. (Nov/Dec 10) (U)
6. Distinguish between the following:
i. Continious time signal and discrete time signal.
ii. Unit bstep and unit ramp functions.
iii. Periodic and aperiodic signal.
iv. Deterministic and random signals. (April/May 10) (U)
7. Find whether the following signals are periodic or not
i. x(t)=2cos(10t+1)-sin(4t-1)
ii. x(t)=3cos4t+2sint (April/May 10) (A)
8. Find the summation (April/May 10) (E)
9. Explain the properties of unit impulse function. (April/May 10) (U)
10. Find the fundamental period T of the continuous time signal
4.13
X(t)=20 cos( ) (April/May 10) (A)
11. Check the following for linearity , time invariance, causality and stability for
(1) y(n)=x(n)+n x(n+1)
(2) y(n)=log[x(n)]
(3)y(n)= (April/May 11) (AZ)
12. Check whether the following are periodic:
1. x(n)=sin
2. x(n)=e (April/May 11) (A)
13. Describe the basic properties of systems with examples. (April/May 11) (U)
14. Sketch the following signal (April/May 11) (E)
i. x(t)=r(t)
ii. x(t)=r(-t+2)
iii. x(t)= -2r(t) where r(t) is a ramp signal.
15. A discrete time system is given as y(n)=y2(n-1)=x(n). A bounded input of
x(n)=2 (n) is applied to the system. Assume that the system is initially relaxed.
Check whether system is stable or unstable. (May/June 12) (AZ)
16. Determine the value of power and energy for each of the signals
(1) x1(n)= , (2) x2= (April/May 08) (A)
17. Let x(t)= be a periodic signal with fundamental
period T=2 and fourier coefficients ak.
i. determine the value of a0.
ii. determine the fourier series representation of .
iii. use the result of part(ii) and the differentiation property of continuous time
fourier series to help determine the fourier series coefficients of x(t).
(April/May 08) (E)
18. Check whether the system is linear, time invariant, causal, memory less and stable
y(t)=x(t-2)+x(2-t) and y(t)= (April/May 08) (AZ)
4.14
19. Determine the energy and power of the following signals:
(1) x(t)=t.u(t)
(2) x(n)=2 (Nov/Dec 08) (A)
20. Determine whether the signal is periodic or not
(1) x(t)=sin2(t)
(2) x(n)=cos(1/4)n (Nov/Dec 08) (A)
21. Evaluate the integral (1) (Nov/Dec 08) (E)
22. Write the mathematical equation and explain the different classification of CT and
DT signals. (April/May 10) (R)
23. Determine energy and power of the signals
(1) x(n)=
(2) x(t)=5cos( t)+sin5 t , (April/May 10) (A)
24. A discrete time signal is given by x(n)=
Find y(n)=x(2n+3) (April/May 10) (A)
25. Explain all classification of DT signals with examples for each category.
(Nov/Dec 11) (U)
26. Find out whether the following systems are
i. Linear or non-linear
ii. Causal or non- Causal
iii. Fixed or time-varient
iv. Dynamic or instantantaneous.
(1) y(n)=x(n)+
(2) (Nov/Dec 11) (A)
27. Describe through examples, the classification of continuous time signals.
(April/May 10) (U)
PART - C
1. Sketch the following signalsx(t)= [u(t-2)+u(t-4)]
4.15
x(t)= (t -4) [ u(t -2)-u(t -4)] (April / May 15) (AZ)2. (i) . Check if x(t) = 4cos( 3πt + ) + 2 cos( 4πt) is periodic.
(ii) . For the system y(n) = log [x(n)], check for linearity, causality, timeinvariance and stability (April/May 20 15) (AZ)
3. Find whether the following signals are periodic or aperiodic . If periodicfind the
fundamental period and fundamental frequency
X1(n)=sin( 2πt)+ cos(πt)
X2(n)=sin( )cos( ) (May /June 16) (A)
4. Find whether the following signals are power or energy signals. Determine power
and energy of the signals (May /June 16) (A)
G(t)=5 cos(17 πt + )+2sin(19 πt + )
G(n)=(0.5)n u(n)
5. Find whether the following systems are time variant or fixed. Also find whether the
systems are linear or nonlinear (May /June 16) (A)
y(n)= a n2x(n)+b nx(n-2).
6. Determine whether the system is linear. Time variant, Causal and memory less
y(t)= (Nov /Dec 16) (AZ)
7. Sketch the following signals. (Nov /Dec 16) (AZ)
(i)u(-t+2)
(ii)r(-t+3)
(iii)2δ[n+2]+δ[n]-2δ[n-1]+3δ[n-3]
(iv) u[n+2] u[-n+3]
Where u(t), r(t), δ[n],u[n] represent continuous time unit step, continuous time
ramp, discrete time impulse and discrete time step functions respectively.
UNIT-II ANALYSIS OF CT SIGNAL
PART - A
1. Find the inverse Fourier transform of X( )=2 ( ) (A)We know, F [ ( )]=2p
4.16
F [2 ( )]=1
2. Write the Fourier transform pair of x(t). (Nov/Dec 03) (R)x(t) X( )
X( )=
x(t)=
3. What are the differences between Fourier series and Fourier Transform?(Nov/Dec 04) (U)
S.No Fourier Series Fourier Transform
1Fourier Series is calculated for periodic signals.
Fourier Transform is calculated for non periodic as well as periodic signals.
2 Expand the signal in time domain. Represents the signal in frequency domain.
3Three types of Fourier series such as trigonometric, polar and complex exponential.
Fourier transform has no such types.
4. A signal x(t)=cos2p ft is passed through a device whose input-output is related by y(t)=x2(t). What are the frequency components in the output? (Nov/Dec 04)
(AZ)y(t)=x2(t)
=( cos2p ft)2
= =1/2 + 1/2cos2
Thus the frequency present in the output is 2f .
5. Define Parsevel s relation for continuous time periodic signals. ( Nov/Dec 06) (R)It states that the total average power of the periodic signal x(t), is equal to
the sum of the average powers of its phasor components. i.e., P= .
6. Find the Laplace Transform for the signal x(t)= - te u(t) ( Nov/Dec 06) (A)
We know that L[e u(t)] =
By differentiation with time property, L[t e u(t)] =
L[-t e u(t)] = , Re(s)>-2.
7. Find the S-domain transfer function, if the poles are located at P1= -1+j , P2=-1-j and a zero at s=0.5. (May/June 07) (A)
H(S)=
4.17
=
=
8. Write the condition to be satisfied for the existence of Fourier Transform of aperiodic energy signal. (May/June 08) (R)
Fourier transform does not exist for all aperiodic functions. The conditions for x(t) to have Fourier Transform are
i. x(t) is absolutely integrable over (- , ), that is
ii. x(t) has finite number of discontinuities and a finite number of maxima and minima in every finite time interval.
9. List out the four properties of Laplace transform used in signal analysis.(May/June 08) (R)
Time shifting, x(t-t0) e X(s)
Time reversal, x(-t) X(-s)
Frequency shifting, x(t)e X(s+a)
Differentiation in S-domain, (-t)nx(t) .
10. List the Dirichlet conditions. (April/May 08) (R)i. The function x(t) should be within the interval T0.
ii. The function x(t) should have finite number of maxima and minima in the interval T0.
iii. The function x(t) should have at the most finite number of discontinuities in the interval T0.
iv. The function should be absolutely integrable.
i.e., <
11. Find Laplace transform and ROC of x(t)= t e u(t). (April/May 08) (A)
L[t e u(t)] = ; ROC : Re(s)>-a
13. What is the Laplace Transform of x(t)= e sin t u(t). (Nov/Dec 04) (A)
L[e sin t u(t).]=
14. Find Fourier Transform of eat u(-t). (May/June 09) (A)
We know FT[e u(t)]=
By the property of Time reversal, x(-t)=X(-j )
4.18
i.e., replace, t = -t and j = -j
FT[e u(-t)]=
15. State Rayleigh s energy theorem. (R)Rayleigh s energy theorem states that the energy of the signal may be written
in frequency domain as superposition of energies due to individual spectral frequencies of the signal.
16. What are the methods for evaluating inverse Laplace transform. (R)The two methods for evaluating inverse laplace transform are
1. By Partial fraction expansion method.2. By convolution integral.
17. Find the LT for signal x(t)=u(t-2) (April/may 11) (A)
Time shifting property :LT x(t-t0)=X(S)=u(t) and t0=2
18. Find FT of eatu(-t) (April/May 11) (A)
x(t)=eatu(-t) is time reversal of signal e-atu(t)Time reversal property of FT[x(-t)]=
19. Define Laplace Transform (April/May 11) (R)The Laplace transform of a signal x(t) is defined as
, where s is complex frequency denoted by s= .
20. Determine the FT of signal x(t)=e-atu(t) (April/May 10) (A)
4.19
.
22. Find LT of unit ramp function (Nov/Dec 08) (A)x(t)=r(t)=t, for t 0
=(t )
=0-(0- )
= .
23. State initial value theorem and final value theorem of Laplace Transform. (U)(April/May 11)
Initial Value Theorem: The Initial Value allows to calculate x(0) directly from transform X(S) without the need for finding inverse transform of X(S).
x(t)= SX(S)
Final value theorem: The Final value of x(t) as t tends to infinity may also be found directly from Laplace Transform X(S).
x(t)= SX(S)24. What is the Fourier transform of x(t)=1 (April/May 11) (U)
F-1[ ]=
F-1[ ]=
F[1]=
PART B
1. Obtain the Fourier transform of rectangular pulse of duration T and amplitude A.
(8 mark, Nov/Dec 10) (A)
2. Find out the inverse laplace transform of F(S)= . (8 mark, Nov/Dec 10)
(A)
3. Find the exponential Fourier series of a impulse train. Plot its magnitude and phase
4.20
Spectrum. (12 mark, Nov/Dec 10) (AZ)
4. What are the two types of Fourier series representation? Give the relevant
4. Find the Inverse Laplace transform of X(s) = (April/May 2015) (A)
5. Obtain the Fourier series coefficient and plot the spectrum for the given waveform
(May/June 2016) (A)6. From basic formula, determine the Fourier transform of the given signals. Obtain the
magnitude and phase spectra of the given signals.x(t) = te-at u(t) a>0x(t) = e-a|t| a>0 (May/June 2016) (A)
7. State and prove Rayleigh s energy Theorem. (May/June2016) (U)8. Find the Fourier transform of the signal x(t) = cosΩ0t u(t) (Nov/Dec2016) (A)9. State and Prove the multiplication and convolution property of Fourier transform.
(Nov/Dec2016) (A)
UNIT - III LINEAR TIME INVARIENT-CONTINUOUS TIME SYSTEMSPART - A
1. Give four steps to compute convolution integral. (Oct/Nov 02) (R)1. Folding : One of the signal is first folded at t=0.2. Shifting:The folded signal is shifted right or left depending upon time at
which output is to be calculated.3. Multiplication: The shifted signal is multiplied to other signal.4. Integration: The multiplied signals are integrated ti get the convolution
output.2. State the properties of convolution. (May/June 09)(R)
3. What is the relationship between input and output of an LTI system? (R)
y(t)=
i.e., it is equal to convolution.
4. What is the output of a system whose impulse response h(t)=e-at for a delta input? (Nov/Dec 05) (A)
Given x(t)= (t)
We know y(t) =
According to the property of convolution with impulse response is equal to the signal itself. i.e, x(t)* (t)=x(t)
y(t) =x(t)*h(t)= (t)* e at
= e at
5. What is the overall impulse response of h1(t) and h2(t) when they are in (a) series (b)parallel. (Nov/Dec 05) (U)List out different ways of inter connecting any two system (April/May 11)System connected in series:
Overall impulse response of the system : h(t)= h1(t)*h2(t)System connected in parallel:
Overall impulse response of the system : h(t)= h1(t)+h2(t)
6. How Laplace transform analysis will help in the analysis of continuous time LTI systems? (May/June 06) (U)
Laplace transform can analysis both stable and unstable system.
7. Find the Fourier Transform of the impulse response. (May/June 06) (A)
X(j )=
=
=
=e0=1
8. Find the Laplace transform of the signal u(t). (May/June 06) (A)
h2(t)h1(t) y(t)
h1(t)
h2(t)
y(t)
4.23
X(s)=
=
We know u(t)=1, for t 0=0, for t<0
X(s)=
=[e-st/(-s)]
=0-(-1/s)=1/s
9. Find the impulse response h(t) for the system described by the difference
equation +5y(t) = x(t)+2 (AZ)
sy(s)+5y(s) = X(s)+2Sx(s)Y(s)(s+5) = 2X(s)(s+1/2)
H(S)=Y(s)/X(s) =
By partial fraction H(s) = =
A = (s+5) |S= - 5 = - 4/9
B = (s+1/2) |S= - 1/2 = 4/9
H(s) =
Take inverse LT we get h(t) = - 4/9 e 5t+4/9 e - (½)t
10. Define natural response (R)Natural response is the response of the system with zero input. It depends on
the initial state of the system. It is denoted by yn (t).11. Define forced response and complete response. (R)
The Forced response is the response of the system due to input alone when the initial state of the system is zero. It is denoted by yf (t).
The complete response of a LTI-CT system is obtained by adding the natural response and forced response . y(t)= yn(t)+ yf (t).
12. Find the initial and final value, given that X(s)= (May/June 07) (A)
Initial Value theorem : x(0) = s [sX(s)]
x(0)= s [s ]
= s [ ] = 1
4.24
Final value theorem : x( ) = s 0 [sX(s)]
= s 0 [s ]
=013. Draw the direct form-II realization of the system described by the differential
equation (April/May 05) (U)
From the equation a1=5, a0=4 and b1=1
14. Define Eigen function and Eigen value. (R)In the equation given below,
y(t)=H(s)e st
H(s) is called Eigen value and e st is called Eigen function.15. Define Causality and stability using poles. (R)
For a system to be stable and causal, all the poles must be located in the left half of the s plane.
16. What are the different forms of realization (April/May 11) (R)1. Direct form I realization2. Direct form II realization3. Cascade form realization4. Parallel form.
17. What is the condition for a system to be causal? (April/May 11) (U)An LTI continuous system is causal if and only if its impulse response
is zero for negative values of t. h(t)=0, for t<0.
18. State and write convolution integral formula. (Nov/Dec 08) (R)The output of system can be obtained using convolution integral if the
input to the system x(t0 and impulse response of system h(t) are known.The convolution integral is given by
y(t)=x(t)*h(t)
= .
19. Given differential equation .Find the frequency response
of system. (Nov/Dec 08) (U)
+
+-a1=-5
-a2= - 4
b1=1
x(t) y(t)
4.25
Frequency response:
PART- B1. Solve the differential equation
with y(0-)=1 and and x(t)=u(t).Find
the system transfer function, frequency response and impulse response.(Nov/Dec 10)
(AZ)
2. The system is described by input output relation
, Find the system transfer function,
frequency response and impulse response. (Nov/Dec 10) (AZ)
3. Draw the direct form I and II implementation of system described by
(Nov/Dec 10) (AZ)
5. Explain the steps to compute the convolution integral. ( April/May 10) (A)
6. Find the convolution of the following signal. (April/May 10) (A)
x(t)=e-2tu(t) and h(t)=u(t+2)
7. Using Laplace transform, find the impulse response of an LTI system described by the
differential equation (April/May 10) (A)
8. Explain the properties of convolution integral. (April/May 10) (U)
9. Realize the following in direct form II (April/May 11) (AZ)
10. Obtain the convolution of the signals x1(t)=e-atu(t), x2(t)=e-btu(t) using Fourier Transform.
(April/May 11) (A)
11. The input and output of a causal CTI system are related by the differential equation
.Find impulse response of the system.
(April/May 11) (AZ)
12. Compute and plot the convolution y(t) of the given signals
i. x(t)=u(t-3)-u(t-5), h(t)=e-3tu(t)
4.26
ii. x(t)=u(t), h(t)=e-tu(t) (May/June 12 &April/May 11) (A)
13. The LTI system is characterized by impulse response function given by
H(S)= , ROC: Re> -10.Determine the output of a system when it is
excited by the input x(t)= -2e-2tu(-t)-3e-3tu(t). (May/June 12) (AZ)
14. Using Laplace transform, find the output response of the system described by the
15. Find the convolution of h(t) and x(t) using graphical method.(Nov/Dec 12) (A)
h(t)=t, 0<t<T
x(t)=u(t), 0<t<T
16. Consider a CT-LTI system find the system function
and determine if the impulse response h(t) for the system is causal, the system is stable
and the system is neither causal nor stable. (Nov/Dec 08& April/May 11) (AZ)
17. Determine the voltage y(t) in the circuit shown in figure for an applied voltage x(t)=3e-
10t u(t). the voltage across the capacitor at time t=0 is 5V. April/May 10) (AZ)
18. Solve the following differential equation using laplace transform
(April/May 11)
(AZ)
19. Find the impulse and step response of the following system H(S)=
(April/May 11) (AZ)
20. Consider the system shown in figure with RC=10. Find frequency response of the
output across the capacitor and sketch |H(ω)|as a function ω. (April/May 08) (AZ)
21. Find the transfer function and impulse response of the system
. (April/May 08) (A)
22. Given x(t)=e-at u(t) and h(t)=u(t-1) convolve and find the response y(t). (Nov/Dec 08)
(A)
4.27
23. Given x(t)=e-2t u(t) and h(t)=e-3t u(t) using the properties of continuous time fourier
transform find the response y(t). (Nov/Dec 08) (A)
24. Define convolution integral and derive its equation. (Nov/Dec 13) (U)
25. A stable LTI system is characterized by the differential equation
,find the frequency response and impulse
response using Fourier transform. (Nov/Dec 13) (A)
26. Draw direct form, cascade and parallel form of a system with system function
H(S)= (Nov/Dec 13) (AZ)
1. Solve the differential equation (D2+3D+2)y(t)=Dx(t)using the input x(t)=10e-3t and with initial conditions are y(0+)=2 and y1(0+)=3 (APRIL-MAY 2015) (A)
2. Draw the block diagram representation for H(s) = (APRIL-MAY 2015) (AZ)
3. For a LTI system with H(s) = find the differential equation. Find the system
output y(t) to the output x(t)= e-2t u(t) (APRIL-MAY 2015) (AZ)
4. Using graphical method convolve x(t)= e-2t u(t) with h(t)= u(t+2). (APRIL-MAY 2015)(A)
PART - C
1. Using graphical convolution, find the response of the system whose impulse response
is h(t)= e-2t u(t) for an input x(t)= (MAY-JUNE 2016)
(A)
2. Realize the following is indirect form II
(MAY-JUNE 2016) (AZ)
3. An LTI system is defined by the differential equation
with y(0-)=1 and and
x(t)=u(t).Find the system response y(t). (MAY-JUNE 2016) (AZ)
4.28
4. Determine the frequency response and impulse response for the system described by
the following differential equation. Assume zero initial conditions.
(MAY-JUNE2016) (AZ)
5.Convolute the following signals
x(t)= e-3t u(t)
h(t)= u(t+3). (NOV-DEC 2016) (A)
6. A system is described by the differential equation
.
Find the transfer function and output signal y(t)for x(t)=δ(t) (NOV-DEC 2016)
(AZ)
UNIT IV ANALYSIS OF DISCRETE TIME SYSTEMS PART - A
1. Obtain Z- transform of x[n]=1,2,3,4 (Nov/Dec 05) (A)The signal is given in sequence.
We know by power series X(z)= ..x(-2),x(-1),x(0),x(1),x(2) ..
X(z) = z n = z n
=x(0)+x(1)z -1+x(2)z -2 +x(3)z -3
=1+2z -1+3z -2+4z -3
2. State sampling theorem. (Nov/Dec 07) (R)A band limited signal x(t) with X(j )=0 for | |> is uniquely determined
determined from its samples x(nT), if the sampling frequency fs 2fm , i.e., sampling frequency must be at least twice the highest frequency 2fm ,which under sampling theorm must be atleast twice the highest frequency present in the signal.
3. Write the properties of Region of convergence of the z-transform. (Nov/Dec 07) (R)
i. The ROC is a ring or disk in the z-plane centered at the origin.ii. The ROC cannot contain any poles.iii. If x[n] is a causal sequence the ROC is the entire z-plane except at z=0iv. The ROC of an LTI stable system contains the unit circle.
4. State and prove time shifting property of DTFT. (Nov/Dec 07) (U)Time shifting
6. List any two properties of Z-transform. ( May/June 07) (U)1. Linearity: ax1[n]+bx2[n] aX1[n]+bX2[n]2. Time shifting: x[n-k] Z kX[z]
7. Define Parsevels relation for discrete time periodic signals. (May/June 06) (R)The Parsevel s relation for discrete time periodic signals is given by
8. Define Zero padding. (R)The method of appending zero in the given sequence is called as Zero padding.
9. State the convolution property of Z transforms. (R)The convolution property states that the convolution of two sequences in time
domain is equivalent to multiplication of their Z transforms.10. Obtain the inverse z transform of X(z)=1/z-a,|z|>|a| (A)
Given X(z)=
By time shifting property, X(n)=an. u(n-1)11. List the methods of obtaining inverse Z transform. (R)
Inverse z transform can be obtained by using1. Partial fraction expansion.2. Contour integration3. Power series expansion4. Convolution.
12. Find the z- transform for x[n]= u[n-1]. (May/June 07) (A)
We know ZT[ u[n]]= ROC: |z|>|a|
Using time shifting property of z-trnsform we haveZTx[n-k]=
Then ZT u[n-1] = = ROC : |z|>|a|
13. State the condition for existence of DTFT? (R)
4.30
The conditions are
If x(n)is absolutely summable then
If x(n) is not absolutely summable then it should have finite energy for DTFT to exit.
14. Write any two properties of Z-transform (April/May 08) (R)Time shifting property:
If X(Z)=ZTx(n) with the initial condition for x(n) are zero, then ZTx(n-m)= ,where m is a positive or negative integer.Scaling property:
If X(Z)=ZTx(n) , ROC:r1< <r2
then ZTa x(n)=X(a Z), ROC: r1< < r2
15. What is the Z- transform and associated ROC of the signal x(n)=u(n-n0)?(Nov/Dec 08) (A)
By time shifting property ZTx(n-m)=
ZTu(n-n0)=
16. Define aliasing effect. (April/May 10) (R)The super imposition of high frequency component on the low frequency is
known as frequency aliasing. Because of aliasing the spectrum X(j ) is no longer recoverable from spectrum of XS(j ).
To avoid aliasing the sampling frequency must be greater than twice the highest frequency present in the signal.
17. Define one sided Z-transform. (April/May 10) (R)One sided Z-transform:Right hand sequence is one for which x(n)=0 for all
n<n0, where n0 is positive or negative but finite. If n0 is greater than or equal to zero,resulting sequence is causal or positive time sequence. For such type of sequence the ROC is entire Z-plane except at Z=0.
Left hand sequence is one for which x(n)=0 for all n n0, where n0 is positive or negative but finite. If n0 0, the resulting sequence is anticausal sequence. For such type of sequence the ROC is entire Z-plane except at Z=
18. Find DTFT OF u(n) (Nov/Dec 10) (A)
X(e )=
=
=
=
19. What is the main condition to be satisfied to avoid aliasing? (Nov/Dec 10) (U)To avoid aliasing the sampling frequency must be greater than twice the
highest frequency present in the signal.
4.31
If fs= then
.
20. If X(e ) is the FT of x(n), Find the FT of x*(-n) in terms of X(e ). (Nov/Dec 08) (A)
By time reversal property:x(-n) X(e )
and by conjugate property:
x (-n) X (e )
21. What is the relationship between Z-Transform and DTFT? (Nov/Dec 08) (U)The Z-Transform of sequence x(n) is given by
X(Z)=ZTx(n)
= ----(1)
Where Z=r e ----(2)Sub (2) in (1) we get
X(re )= ----(3)
The Fourier Transform of x(n) is given by
X(e )= ----(4)
Equation (3) and (4) are identical when r=1.In this Z-plane this corresponds to the locus of points on the unit circle .Hence H(e ) is equal to H(Z) evaluated
along the unit circle.
X(e )=
PART B
1. State and prove the property of Z-transform. (Nov/Dec 10) (U)
2. Determine the Z-transform of
i. x(n)=
ii. nu(n) , for n 0. (Nov/Dec 10) (A)
3. State and prove sampling theorem. (Nov/Dec 10) (U)
4. Find the inverse Z transform of the following: (Nov/Dec 10) (A)
4.32
i. X(Z)=
ii. X(Z)=
5. Find the Fourier transform of x(n)=A,
=0, (April/May 10)(A)
6. Explain any four properties of DTFT. (April/May 10)(U)
7. Find Z-transform of the given signal x(n) and find ROC.
x(n)=[sin ]u(n) (April/May 10)(A)
8. Describe the sampling operation and explain how aliasing error can be prevented.
(April/May 10) (U)
9. What is aliasing? Explain with an example. (April/May 11) (R)
10. State and prove the following properties of DTFT: (April/May 11) (U)
∑ Convolution property
∑ Time shifting
∑ Time reversal
∑ Frequency shifting.
11. Obtain inverse Z transform of X(Z)= for ROC:
¸
¸
¸ (April/May 11) (A)
12. Determine the Z-transform and sketch the pole zero plot with the ROC for each of the
following signals. (May/June 12) (A)
1. x(n)=(0.5)nu(n)-(1/3)nu(n)
2. X(n)=(1/2)nu(n)+(1/3)nu(n-1).
13. Find inverse Z-transform of the (May/June 12) (A)
14. Express the Fourier transforms of the following signals in terms of X(ej )
1. x1(n)=x(1-n)
4.33
2. x2(n)=(n-1)2x(n). (May/June 12) (A)
15. Prove sampling theorem and explain how the original signal can be reconstructed
from the sampled version. (Nov/Dec 11) (AZ)
16. Find DTFT for signal x(n)=u(n-2). (Nov/Dec 11) (A)
17. Determine the Z transform for the sequence x(n)=4ncos u(-n-1).sketch the
pole-zero plot and indicate the ROC. (April/May 08) (A)
18. Find inverse Z transform of X(Z)= ,|z|>0 (April/May 08) (A)
19. Suppose that the algebraic expression for the Z transform of x(n) is
How many different regions of convergence
could correspond to X(Z)? (April/May 08) (AZ)
20. Find the Nyquist s frequency and Nyquist s rate for each of the following signals:
1. x(t)=25 cos(500πt)
2. x(t)=15sect(t/2) (Nov/Dec 08) (A)
21. Find inverse Z transform of X(Z)= (Nov/Dec 08) (A)
22. Determine the initial and final values for the signal x(n) with the transfer function
x(z)= (Nov/Dec 08) (A)
23. Consider an analog signal x(t)=10 cos 100πt
i. determine the minimum sampling rate to avoid aliasing
ii. If sampling rate FS=200Hz, what is the DT signal after sampling?
iii. find the DT signal given is sampled at 75 Hz.
iv. What is the frequency 0<F<FS/2 of a sinusoidal that yields samples
identical to those obtained in part iii. (April/May 10) (AZ)
24. Determine the Z transform, the ROC and the location of poles and zeros of X(Z) the
signal x(n)= (April/May 10) (A)
4.34
25. Find the inverse Z Transform of X(Z)= with ROC |z|>1/2 using a
power series expansion. (April/May 10) (A)
26. Explain the reconstruction of the original signal from the sampled signal.
(April/May 11) (U)
27. Find the discrete time signal of X(e-jw)= (April/May 08)
(A)
28. Determine the Z transform and the ROC for the following sequence (April/May 08)
i. x(n)=(-3)nu(-n-1)
ii. x(n)=n(1/2)n+(n-1)(1/3)n (A)
29. State and prove parsevel s relation for discrete aperiodic signals.(Nov/Dec 08) (U)
PART - C
1. A continuous time sinusoid cos(2πft+θ) is sampled at a rate fs = 1000 Hz. Determine the resulting signal samples if the input signal frequency f is 400Hz, 600Hz and 1000Hz respectively. (April/May 2015) (Az)
2. Prove the following DTFT properties
(i) nx(n) => j
(ii) x(n) ejΩcn => X(Ω Ωc) (April/May 2015) (A)
3. Find the DTFT of x(n) = (1/2)n-1 u(n-1) (April/May 2015) (A)4. Using suitable transform properties find X(z) if
x(n) = (n-2)(1/3)n-2 u(n-2) (April/May 2015) (A)5. Find the Z-transform of x(n) = a|n| 0<a<1 (April/May 2015) (A)6. State and prove sampling theorem. (May/June2016) (U)7. What is Aliasing? Explain the steps to be taken to avoid aliasing. (May/June2016)(U)8. State and Prove the following theorems
(i) Convolution theorem of DTFT(ii) Initial value theorem of z-transform. (May/June2016) (U)
9. Discuss the effects of undersampling a signal using necessary diagram.(Nov/Dec2016) (U)
10. Fin the Z-transform of x(n) = an u(n) = bn u(-n-1) and specify its ROC.(Nov/Dec2016) (A)
11. State and Prove the time shifting property and time reversal property of z-transform. (Nov/Dec2016) (A)
4.35
UNIT V LINEAR TIME INVARIENT DISCRETE TIME SYSTEMSPART-A
1. Determine the transfer function of the system described by y[n]=ay[n-1]+x[n] (Nov/Dec 05) (U)
2. Find the convolution sum for x[n]=1,1,1,1 and h[n]=1,2,2,1 (May/June 06)(A)
x[n] = 1 1 1 1h[n] = 1 2 2 1
1 1 1 12 2 2 2 x
2 2 2 2 x x1 1 1 1 x x x
1 3 5 6 5 3 1
x[n]*h[n] = 1,3,5,6,5,3,13. What is the difference between the spectrums of the CT signal and the spectrum
of the corresponding sampled signal? (Nov/Dec 04) (U)i. The spectrums of CT signal and sampled signal are related as,
X ( ) =
ii. This means spectrum of sampled signal is periodic repetition of spectrum of CT signal.iii. It repeats at sampling frequency and amplitude is also multiplied by .
4. Differentiate between natural response and forced response. (May/June 07)(U)
Natural response: It is the response of the system with zero input.it depends on the initial state of the system.Forced response: It is the response of the system due to input alone when the initial state of the system is zero.
5. What is the response of an LSI system with impulse h[n]= [n]+2 [n-1] for the input x[n]=1,2,3? (April/May 05) (A)h[n]= [n]+2 [n-1] can be represented as h[n]=1,2
11. Compare FIR and IIR filter realization (U)FIR: It stands for finite impulse response and it is non-recursive type. The present output sample depends on present input samples and previous input samplesIIR: It stands for infinte impulse response.present output sample depends on present input and past input samples and output samples. It is recursive type.
12. State the condition for an DT-LTI system to be causal and Stable.(April/May 08) (U)
Causal system: A LTI system is causal if and only if, h(n) = 0 for n<0.This is the sufficient and necessary condition for causality of the system.
4.37
Stable system:The bounded input x(n) produces bounded output y(n) in the LTI system
only if, When this condition is satisfied ,the system will be stable.
13. Define non recursive and recursive systems? (April/May 08) (R)Non-recursive system: When the output y(n) of the system depends upon present and past inputs then it is called non-recursive system.Recursive system: When the output y(n) of the system depends upon present and past inputs as well as past outputs, then it is called recursive system.
14. What is the advantage of direct form II over direct form I structure? (U)The direct form II structure has reduced memory requirement compared to
direct form I structure.15. A causal DT system is BIBO stable only if its transfer function has _________.
(U)A causal DT system is stable if poles of its transfer function lie within the unit
circle.16. Determine the range of values of the parameter a for which linear time
invariant system with impulse response h(n)=an u(n) is stable? (U)
H(z)= , There is one pole at z=a. The system is stable, if all its
poles.i.e., within the unit circle. Hence |a| < 1 for stability.
17. What are the drawbacks of transfer function analysis method? (R)i. Transfer function is defined under zero initial conditions.
ii. Transfer function approach can be applied only to linear time invariant systems.
iii. It does not give any idea about the internal state of the system.iv. It cannot be applied to multiple input multiple output systems.v. It is comparatively difficult to perform transfer function analysis on
computers.
PART-B
1. The system function of the LTI system is given as .
Specify the ROC of and determine for the following condition.
Stable system and Casual system. (Nov/Dec 10) (A)
2. Obtain the direct form II structure for
. (Nov/Dec 10) (AZ)
3. A discrete time casual system has a transfer function
4.38
i) Determine the difference equation of the system.
ii) Show pole zero diagram.
iii) Find the impulse response (Nov/Dec 10) (AZ)
4. Find the impulse response of the discrete time system described by the difference
equation . (April/May 10) (AZ)
5. Discuss the block diagram representation for LTI discrete time systems.
(April/May 10) (U)
6. Obtain the cascade realization of
.
(April/May 11) (AZ)
7. Obtain the relationship between DTFT and Z transforms. (April/May 11) (U)
8.Find the impulse response of the difference equation
. (May/June 12) (A)
9.Draw the direct form II block diagram representation for the system function
. (May/June 12) (AZ)
10. Find the input which produces output when passed
through the system having . (May/June 12) (AZ)
11. Determine the system function and impulse response of the casual LTI system
defined by the difference equation ,
Using Z-transform, determine if . (Nov/Dec 11) (A)
12. Determine the transfer function and impulse response for the causal LTI
system described by the difference equation using Z transform.
(Nov/Dec 13) (A)
4.39
13. Draw the direct form I and direct form II implementation of the dsyatem
described by difference equation
(Nov/Dec 13) (AZ)
14. Given y(n)+4y(n-1)+4y(n-2)=x(n). Find the impulse response h(n).
(April/May 10) (A)
15. Find the Z transform of x(n)=(1/3)n u(n)+( 1/2)n u(-n-1) (April/May 08) (A)
17. Find Convolution sum of x(n)= (1/2)n u(n) and h(n) = δ (n) + δ (n-1) +
(1/3)nu(n) . (April/May 08) (A)
18. Find Transfer function of system y(n) = x(n) + 1/3 x(n-1) + 2x(n-2) n 0,
for x(n ) = u(n). Plot the pole - zero locations in Z Plane.(April/May 08) (AZ)19. Determine system function and impulse response of Causal LTI system
defined by differential equation:
(April/May 11) (A)20. Find the transposed direct form II realization for the system described by
difference equation y(n)=x(n)-1/3x(n-1)-3/4y(n-1)-3/4y(n-2) and write down the set of equations corresponding to this realization. (April/May 10) (A)
21. Discuss the block diagram representation for LTI DT system. (U)22. Compute Convolution of two sequences shown. Plot y(n) Vs n (A)
x(n) h(n)
2 2
1 1
23. Find overall response of the system shown with : (Nov/Dec 08) (AZ)h1(n)= δ(n) , h2(n) = (n-1)u(n) & h3(n) = δ(n) + nu(n-1) + δ(n-2)
-
+
24. Derive transfer function of FIR & IIR system. (Nov/Dec 08) (U)25. Realize the given DT system in Cascade & Parallel form: (Nov/Dec 08) (AZ)
h1(n)
h3(n)
h2(n)
4.40
26. When an input x(n) = 3δ (n-2) is applied to a causal LTI system, whose output is found to be y(n) = 2(-1/2)n + 8(1/4)n . Find the impulse response h(n) of the system. (AZ)
PART C1. Determine the impulse response and step response of y(n) + y(n-1) 2y(n-2) = x(n-
1) + 2x(n-2). (April/May 2015) (Az)2. Find the convolution sum between x(n) = 1,4,3,2 and h(n0 = 1,3,2,1.
(April/May 2015) (Az)3. A causal system has x(n) = δ(n)+ 1/4 δ(n-1) 1/8 δ(n-2) and y(n) = δ (n )- 3/4 δ(n-
1).Find the impulse response and output if x(n) = (1/2)n u(n). (April/May 2015) (Az)
4. Compare recursive and non recursive systems. (April/May 2015) (U)5. Realize the following systems in cascade form
7. A system is governed by a linear constant coefficient difference equationy(n) = 0.7 y(n-1) 0.1 y(n-2) + 2(n) x(n-2). Find the output response of the system
y(n) for an input x(n) = u(n). (May/June2016) (Az)8. Convolve the following signals
9. Determine whether the given system is stable by finding H(z) and plotting the pole-zero diagram y(n) = 2y(n-1) -0.8y(n-2) +x(n) +0.8x(n-1) (Nov/Dec2016) (A)
ADDITIONAL UNIVERSITY QUESTIONS1. Define power signal (April/May 15) (R)2. How the impulse response of a discrete system is useful in determining its stability
and causality? (April/May 15) (U)3. Find the Fourier co-efficients of the signal
(April/May 15) (A)
4. Draw the spectrum of a CT rectangular pulse (April/May 15) (U)5. Given x(t)=δ(t). Find X(s) and X(ω). (April/May 15) (A)6. State the convolution integral (April/May 15) (R)7. Determine the Nyquist sampling rate for x(t)=sin(200πt)+3sin2(120πt).
(April/May 15)(A)8. List the methods used for finding the inverse Z transform. (April/May 15) (R)9. Name the basic building blocks used in LTIDT system block diagram
4.41
(April/May 15)(U)10. Write the nth order difference equation. (April/May 15) (R)
11. Sketch the following signals : Rect ( ; 5 ramp (0.1t) (April/May 16) (U)
12. Given g(n)= 2 e-2n-3 , Write out and simplify the functions
(i)g(2-n) (ii) g ( ) (April/May 16) (A)
13. What is the inverse fourier transform of (i) e-j2πft0 (ii)δ(f-f0) (April/May 16)(A)
14. Give the laplace transform of x(t)= 3e-2t u(t)- 2e-t u(t) with ROC. (April/May 16) (A)
5.1
PANIMALAR ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS & COMMUNICATION
ENGINEERING
EC 6304 ELECTRONIC CIRCUITS - I
SOLVED TWO MARKS , PART - B, PART-C QUESTIONS
ASSIGNMENT QUESTIONS
(FOR THIRD SEMESTER ECE 2017-18)
5.2
UNIT – I BIASING OF DISCRETE BJT AND MOSFET
PART - A
1.List the applications of transistor. (R)
1. It is used as an amplifier 2. It is used as a switch 3. It is used in oscillator circuit 4. It is used as buffer
2. What is transistor biasing? (U)
In order to operate transistor in the desired region, we have to apply external d.c. voltages of correct polarity and magnitude to the two junctions of the
Transistor. This is called as Transistor biasing. 3. Why a transistor must be biased? (OR) What is the need to bias a
transistor?(M/J 2010) (R)
The transistor is biased to achieve faithful amplification and if the transistor is not biased properly, it would work inefficiently and produce distortion in the output signal. 4. Mention the reason for producing distortion in the output signal of a
transistor. (R)
Improper biasing of a transistor circuit leads to distortion in the output
Signal.
5. Most of the transistors are NPN type and not PNP type, why? (R)
In NPN transistors the current conduction is mainly due to electrons, whereas in PNP transistors the current conduction is mainly by holes. As the electrons are more mobile than holes we can have more conduction in NPN transistors. Therefore most of the transistors are NPN type. 6. What are the different methods of biasing JFET.[M/J 2012] (R)
Fixed bias Self bias Voltage divider bias
7. What are the factors against which an amplifier needs to be stabilized? [A/M 2014] (R)
The stability factor indicates the degree of change in operating point due to variation in Ico,VBE& β .
5.3
8.What is a DC Load line? (N/D 2016)(R)
The DC load line is a line drawn on the output characteristics of a transistor, which gives the values of IC and VCE corresponding to zero signal conditions (DC conditions)
9. What is a AC Load line?[A/M 2010] (R)
The AC load line is a line drawn on the output characteristics of a
transistor, which gives the values of IC and VCE when signal is applied. 10. Criticize the need to draw a DC load line on the output characteristics of a transistor?(E)
To study the effects of biasing conditions on the performance of a transistor, it is necessary to draw a DC load line on the output characteristics of the transistor 11.Explain the term Quiescent point or Operating point? (N/D2011)(U)
The selected point on the load line, which represents the values of IC and VCE when no signal is applied at the input, is known as quiescent point or Q-point. 12. What is meant by stabilization of operating point? (OR) what is biasstabilization?(R)
The process of making maintenance of operating point stable, independent of temperature variations or variations in transistor parameters is known as stabilization.
13. Analyze the necessity to stabilize the operating point of transistoramplifier?(R)
The stabilization of operating point of a transistor is necessary due to the following reasons
1. Temperature dependence of IC. 2. Individual parameter variations such as β and ICEO.
14. What are the two factors which are responsible for instability of operating point?(R)
1. Variations in the parameter values of the same type. 2.Effect of temperature on IC
5.4
15. Draw the circuit diagram of base bias with emitter feedback(R)
16. Draw the circuit diagram of self biasing for CE amplifier or voltage divider biasing (R) 17. List the advantages and disadvantages of fixed bias method. (N/D 2016)(R)
Advantages:
The advantages of fixed bias method are, 1. The biasing circuit is very simple 2. Biasing conditions can be easily set 3. There is no loading of the source by the biasing circuit, as no resistor
is used across base-emitter junction.
Disadvantages: The disadvantages of fixed bias method are, 1. This method provides poor stability 2. There are good chances of thermal runway. This is due to high
stability factor S.
5.5
18.What is thermal Runway?[A/M 2010 & A/M 2014](R)
The continuous increase in collector current due to poor biasing causes the temperature at collector terminal to increase, if no stabilization is done, the collector leakage current also increases. This further increases the temperature. This action becomes cumulative and ultimately the transistor burns out. The self destruction of an unstabilised transistor is known as thermal runway.
19.Explain whya fixed bias circuit is not commonly used?(AZ)
Rise in temperature causes increase in leakage current ICO, increase in current amplification factor β and decrease in base-emitter voltage VBE, so operating point is not stabilized. This is the reason that fixed bias circuit is not commonly used. 20. Explainwhy a FET is called as voltage controlled device?[A/M 2010](AZ)
In a FET, drain current is controlled by the effect of the extension of the field associated with the depletion region developed by the reverse bias on the gate, so it is called as voltage controlled device. 21. Summarize why it is necessary to stabilize the operating point of a
transistor?(E)
It is necessary to stabilize the operating point of a transistor because the operating point tends to shift its position due to any or all of the following three main factors.
i) Reverse saturation current, ICO, which doubles for every 10C increase in temperature ii) Base-Emitter voltage, VBE, which decreases by 2.5mV per C
iii) Transistor current gain, , which increases with temperature.
22. Define stability factor of an amplifier.(R) (A/M 2010), (N/D2011) (M/J 2012)
The stability factor (S) is defined as the rate of change of collector current (IC) with respect to the reverse saturation current (ICO) at constant IB and β.
S =dIC ( at constant IB and )
dIc0 23.State the advantages of self bias over other types of biasing [N/D 2016] (R)
Stability factor S of self bias is less compared to other biasing circuits
5.6
PART-B
1. i) What is meant by bias stability? What factors affect BJT
biasing? ii)With the help of neat diagram explain the voltage divider biasing method for BJT(R)(A/M 2014)
2. Draw the circuit diagram of self-bias circuit using CE configuration
and explain how it stabilizes operating point.(R)
3. Draw a Voltage divider bias for BJT network, derive the expressions
for ICQ and VCEQ and describe the method of drawing the dc load line on the output characteristics of transistor(M/J 2012& A/M 2014)(AZ)
4.Explain the fixed bias method and derive an expression for the Stability factor& compare with the expression of voltage divider Bias (N/D 2014) (AZ)
5. (i) Explain the circuit which uses a diode to compensate for changes in
VBE and Ico (ii) Discuss the operation of thermistor compensation. (A/M 2010) (R)
6. (i) Draw a CE amplifier of BJT networks. (ii) Derive expressions for ICQ and VCEQ and describe the method of
drawing the dc load line on the output characteristics of transistor (M/J 2012)(R)
7. (i) Compare fixed biasing in BJT and FET. (ii) Explain the procedure for locating suitable operating point on the
characteristics curves. (M/J 2012)(AZ)
8. Draw a self -voltage divider bias and derive all the stability factors S,S‟ and S‟‟ (A/M 2010), (N/D 2010)(R)
9. (i) Draw a voltage divider bias circuit using npn transistors and explain
its operation. (ii) Analyze the circuit and obtain the stability factor of the circuit. (AZ)
10. What is the need for bias compensation? Describe the method of
bias compensation using diodes.(N/D 2011) (R)
11.Explain the use of Thermistor and sensistor for Bias Compensation. (N/D 2011)(R)
5.7
12. Discuss in detail about biasing circuits for an enhancement type
MOSFET. (A/M 2014).(U)
13. List out the importance of selecting the proper operating point. (A/M-15) (R)
UNIT –II BJT AMPLIFIERS
PART-A
1. What is meant by CMRR of a differential amplifier?(N/D 2009) (N/D 2016) (R)
The common mode rejection ratio [CMRR] serves as a figure of merit of a
differential amplifier and is defined as the ratio of the differential mode voltage gain (Ad) to the common mode voltage gain (Ac)
2. What does bootstrapping mean?(R)
Bootstrapping is a technique used to improve the input impedances of common collector (emitter follower) configurations.
3. What is the advantage of Darlington circuit.(N/D 2010),(N/D 2011)(R)
Increased input Resistance and current gain
4. Illustrate are features of differential amplifier? (A)
(a) High differential voltage gain (b) Low common mode gain (c) High CMRR (d) Two input terminals (e) High input impedances (f) Large bandwidth (g) Low offset voltages and currents (h) Low output impedances
5. What are the features of cascode amplifier? (R)
1. The input resistances and current gain of the cascode configuration (h11 and h21) are equal to the corresponding value of a single stage CE amplifier
2. The output resistances is equal to that of CB configuration 3. The millers‟ capacitor shunting the CE input stage is very
5.8
small.This gives very large value of upper cutoff frequency. Therefore the bandwidth of the cascode stage is very large.
4. The internal Feedback due to interelectrode capacitor decreases. 6. Mention two disadvantages which are specific to Darlington connection(N/D2011) & (A/M 2014)(R)
(i).The main drawback of the Darlington pair is that the leakage current of the first transistor is also amplified by the second stage, hence the overall leakage current may be high, so Darlington connection of three or more is impractical. (ii) The principal merit of Darlington circuit is its high input impedance. But the biasing arrangement reduces the input impedance considerable in the case of ordinary emitter follower as well as Darlington emitter follower.
7. Why do we use a current source in emitter terminal in a differential amplifier.(N/D 2010) (R)
To improve the value of CMRR
8. How does input impedance increase due to Darlington connection? (R)
Input impedance increases due to direct coupling of 2 stages of Emitter follower
9. What are the special features of a differential amplifier which is used FETs? (R)
(i). A very high input impedance. (ii). The common mode rejection ability is increased which makes the common gain almost zero,very high value of CMRR
10. Illustrate the effect of bypass capacitor in RC coupled amplifier?(A)
(i).The main effect of by pass capacitor CE in a RC coupled amplifier is that, it cannot shunt the emitter resistance Re effectively, because of its large reactance at low frequencies. (ii) the emitter by pass capacitor offers low reactance path to the signal, without it, the voltage gain of each stage would be lost.
11.What is the coupling schemes used in multistage amplifiers? (A/M2010)(R)
RC Coupling Transformer Coupling Direct Coupling
5.9
12. DefineCMRR.(N/D2010)(R)
CMRR is defined as the ratio between Differential gain and Common
mode gain.
13. Which transistor configuration is more suitable for cascading? Why?(R)
Common Emitter configuration is more suitable for cascading because it has high voltage gain.
14. Why R-C coupling is the most commonly used coupling between the two stages of a cascaded or multistage amplifier?(R) R-C coupling is the commonly used coupling between the two stages of a cascaded or multistage amplifier because it is cheaper, very compact circuit and provides excellent frequency response. 15.Discuss, why the amplifier gain reduces at lower and upper
frequencies?(U)
At lower frequencies the amplifier gain reduces due to the coupling capacitors C1, C2 and bypass capacitors CE.
At upper frequencies the amplifier gain reduces due to the internal transistor capacitance and stray capacitance
16. Why do we cascade the amplifiers?(N/D 2015)(R)
The voltage or power gain obtained from a single stage amplifier is not sufficient to meet the needs of either a composite electronic circuits or load device. So, cascading of amplifiers is needed to provide greater voltage or power gain.
17. What is a multi-stage amplifier circuit?(A/M 2010)(R)
A transistor circuit containing two or more amplification stages is
called as multi-stage amplifier
18.Which transistor configuration is more suitable for cascading? Why?(R)
Common Emitter configuration is more suitable for cascading because it has high voltage gain.
19. Explain why R-C coupling is the most commonly used o
5.10
coupling between the two stages of a cascaded or multistage
amplifier?(AZ)
R-C coupling is the commonly used coupling between the two stages of a cascaded or multistage amplifier because it is cheaper, very compact circuit and provides excellent frequency response.
20.List out the advantages of h parameters (R) i)h-parameters are real numbers upto radio
frequency ii)They are easy to measure iii)They can be determined from transistor static characteristic curves iv)Readily supplied by manufacturers
21. Explain, why coupling capacitor provided in a self biased CE RC
coupled amplifier is also called as blocking capacitor? (AZ)
In a self biased CE RC coupled amplifier, coupling capacitor transmits AC signal but blocks the DC voltage of the first stage from reaching the base of the next stage, so it is also called as the blocking capacitor. 22. How to improve the gain of an RC coupled amplifier at
low frequencies? (AZ) The voltage gain of an RC coupled amplifier at low frequencies can be improved by, selecting very large coupling and bypass capacitors so that their reactance is small
23. Mention two important characteristics of CC circuit.(N/D2013)(R) i)High current gain
ii)Voltage gain of approximately unity iii)Power gain approximately equal to current gain iv)Large input impedance
5.11
PART-B
1. Briefly explain the operation of a Darlington emitter follower and also derive
an expression for its performance measures? (A/M 2014) (U) 2. Analyze a basic common Base Amplifier and derive the expression for its
small- signal voltage gain, current gain, input impedance and output impedance.(N/D 16)(AZ)
3. What is a differential amplifier? Explain its working in differential & common mode operation. Obtain its AC equivalent circuit & derive the expression for voltage gain? (R)
4. What are the methods to improve the CMRR of differential amplifier?
Detail any two of them(R) 5. With the neat sketch, describe the principle of operation of RC coupled
Amplifier?(U) 6. Draw the equivalent circuit of cascaded CE stage and also derive an
expression for its performance measures? (A)
7.(i) Derive the expressions for the following of a small signal transistor
amplifier in terms of the h- parameters
Current gain
Voltage gain
Input impedance
Output impedance (E)
(ii)Compare CB,CE, and CC amplifiers(A/M 2010), (N/D 2011) (U)
8.Discuss the transfer characteristics of the differential amplifier. (A/M2010)(U)
9. Explain with circuit diagram the boot strapped darlington emitter follower.
(M/J 2012) & (A/M 2014)(U)
10.Compare changes in the a.c. characteristics of a common Emitter amplifier when an Emitter Resistance and an emitter bypass capacitor are incorporated
in the design, Explain with necessary equations.(M/J 2016)?(AZ)
5.12
11.Draw the circuit of a emitter coupled differential amplifier and explain its
operation. Analyze the circuit and obtain its transfer characteristics.(A/M 2014)(R)
12.Derive CMRR of differential amplifier with its equivalent circuit (N/D 2014)(U)
13.Explain the operation of cascode amplifier and derive gain,input and
output Impedance.(N/D 2014).(U)
UNIT III JFET AND MOSFET AMPLIFIERS PART A
1. Give the different FET configurations (R)
A. common source amplifier B. common drain amplifier C. common gate amplifier
2. Give the voltage gain of source follower (R)
Unity 3.Statethe advantage of BICMOS cascode amplifier.(R)
MOSFET is used for the input device,provide infinite input resistance.Bipolar Transistor provide larger output resistance.
4. Give the parameters of common gate JFET amplifier(R)
Sr.No parameter With exact analysis With approximate analysis
5.Draw the simplified diagram for a MOSFET amplifier(R)
5.13
6.What are the features of BiMOScascode amplifier?(R) i)infinite input resistance
ii)frequency response of BOCMOS cascode circuit is superior
7.What is source follower(N/D 2016)(R)
A common-drain amplifier,also known as a source follower, is one of three basic single-stage field effect transistor(FET) amplifier topologies, typically used as a voltage buffer.In this circuit (NMOS) the gate terminal of the transistor serves as the input, the source is the output, and the drain is common to both (input and output), hence its name.
8.Define voltage swing(R) The peak-to-peak voltage range of a signal in a circuit. 9.What is common source amplifier(R)
A common-source amplifieris one of three basic single-stage field-effect transistor(FET) amplifier topologies, typically used as a voltage or transconductance amplifier.In common source amplifier, the signal enters the gate, and exits the drain & source is common to both. This is a common-source FET circuit.
10. What is common gate amplifier?(R)
A common-gate amplifieris one of three basic single-stage field-effect transistor(FET) amplifier topologies, typically used as a current buffer voltageamplifier. In common gate amplifier, the signal enters the source, and exits the drain & gate is common to both. This is a common-gate FET circuit.
PART B
1.Draw the circuit of a common source FET amplifier & explain its
operation(R) 2. Draw the high frequency equivalent of FET amplifier and derive all
the parameters (A/M 2008) (R)
3. Discuss in brief about voltage swing limitation of JFET amplifiers (E)
4. With a neat circuit diagram, explain JFET source follower (U)
5. Explain the working operation of BIMOS cascode amplifier with necessary circuit diagram (U)
6. Draw the schematic diagram of small signal equivalent circuit of MOSFET
Amplifier& derive the necessary equations of different parameters(?U)
7.Derive& compare gain, input and output impedance of common source JFET amplifier (different biasing methods)with neat circuit diagram and equivalent circuit.(N/D 2014)(AZ)
8. Derive gain, input and output impedance of MOSFET source follower with neat circuit diagram and equivalent circuit.(N/D 2014)(A)
UNIT –IV FREQUENCY ANALYSIS OF BJT AND MOSFET AMPLIFIERS
PART-A
1. What is frequency response?(R)
The frequency response of an electronic device or an amplifier is defined as “the response of the device to the changes in the frequency of the input signal”
2. What is meant by frequency response curve?(R)
The curve drawn between the voltage gain and signal frequency of an
amplifier is known as the frequency response of an amplifier.
3. What are the different regions in the frequency response curve? (R)
The different regions in the frequency response curve are, 1. Low frequency region 2. Mid frequency region 3. High frequency region
4. Which region is important in the frequency response? Why (A)
Midband region is the important region because the amplifier gain is constant
5. Define Bandwidth.(R)
The Bandwidth of an amplifier is defined as the difference between the upper cutoff frequency and the lower cutoff frequency. BW = fH–fL
6.How a bandwidth can be can be calculated from the frequency response curve? (R)
5.15
Bandwidth of an amplifier can be calculated from the frequency response curve by the following procedure
Step1: Find the mid frequency gain (AV) Step2: Draw a –3dB horizontal line (parallel to x-axis) on the frequency
response curve and obtain the two intersection points. Step3: Project these points on the x-axis as they correspond to the
3dB frequencies f1 and f2 Step4: Calculate BW = f2 – f1
7. What are the other names of fL and fH ? (R)
The other names of fL and fH are, 1. Cutoff frequencies 2. Half power frequencies
3. Corner frequencies
8. What is lower cutoff frequency (R)
The lower cutoff frequency is defined as the frequency at which the
1
magnitude of the voltage gain in the low frequency range falls to
or
2
0.707 of the magnitude of the gain in the mid frequency range.
9. What is Upper cutoff frequency ?(R)
The upper cutoff frequency is defined as the frequency at which the
1
magnitude of the voltage gain in the high frequency range falls to
or
2
0.707 of the magnitude of the gain in the mid frequency range.
10. Define Cutoff frequency(R)
The cutoff frequency is the frequency at which the gain on a frequency response plot is 3dB less than the mid band gain.
11. What is semi log paper?(R)
If one of the axis of the graph paper has a logarithmically spaced scale and the other has conventional linear spacing then the paper is called as semilog graph paper.
5.16
12. Why the frequency response of an amplifier is plotted logarithmically?(AZ)
The frequency response of an amplifier is plotted logarithmically so that a wide range of frequency can be plotted on a convenient size of paper without losing resolution at the low frequency end. (For example, if it is necessary to scale frequencies directly on average sized graph paper over the range from 1HZ to 10KHZ, each small division might represent 100HZ. It would then be impossible to plot points in the range from 1HZ to 10HZ, where the lower cutoff frequencies might occur. When the horizontal scale represents logarithmic of frequency values, the low frequency end is expanded and the high frequency end is compressed. 13. What is a decade? (U)
Any 10 to 1 range of values is called as decade. For example, each of the frequency ranges from 1Hz to 10HZ, 10KHZ to 100KHZ, 500HZ to 5KHZ is called a decade.
14. Give the mathematical expression to find the voltage gain at low frequency region. (R)
The mathematical expression for the low frequency region voltage gain is given by,
AV(mid) AV (low) =
1 + (fL/f )2
15. Give the mathematical expression to find the voltage gain at high frequency region.(R)
The mathematical expression for the low frequency region voltage gain is given by,
AV(mid) AV (high) =
1+ (f/fH )2
16. DefinefT of a BJT(R)
The fTof a BJT is defined as the frequency at which the short circuit common emitter current gain falls to unity. It is equal to f
17. Define f of a BJT
The beta cutoff frequency is defined as the frequency at which the
current gain decreases to 0.707 of its low frequency value.
18. If fT = 500MHz andhfe = 100 for a BJT. What is its?(A)
5.17
fβ= fT X hfe= 5MHz
19.What is the effect of Miller capacitance on the frequency response of an amplifier?(N/D 2014)(AZ)
In inverting amplifiers ,the capacitive element is connected between input
and output terminals of a active device .The large capacitors will control the low frequency response due to their low reactance levels.
20. What do you mean by amplifier rise time? (A/M2010)(R)
It is defined as the time taken for the output to increase from 10% to 90% of output.
21. Define gain-bandwidth product and unity gain frequency. (N/D 2010),(A/M 2008)(R)
Unity gain frequency- It is defined as the frequency at which short circuit CE currentgain becomes unity.
Gain-bandwidth product- It is defined as the product of Ais low and fH 22.Mention the importance of the resistor rbb’ in the transistor hybrid ∏ Model(N/D2011)(R)
The bulk resistance between external base terminal internal node b‟ is represented as resistor rbb’ in hybrid ∏ model.
PART-B
1. Derive the expression for the CE short circuit current gain of transistor at
high frequency(A/M 2010) (U) 2. i)What is the effect of Cb‟e on the input circuit of a BJT amplifier at
Highfrequencies ii)Derive the equation for gm which gives the relation between gm, Ic and temperature. (AZ)
3. i) Draw the high frequency hybrid –π model for a transistor in the CE configuration and explain the significance of each component. (M/J 2012)
ii) Define alpha cut off frequency(M/J 2012),(N/D 2010) (U) 4.Define fα,fβ and fT and state the relation between fβ and
fT. Derive the expressions of fα, fβ and fT(R) 5.Using hybrid π model for CE amplifier. Derive an expression for gain band
width product(A/M 2010) & (A/M 2014) (R) 6.Explain the operation of low frequency response CE amplifier.(AZ) 7.Define the frequency response of multistage amplifier and derive its upper and lower cutt-off frequency. (M/J 2012),(N/D 2009) (AZ)
5.18
8.How does rise and sag time related to cut off frequency? Justify (N/D 2009)(E)
9. Discuss the low frequency response and the high frequency response of an amplifier(A/M 2010) (E)
10.Explain the operation of high frequency common source FET amplifier with neat diagram. Derive the expression for (i) Voltage gain, (ii) Input admittance, (iii) Input capacitance, (iv) Output admittance. (A/M 2010)(AZ)
11.Explain the effect of cascading transistor stages on the bandwidth of a casade amplifier.(AZ)
12.Using hybrid pi model, draw the high frequency equivalent circuit of CE amplifier and derive for higher cut-off frequencies. (N/D 2010) (E)
13.Draw and explain the high frequency equivalent circuit of a FET.(AZ) 14. Explain the high frequency operation of common source amplifier with its
equivalent circuit. (N/D 2014)(AZ)
UNIT 5 : IC MOSFET AMPLIFIERS
PART A
1. Mention the characteristics of CMOS CS AMPLIFIERS (R) a)Very large input resistance b) Very large output resistance c) Potentially large small –signal voltage gain
2.Give the expression of gm in a CMOS common source amplifier.(R)
gm=kn’ W/L(VGS-Vt) 3. State advantages of CMOS Common- Source Amplifier.(R)
a. Like NMOS amplifer with depletion load, CMOS common- source
amplifier also provides large small- signal voltage gain, b. CMOS amplifier does not suffer from body effect.
3. Give a simple method to reduce nonlinearity in common source amplifier.(R) The Gain equation must be a weak function of a signal dependent parameters such as gm. 4. sketch ID and gm of MOSFET as a function of the Vin.(A)
5.19
5. How to increase voltage gain of common source
amplifier(R) By increasing W/L,increasing VRD, reducing ID
6. Define current steering process. (U)
On an IC chip with a number of amplifier stages a constant dc current is generated at one location & is then replicated at various other locations for biasing the various amplifier stages through a process known as current steering. 7.What is an intrinsic gain(R) The maximum voltage gain available from a common source amplifier. 8.What is current mirror(R) In special case of identical transistors, Io=IREF& the circuit simply replicates (or) mirrors the reference current in the output terminal. This is called as current mirror. 9. Define current transfer ratio(R) Ratio between the reference current of current source to output current.
I0/IREF =(W/L)2/(W/L)1 10.What is Dominant –pole response(R) The pole of wp1 will dominate the high-frequency response of the amplifier & the amplifier said to have a dominant –pole response. 11.Define active load(R) IC MOS amplifier consist of a grounded source MOS transistor with the drain resistor RD replaced by a constant – current source I. The current source can be implemented using a PMOS transistor. This is called as an active load.
5.20
PART B
1.With necessary equation,circuit diagram explain about IC MOSFET amplifier Biasing.(U)
2.Explain the working operation of CMOS differential amplifier.(U)
3. Interpret the voltage transfer characteristics of differential amplifier. (U)
4. Explain IC biasing current steering circuit using MOSFET. (U)
5.Discuss in detail about MOSFET current sources.(U) 6. With the necessary circuit diagrams , explain about MOSFET amplifiers with
active loads (U)
7. Derive the expression of CMRR in a CMOS differential amplifier (U)
8.Draw the circuit of CMOS common source and source follower, explain
the working operation (U) 9.Draw a MOS current steering circuit ,write the expression for the terminal
currents in terms of reference current.(N/D 2014) (R) 10. Derive gain, input and output impedance of common source amplifier
with NMOS diode connected active load.(N/D 2014) (U)
5.21
PART-C & ASSIGNMENT QUESTIONS
UNIT1
1. a)Analyze a BJT With a voltage divider bias circuit, and determine the
change in the Q- point with a variation in β when the circuit contains an
emitter Resistance . Let the biasing resistors be RB1= 56KΩ, RB2= 12.2KΩ,
RC= 2KΩ,RE=0.4KΩ, VCC= 10V, V BE(on)= 0.7 V and β= 100(N/D16) (AZ)
b)Consider the circuit shown below with transistor parameters IDSS=
12mA, VP=-4v and λ= 0.008 V-1. Determine the small signal voltage gain
AV = VO/Vi(N/D16) (E)
2. Determine the quiescent current & voltage values in a p-channel JFET circuit(E)
5.22
3. The circuit in the figure has hfe=100. Find VTH and RTH for the base
circuit. Determine the ICQ and VCEQ values. Also draw the DC load line(E)
UNIT 2
1. Design the cascode circuit shown below to meet the following
specifications: VCE1=VCE2=2.5V,VRE=0.7V,IC1=IC2=1mA and
IR1=IR2=IR3=0.1mA (N/D16) (C)
2. A small signal source Vi(t)= 20 cos20t+30sin106t is applied to a
Transistor Amplifier as shown inFigure, the Transistor has hfe=150, ro=∞
and rs=3K. Determine Vo(t).(E)
5.23
3. Consider the circuit shown in the figure with the parametrs:hfe= 120
and VA=∞.
Determine i) current gain , voltage gain, input impedance,output
impedance.
ii)Maximum undistorted output voltage swing.(E)
4. The parameters for each transistor in the circuit in figure are hfe=100,
VA=∞ and V BE(ON)= 0.7V.
Determine the input & output impedances. (E)
5.24
5. For the circuit shown in the figure, the Transistor parameters are
hfe=125, VA=∞, VCC=18V,RL=4k,RE=3K,RC=4K,R1=25.6K,R2=10.4K. The
input signal is a current source. Determine its small signal voltage gain,
current gain, maximum voltage gain and input impedance.(E)
UNIT3
1. Determine the small- signal voltage gain of a multi-stage cascade circuit
shown in the figure below. The Transistor parameters are Kn1 =
0.5mA/V2, Kn2 = 0.2mA/V2, VTN1= VTN2=1.2v and λ1= λ2 =0.The
Quiescent drain currents are ID1 = 0.2mA and ID2= 0.5mA(N/D16)(E)
2. Design the circuit shown below such that IDQ= 100µA, VSDQ= 3V and
VRS=0.8V.Note that VRS is the voltage across the source Resistor RS. The
value of the larger Resistor, either R1 or R2 is to be 200KΩ. Transistor
parameter values are KP= 100µA/v2 and VTP= -0.4v . The conduction
parameter, Kp may vary by 5 percent. (N/D16)(C)
5.25
3. Design a JFET source follower circuit with a specified small signal
voltage gain IDSS=12mA, VP=-4V,λ=0.01 V-1. Determine RS and IDQ such
that the small signal voltage gain is atleast AV= VO/VI = 0.90(C)
4. Determine the small signal voltage gain of a common source circuit containing a source resistor. The Transistor parameters are VTN= 0.8V,
kn= 1mA/V2 and λ = 0.(E)
5.26
5.Derive the voltage gain of BICMOS cascade Amplifier shown in the figure.(E)
6.Consider the PMOS Amplifier shown in figure. The Transistor parameters
are Vtp=-1v, β= 1mA/V2 and λ = 0.
i)Determine RD and RS, such that IDQ= 0.75mA and VSDQ= 6V.ii) determine
the input & output Resistance.iii)Voltage gain, Current gain & Maximum
output voltage swing.(E)
5.27
UNIT4
1. Determine the 3 dB frequencies and mid band gain of a cascade circuit.
For the figure, the parameters are V+ = 10V, V=-10V, Rs=1K,R1=42.5K,R2=20.5K,R3=28.3K,RE=5.4K,Rc=5K,RL=10K,CL=0. The Transistor parameters are β=150, VBE(ON) = 0.7v,VA =∞,Cπ=35PF
and Cµ= 4PF(E)
2. The Transistor in the figure has parameters β = 125, VBE(ON) = 0.7V,
VA = 200V,Cπ=24PF and Cµ= 3 pf.
i)Calculate the miller capacitor ii) determine the upper 3 dB frequency.
iii) determine the small signal mid band voltage gain(E)
3. For the circuit shown in the figure, has the following parameters:
hfe=125,Cπ = 24pF,Cµ = 3pF. Determine i)mid-band gain, upper cut-off frequency
ii)Find the value of CC1, CC2 and CE by assuming lower cut-off frequency of 100 Hz.(E)
5.28
4. For the circuit shown in figure, the NMOS Transistor parameters are:
µnCox(W/L) = 2mA/V2, VGSQ= 3.25v,Cgd=0.1pf and Cgs=1pf.Calculate the
mid-band gain, input impedance, output impedance, bandwidth and
maximum output voltage swing.(E)
UNIT 5
1. For the circuit shown in the figure, let V+= 10v and V-=0 and the Transistor
parameters are VTN= 2V,1/2 µnCox= 20µA/V2 and λ= 0. Design the circuit
such that I ref= 0.5mA and Io= 0.2mA remains biased in the saturation
region for VDS2> 1v(C)
5.29
2. For the circuit shown in figure, VDD= VSS= 1.5V,vtn=0.6V, Vtp=-0.6v, all
channel lengths = 1µm. Kn=200 µA/V2, Kp= 80 µA/V2 and λ= 0. For
Iref= 10 µA, find the widths of all transistors to obtain I2=60 µA, I3=20 µA
and I5= 80 µA.(E)
3. Consider the circuit of NMOS Amplifier with depletion Load. The
Transistor parameters are VTN= 0.8v, VTNL= -1.2v, βnd=500 µA/V2,
βnd=500 µA/V2,IDQ= 100 µA, VDD=5v .
i) Determine VGS such that Q point is in the middle of the saturation
region.
ii) Calculate the Q-point drain current.
iii) Determine the small signal voltage gain.(E)
6.1
PANIMALAR ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS AND
COMMUNICATION ENGINEERING
EE6352
ELECTRICAL ENGINEERING AND
INSTRUMENTATION SOLVED TWO MARKES AND PART – B & PART – C
QUESTIONS (FOR THIRD SEM ECE)
6.2
UNIT-I DC MACHINES
PART-A
1. What is prime mover? [R]
The basic source of mechanical power which drives the armature of the
generator is called prime mover.
2. Give the materials used in machine manufacturing? [R]
There are three main materials used in m/c manufacturing they are steel
to conduct magnetic flux copper to conduct electric current insulation.
3. What are factors on which hysteresis loss depends? [U]
It depends on magnetic flux density, frequency & volume of the material.
4. What is core loss? What is its significance in electric machines? [U]
When a magnetic material undergoes cyclic magnetization, two kinds of
power losses occur on it. Hysteresis and eddy current losses are called as core
loss. It is important in determining heating, temperature rise, rating & efficiency
of transformers, machines & other A.C run magnetic devices.
5. What is eddy current loss? [R]
When a magnetic core carries a time varying flux, voltages are induced in
all possible path enclosing flux. Resulting is the production of circulating flux in
core. These circulating current do no useful work are known as eddy current and
have power loss known as eddy current loss.
6. How hysteresis and eddy current losses are minimized? [U]
Hysteresis loss can be minimized by selecting materials for core such as
silicon steel & steel alloys with low hysteresis co-efficient and electrical resistivity.
Eddy current losses are minimized by laminating the core.
7. How will you find the direction of emf using Fleming’s right hand rule?
[U]
The thumb, forefinger & middle finger of right hand are held so that these
fingers are mutually perpendicular to each other, then forefinger gives the
direction of the lines of flux, thumb gives the direction of the relative motion of
conductor and middle finger gives the direction of the emf induced.
6.3
8. How will you find the direction of force produced using Fleming’s left
hand rule? [U]
The thumb, forefinger & middle finger of left hand are held so that these
fingers are mutually perpendicular to each other, then forefinger gives the
direction of magnetic field, middle finger gives the direction of the current and
thumb gives the direction of the force experienced by the conductor.
9. What is the purpose of yoke in d.c machine? [R] 1. It acts as a protecting cover for the whole machine and provides
mechanical support for the poles. 2. It carries magnetic flux produced by the poles
10. What are the types of armature winding? [R]
1. Lap winding, A=P, 2. Wave winding, A=2.
11. How are armatures windings are classified based on placement of coil inside the armature slots? [U]
Single and double layer winding.
12.Write down the emf equation for d.c.generator? [C]
E= (ФNZ/60)(P/A)V. Where P –no of poles -Total no of conductor,
Ф -flux per pole, N-speed in rpm.
13. Why the armature core in d.c machines is constructed with laminated
steel sheets instead of solid steel sheets? [A]
Lamination highly reduces the eddy current loss and steel sheets provide
low reluctance path to magnetic field.
14.Why commentator is employed in d.c.machines? [A]
Conduct electricity between rotating armature and fixed brushes, convert
alternating emf into unidirectional emf (mechanical rectifier).
15. Distinguish between shunt and series field coil construction? [A]
Shunt field coils are wound with wires of small section and have more no of
turns. Series field coils are wound with wires of larger cross section and have less
no of turns.
16. How does d.c. motor differ from d.c. generator in construction? [A]
Generators are normally placed in closed room and accessed by skilled
6.4
operators only. Therefore on ventilation point of view they may be constructed
with large opening in the frame. Motors have to be installed right in the place of
use which may have dust, dampness, inflammable gases, chemical etc. to protect
the motors against these elements the motor frames are used partially closed or
totally closed or flame proof.
17. How will you change the direction of rotation of d.c.motor? [E]
Either the field direction or direction of current through armature
conductor is reversed.
18. What is back emf in d.c. motor? [R]
As the motor armature rotates, the system of conductor come across
alternate north and South Pole magnetic fields causing an emf induced in the
conductors. The direction of the emf induced in the conductor is in opposite to
current. As this emf always opposes the flow of current in motor operation it is
called as back emf.
19. What is the function of no-voltage release coil in d.c. motor starter? [R]
As long as the supply voltage is on healthy condition the current through
the NVR coil produce enough magnetic force of attraction and retain the starter
handle in ON position against spring force. When the supply voltage fails or
becomes lower than a prescribed value then electromagnet may not have enough
force to retain so handle will come back to OFF position due to spring force
automatically.
20. Enumerate the factors on which speed of a d.c.motor depends?
(Non/Dec2015) [A]
N = (V-Ia Ra) / Ф so speed depends on voltage applied to armature,
flux per pole, resistance of armature.
21. Under what circumstances does a dc shunt generator fails to generate?
[AZ]
Absence of residual flux, initial flux set up by field be opposite in direction
to residual flux, shunt field circuit resistance may be higher than its critical field
resistance, load circuit resistance may be less than its critical load resistance
22. Define critical field resistance of dc shunt generator? [R]
Critical field resistance is defined as the resistance of the field circuit
which will cause the shunt generator just to build up its emf at a specified field.
6.5
23.Why is the emf not zero when the field current is reduced to zero in dc
generator? [A]
Even after the field current is reduced to zero, the machine is left out with
some flux as residue so emf is available due to residual flux.
24.On what occasion dc generator may not have residual flux? [A]
The generator may be put for its operation after its construction, in
previous operation, the generator would have been fully demagnetized.
25.What are the conditions to be fulfilled by for a dc shunt generator to
build back emf? [R]
The generator should have residual flux, the field winding should be
connected in such a manner that the flux setup by field in same direction as
residual flux, the field resistance should be less than critical field resistance, load
circuit resistance should be above critical resistance.
26.Define armature reaction in dc machines? [R]
The interaction between the main flux and armature flux cause
disturbance called as armature reaction
27.What are two unwanted effects of armature reactions? [R]
Cross magnetizing effect & demagnetizing effect.
28.What is the function of carbon brush used in dc generators? [AZ]
The function of the carbon brush is to collect current from commutator and
supply to external load circuit and to load.
29.What is the principle of generator? [AZ]
When the armature conductor cuts the magnetic flux emf is induced in the
conductor.
30. What is the principle of motor? (Nov/Dec 2016)[AZ]
When a current carrying conductor is placed in a magnetic field
it experiences a force tending to move it.
31.What are different methods of speed control in D.C shunt motor? [R] • Armature control
6.6
• Flux or field control • Applied voltage control
32. When is a four point DC starter required in DC motors? [A]
A four point DC starter is required for dc motor under field control .
33. If speed is decreased in a dc motor, what happens to the back emf
decreases and armature current? [A]
If speed is decreased in a dc motor, the back emf decreases and armature
current increases.
34. How does a series motor develop high starting torque? [U]
A dc series motor is always started with some load. Therefore the motor
armature current increases. Due to this, series motor develops high starting
torque.
35. What is the necessity of starter in dc motors? [U]
When a dc motor is directly switched on, at the time of starting, the motor
back emf is zero. Due to this, the armature current is very high. Due to the very
high current, the motor gets damaged. To reduce the starting current of the
motor a starter is used.
36.Mention the types of braking of dc motor? [R] 1. braking
2. Dynamic braking 3. Regenerative Plugging
37. What are the losses in dc motor? [R] 1. Copper losses 2. Iron losses
3. Mechanical losses
38. Name any 2 non-loading method of testing dc machines? [R] 1. Swinburne’s test
2. Hopkinson test
39. Mention the advantages of star and delta systems.(April/May 2015)[ C ]
Star Connection:
1. In star connection, we get 3-phase and 4-wire system. This permits the use of two voltages (phase voltages as well as line voltages). Single phase loads
6.7
can be connected between any one lie and neutral wire while the 3-phase loads can be put across the three lines. Such flexibility is not available in
delta connection. 2. In star connection, the neutral point can be earthed. Such a measure offers
many advantages. For example, in case of line to earth fault (L-G fault), the insulators have to bear 1/31/2 (57.7%) times the line voltage. Earthing of neutral also permits the use of protective devices (relays) to protect the
system in the case of ground faults
Delta Connection:
1. This type of connection is most suitable for rotatory conveyers.
2. Most of the three phase loads are delta connected than star connected. One reason for this, at least for the case of unbalanced load, is the flexibility with which loads may be added or removed on a single phase. This is difficult to do
with star connected 3-wire load.
3. Most of the 3-phase induction motors are delta connected.
40. Faraday’s law of electromagnetic induction is used in what type of DC machine? Write its principle of operation. (May/June2016) [E]
Faraday’s law of electromagnetic induction is used in DC motor and
generators.
First Law of Faraday's Electromagnetic Induction state that whenever a conductor are placed in a varying magnetic field emf are induced which is called induced emf, if the conductor circuit are closed current are also induced which is
called induced current.
41.Why is the starting current very high in a dc motor?(May/June2016)[ R ]
A rotating d.c. motor generates a back-emf which opposes the supply voltage and reduces the current drawn by the motor. When the motor is
stationary, it cannot generate this back emf and, so, the only opposition to current is the resistance of its windings which is relatively low. So, on startup, the current is large ; as the machine starts to run, the resulting back emf, acts to
reduce the current.
42.How are D.C machines classified? (Nov/Dec2015)[C]
D.C machines are classified as D.C Motor & D.C Generator
6.8
PART -B
1. What is the principle on which d.c. Generator works? List out the main parts of it. Write details about the construction and function main parts of it
(Nov/Dec2016) [U]
2. Describe the working principle of d.c generator and d.c motor with neat diagrams. (May/June2016)[U]
3. Write the expression for emf generated in d.c. Machine? [R]
4. Describe the different types of d.c. Generators and discuss about its characteristics? (April/May 2015 )[A]
5. Draw the circuit models of d.c. generator and write relationship among the
currents and voltage.[C] 6. Derive the torque equation of dc motors? (April/May2015) [A]&[E]
Draw the mechanical characteristics of (N-T) dc shunt and series motors 7. Why series motors cannot be started without load. [A] 8. Draw the diagram of three point starter and identified the various parts. [A]
9. Describe the brake test on dc motors to determine the efficiency characteristics of dc motors. [U]
10. Explain the Swinburne test to predetermine the efficiency of dc machine.[R] 11. Explain the speed control methods of D.C motor.[R]
PART-C
1.A 220V dc shunt motor draws 4.5A on no load and runs at 1000rpm.Resistance of the
armature winding and shunt field winding is 0.3 and 157 ohms respectively. Calculate
the speed when loaded and drawing a current of 30A.Assume that the armature reaction
weakens the field by 3%. (May/June 2016)[A]
2.A 4-pole lap wound DC shunt generator has a useful flux/pole of 0.06Wb.The
armature winding consists of 200turns,each turn having a resistance of
0.003Ω.Calculate the terminal voltage when running at 1000rpm if armature current is
45A.
(Nov/Dec 2016)[A]
3.A 10Kw 250V,DC shunt generator is driven at 1000rpm.Armature circuit resistance is
0.15Ω and the field current is 1.64A when the terminal voltage is 250V.Rotational losses
are to be 540W.Find at rated load armature induced emf, developed torque and
efficiency.
(April/May2015)[A]
4. A 200V DC motor has an armature resistance of 0.06Ω and series field resistance of
0.04Ω.If the motor input is 20kW, find the back emf of the motor and power developed in
armature. (April/May 2015)[A]
6.9
UNIT-II TRANSFORMERS PART -A
1. Define a transformer? [R]
A transformer is a static device which changes the alternating voltage from
one level to another.
2. What is the turns ratio and transformer ratio of transformer? [U]
8. Define all day efficiency of a transformer? [R]
It is computed on the basis of energy consumed during a certain period,
usually a day of 24 hrs. all day efficiency=output in kWh/input in kWh for 24
hrs.
9. Why transformers are rated in kVA? [U]
Copper loss of a transformer depends on current & iron loss on voltage.
Hence total losses depend on Volt-Ampere and not on PF. That is why the rating
of transformers are in kVA and not in kW.
10. What determines the thickness of the lamination or stampings? [U] 1. Frequency
2. Iron loss
11. What are the typical uses of auto transformer? [U]
1. To give small boost to a distribution cable to correct for the voltage drop.
2. As induction motor starter.
12. What are the applications of step-up & step-down transformer? [U]
Step-up transformers are used in generating stations. Normally the
generated voltage will be either 11kV. This voltage (11kV) is stepped up to 110kV
or 220kV or 400kV and transmitted through transmission lines (simply called as
sending end voltage).
Step-down transformers are used in receiving stations. The voltage are
stepped down to 11kV or 22kV are stepped down to 3phase 400V by means of a
distribution transformer and made available at consumer premises. The
transformers used at generating stations are called power transformers.
13. How transformers are classified according to their construction? [U]
1. Core type 2. Shell type.
In core type, the winding (primary and secondary) surround the core and
In shell type, the core surrounds the winding.
14. Explain on the material used for core construction? [U]
The core is constructed by sheet steel laminations assembled to provide a
continuous magnetic path with minimum of air gap included. The steel used is of
high silicon content sometimes heat treated to produce a high permeability and a
low hysteresis loss at the usual operating flux densities. The eddy current loss is minimized by laminating the core, the laminations being
used from each other by light coat of core-plate vanish or by oxide layer on the
surface.
6.11
15. How does change in frequency affect the operation of a given
transformer? [U]
With a change in frequency, iron and copper loss, regulation, efficiency &
heating varies so the operation of transformer is highly affected.
16.What is the angle by which no-load current will lag the ideal applied voltage? [U]
In an ideal transformer, there are no copper & core loss i.e. loss free core.
The no load current is only magnetizing current therefore the no load current lags
behind by angle 900. However the winding possess resistance and leakage
reactance and therefore the no load current lags the applied voltage slightly less
than 900.
17. List the arrangement of stepped core arrangement in a transformer? [R] 1. To reduce the space effectively
2. To obtain reduce length of mean turn of the winding
3. To reduce I2R loss.
18. Why are breathers used in transformers? [U]
Breathers are used to entrap the atmospheric moisture and thereby not
allowing it to pass on to the transformer oil. Also to permit the oil inside the tank
to expand and contract as its temperature increases and decreases.
19. What is the function of transformer oil in a transformer? [U] 1. It provides good insulation 2. Cooling.
20. Can the voltage regulation go –ive? If so under what condition? [A]
Yes, if the load has leading PF.
21. Distinguish power transformers & distribution transformers? [A]
Power transformers have very high rating in the order of MVA. They are
used in generating and receiving stations. Sophisticated controls are required.
Voltage ranges will be very high. Distribution transformers are used in receiving
side. Voltage levels will be medium. Power ranging will be small in order of kVA.
Complicated controls are not needed.
22. Name the factors on which hysteresis loss depends? [R]
1. Frequency 2. Volume of the core 3. Maximum flux density
6.12
23.Why the open circuit test on a transformer is conducted at rated
voltage? [U]
The open circuit on a transformer is conducted at a rated voltage because
core loss depends upon the voltage. This open circuit test gives only core loss or
iron loss of the transformer.
24. What are the necessary tests to determine the equivalent circuit of the Transformer? [U]
1. Open circuit test 2. Short circuit test
25. Define regulation and efficiency of the transformer? [R]
The regulation of the transformer is defined as the reduction in magnitude of
the terminal voltage due to load, with respect to the no-load terminal voltage. % regulation = (V2 on no-load-V2 when loaded/ V2 on no-load) x 100
%Transformer efficiency ƞ = (output power/input power) x 100
PART-B
1. What is Transformers? Define step up and step down Transformer? [U]
2. Classify the transformers according to the construction? [R] 3. Describe the construction of single phase Transformer? [A]
4. Discuss about the working principle of transformers. [U]
5. Derive the equation for the emf induced in a transformer? (Nov/Dec 2015) [E]
6. What is an ideal transformer? [U]
7. Draw and explain the no load vector diagram of ideal transformers and practical Transformers [A]
8. What are the two components of transformers no load current? [A]
9. Explain the behavior of a transformer on load with relevant to phasor
diagrams? (Nov/Dec 2016) [C]& [U]
10. Derive the equivalent circuit of single phase two winding transformers?
(April/may 2015) [E]
6.13
11. Explain the OC and SC test on single phase transformers. Develop the
equivalent circuit from the above tests? (Nov/Dec 2016)[U]& [C]
12. Draw the phasor diagram and explain the operation of practical transformer
on load? [C]
13. Define voltage regulation. Draw the phasor diagram for lagging power factor and determine voltage regulation. [K] &[C]
14. Compare the operation of the transformer when in no load and on load
respectively with their relevant phasor diagrams. (Nov/Dec 2015)[U]
PART-C
1. A 20 KVA single phase transformer designed for 2000/200V per phase the
following constant: R1=2.5Ω,X1=8Ω,R1=0.04 Ω and X2=0.07Ωcalcultae the approximate value of the secondary terminal voltage and %regulation at the full
load and 0.8p.flagging when primary applied voltage is 2000 V . (April/may 2015) [A]
2. Find the all day efficiency of a transformer having maximum efficiency of 98% at15KVA at unity power factor and loaded as follows: (April/may 2015) [A]
12 hours -- 2KW at 0.5 p.f lag 6 hours -- 12 KW at 0.8 p.f lag 6 hours -- at no load
3. A 1100/110 V, 22KVA single phase transformer has primary resistance and reactance 2Ω and 5Ω respectively .the secondary resistance and reactance are
0.02Ωand 0.045 Ω respectively calculate: (April/may 2015) [A] 1. Equivalent resistance and reactance of secondary referred to primary
2. Total resistance and reactance referred to primary 3. Equivalent resistance and reactance of primary referred to secondary 4. Total resistance and reactance referred to secondary
5. Total copper loss 3. The maximum efficiency of a 500KVA, 3000/500V, 50Hz single phase
transformer is 98%and occurs at 3/4 full load unity power factor lagging. if the impedance is 100%.calculate the regulation at full load 0.8 power factor lagging.
(May/June 2016)[A]
6.14
UNIT – III INDUCTION MACHINES AND SYNCHRONOUS MACHINES
PART -A
(i) INDUCTION MACHINES
1. What are the 2 types of 3phase induction motor? [R] Squirrel cage and slip ring induction motor.
2. Write two extra features of slip ring induction motor? [U]
Rotor has 3-phase winding. Extra resistance can be added in rotor circuit
for improving PF with the help of three slip rings.
3. Why an induction motor is called as rotating transformer? [U]
The rotor receives same electrical power in exactly the same way as the
secondary of a two winding transformer receiving its power from primary. That is
why induction motor is called as rotating transformer.
4. Why an induction motor never runs at its synchronous speed? [U]
If the motor runs at sync. speed then there would be no relative speed
between the two, hence no rotor emf, so no rotor current, then no rotor torque to
maintain rotation.
5. What are slip rings? [U]
The slip rings are made of copper alloys and are fixed around the shaft
insulating it. Through these slip rings and brushes rotor winding can be
connected to external circuit.
6. What are the advantages of cage motor? [U]
Since the rotors have low resistance, the copper loss is low and efficiency is
very high. On account of simple construction of rotor it is mechanically robust,
initial cost is less, maintenance cost is less, simple starting arrangement.
7. Give the condition for maximum torque for 3phase induction motor,
when it is running? [R] The rotor resistance and reactance should be same for max.torque i.e. R2=S*X2
8. List out the method for speed control of 3phase cage type induction
motor? By changing supply frequency [R] [U]
1. By changing no of poles 2. By operating the two motors is cascade
6.15
9. Name the two winding of single phase induction motor? [R] Running and starting winding
10. What are methods available for making single phase induction motor a
self starting?[U]
By slitting the single phase, by providing shading coil in the poles.
11. What is the function of capacitor in single phase induction motor? [R]
To make phase difference between starting and running winding, to
improve PF and to get more torque.
12. State any 4 use of single phase induction motor? [R] Fans, wet grinders, vacuum cleaner, small pumps, compressors, drills.
13. What kind of motors used in ceiling fan and wet grinders? [U] Ceiling fan -Capacitor start and capacitor run single phase induction motor, wet grinders -Capacitor start capacitor run single phase induction motor.
14. How to reverse the direction of rotation of 3 phase induction motor?[C]
By interchanging any two terminals of three phase winding while connecting it to three phase a.c. supply, direction of rotation of rotating magnetic field gets reversed.
15. What is the application of shaded pole induction motor? [A]
Because of its small starting torque, it is generally used for small toys,
instruments, hair driers, ventilators.etc.
16. In which direction a shaded pole motor runs? [U]
The rotor starts rotation in the direction from un shaded part to the shaded
part.
17. Why single phase induction motors have low PF? [U]
The current through the running winding lags behind the supply voltage by large
angle so only single phase induction motor have low PF.
18. Differentiate between “capacitor start” & “Capacitor start capacitor run”
single Phase induction motor (IM)? [A]
Capacitor start – capacitor run is connected series with starting winding,
but it will be disconnected from supply when motor pick up its speed. Capacitor
start Capacitor run starting winding and capacitor will not be disconnected from
6.16
supply even though motor pick up its speed.
19. Define slip in an IM? (May/June 2016) [R]
The slip of an IM is defined as the ratio of difference between sync.
speed (Ns) and rotor speed (N) to the sync. Speed s= (Ns – N)/ Ns
20. Define slip speed in an IM? [R]
The slip speed is defined as the difference in speed between the rotating
magnetic field produced by stator (Ns) and rotor speed (N). 21. What is the speed of the rotor field in space? [U] The speed of the rotor field in space is speed of rotating field.
22. What is sync. Speed in 3-phase IM? [U]
Ns = 120f/p Where f-supply frequency, P-No of poles on the stator. 23. List the various methods of speed control of 3 phase IM? [R]
Types of stator side control
1. Stator voltage control 2. Stator frequency control
3. v/f control 4. pole changing method 5. starting torque increased
6. starting current decreased 7. motor speed can be controlled
24. Why the slots on the IM are usually skewed? [U]
In order to obtain a uniform torque, reduce the magnetic locking of the
stator and rotor and reduce the magnetic humming noise while running.
25. What are the types of poly phase IM? [U] 1. Squirrel cage IM 2. Slip ring IM
26. What is slip power recovery scheme? [U]
Slip power can be returned to the supply source and can be used to supply
an additional motor which is mechanically coupled to the main rotor. This type of
drive is known as slip power recovery system and improves overall efficiency of
the system.
6.17
27. For domestic and commercial purposes which motor is best suited and
why? (Nov/Dec 2015) [A]
Single phase induction motor. Where three-phase power is unavailable or
impractical, it’s single-phase motors to the rescue. Though they lack the higher
efficiencies of their three-phase siblings, single-phase motors — correctly sized
and rated — can last a lifetime with little maintenance.
(ii)ALTERNATOR
1. Why almost all large size Synchronous machines are constructed with rotating field system type? [U]
The following are the principal advantages of the rotating field system type
construction of Synchronous machines: The relatively small amount of power, about 2%, required for field system via slip-rings and brushes.
For the same air gap dimensions, which is normally decided by the kVA
rating, more space is available in the stator part of the machine for providing more insulation to the system of conductors, especially for machines rated for 11kV or above. Insulation to stationary system of conductors is not subjected to
mechanical stresses due to centrifugal action. Stationary system of conductors can easily be braced to prevent
deformation. It is easy to provide cooling arrangement for a stationary system of conductors. · Firm stationary connection between external circuit and system of conductors
enable he machine to handle large amount of volt-ampere as high as 500MVA.
2.Write down the equation for frequency of emf induced in an Alternator. [E] Frequency of emf induced in an Alternator,f ,expressed in cycles per second or Hz, is given by the following equation F = (PN)/120 Hz, Where P-
Number of poles N-Speed in rpm 3. How are alternators classified? [A]
According to type of field system · Stationary field system type · Rotating field system type -According to shape of field system · Salient pole type · Smooth
cylindrical type 4. Name the types of Alternator based on their rotor construction.[R]
Alternators can be classified into the following two types according to its
rotor construction · Smooth cylindrical type alternator · Salient pole alternator
5. Why do cylindrical Alternators operate with steam turbines? [U] Steam turbines are found to operate at fairly good efficiency only at high
speeds. The high speed operation of rotors tends to increase mechanical losses
and so the rotors should have a smooth external surface. Hence, smooth cylindrical type rotors with less diameter and large axial length are used for
6.18
Synchronous generators driven by steam turbines with either 2 or 4 poles.
6. Which type of Synchronous generators are used in Hydro-electric plants and why? [U]
As the speed of operation is low for hydro turbines use in Hydro-electric plants, salient pole type Synchronous generators are used. These allow better ventilation and also have other advantages over smooth cylindrical type rotor.
7. What are the advantages of salient pole type construction used for Synchronous machines? [A]
Advantages of salient-pole type construction are: 1. They allow better ventilation
2.The pole faces are so shaped that the radial air gap length increases from the pole center to the pole tips so that the flux distribution in the air-gap is sinusoidal in shape which will help the machine to generate sinusoidal emf · Due
to the variable reluctance the machine develops additional reluctance power which is independent of excitation
8. Why is the stator core of Alternator laminated? [U]
The stator core of Alternator is laminated to reduce eddy current loss.
9. How does electrical degree differ from mechanical degree? [A]
Mechanical degree is the unit for accounting the angle between two points
based on their mechanical or physical placement. Electrical degree is used to account the angle between two points in rotating electrical machines. Since all
electrical machines operate with the help of magnetic fields, the electrical degree is accounted with reference to the magnetic field. 180 electrical degree is accounted as the angle between adjacent North and South poles.
10. Write down the e.m.f equation of an alternator. [C]
𝐸𝑝ℎ = 4.44𝐾𝐶𝐾𝑑 ∗ 𝑓 ∗ 𝛷𝑇𝑝ℎ
11. What is distributed winding? [U]
When coil-sides belonging to each phase are housed or distributed in
more than one slot under each pole region then the winding is called distributed winding.
12. Why is short pitch winding preferred over full-pitch winding? [A]
Advantages · Waveform of the emf can be approximately made
to a sine wave and distorting harmonics can be reduced or totally eliminated. · Conductor material, copper, is saved in the back and front end connections due
to less coil-span. · Fractional slot winding with fractional number of slots/phase can be used which in turn reduces the tooth ripples. · Mechanical strength of the coil is increased.
6.19
13. Write down the formula for distribution factor. [E] Kd =sin(mβ/2)/ (m sin β/2) , m= number of slots/ pole/ phase n = order
of harmonic β= angle between adjacent slots in electrical degree
14. Define winding factor. [R] The winding factor Kd is defined as the ratio of phasor addition of emf
induced in all the coils belonging to each phase winding to their arithmetic addition.
15. Why are Alternators rated in kVA and not in kW? [U]
The continuous power rating of any machine is generally defined as the power the machine or apparatus can deliver for a continuous period so that the losses incurred in the machine gives rise to a steady temperature rise not exceeding the
limit prescribed by the insulation class. Apart from the constant loss incurred in Alternators is the copper loss, occurring in the 3 –phase winding which depends
on I2 R, the square of the current delivered by the generator. As the current is directly related to apparent – power delivered by the generator, the Alternators have only their apparent power in VA/kVA/MVA as their power rating.
16. What are the causes of changes in voltage in Alternators when loaded?[A]
Variations in terminal voltage in Alternators on load condition are due to the following three causes: · Voltage variation due to the resistance of the
winding, R · Voltage variation due to the leakage reactance of the winding, Xl · Voltage variation due to the armature reaction effect, Xa
17. What is meant by armature reaction in Alternators? [U]
The interaction between flux set up by the current carrying armature Ia
and the main field Im is defined as the armature reaction.
18. What do you mean by synchronous reactance? [U] Synchronous reactance X s= (Xl + Xa) The value of leakage reactance Xl is
constant for a machine based on its construction. Xa depends on saturating
condition of the machine. It is the addition of Xa, which represent the armature reaction effect between two synchronously acting magnetic fields that makes the total reactance Xa to be called synchronous reactance
19. What is meant by synchronous impedance of an Alternator? [U]
The complex addition of resistance, R and synchronous reactance, jXs can
be represented together by a single complex impedance Zs called synchronous
impedance. In complex form Zs = (R + jXs ) In polar form Zs = | Zs | ∟ Where |
Zs | = √(R2 + Xs2) And =tan-1 (Xs /R)
20. What is meant by load angle of an Alternator? [U] The phase angle introduced between the induced emf phasor, E and
terminal voltage phasor , U during the load condition of an Alternator is called
6.20
load angle.
21. Upon what factors does the load angle depend? [A]
The nature of load angle increases with increases in load. Further the load
angle is positive during generator operation and negative during motor operation.
22. An Alternator is found to have its terminal voltage on load condition more than that on no load. What is the nature of the load connected? [A]
The nature of the load is of leading power factor , load consisting of
resistance and capacitive reactance. 23. Define the term voltage regulation of Alternator. [R]
The voltage regulation of an Alternator is defined as the change in terminal voltage from no-load to load condition expressed as a fraction or
percentage of terminal voltage at load condition; the speed and excitation conditions remaining same. Voltage regulation in percentage, URP = [(|E|-|U|)/|U|] x 100
24. What is the necessity for predetermination of voltage regulation? [U]
Most of the Alternators are manufactured with large power rating, hundreds of kW or MW, and also with large voltage rating up to 33kV. For Alternators of such power and voltage ratings conducting load test is not
possible. Hence other indirect methods of testing are used and the performance like voltage regulation then can be predetermined at any desired load currents and power factors.
25. Name the various methods for predetermining the voltage regulation of
3phase Alternator. [R] The following are the three methods which are used to predetermine the
voltage regulation of smooth cylindrical type Alternators · Synchronous
26. How synchronous impedance is calculated from OCC and SCC? [A] Synchronous impedance is calculated from OCC and SCC as |Zs| =
Eo/Isc(for same If) A compromised value of Zs is normally estimated by taking the
ratio of (E0/Isc) at normal field current Ifn. A normal field current Ifn is one which gives rated voltage Ur on open circuit. |Zs| = Ur/Iscn
27. What are the advantages and disadvantages of estimating the voltage regulation of an Alternator by EMF method? [A]
Advantages: · Simple no load tests (for obtaining OCC and SCC) are to be conducted · Calculation procedure is much simpler Disadvantages: · The value of voltage regulation obtained by this method is
always higher than the actual value .
6.21
28. Why is the synchronous impedance method of estimating voltage regulation considered as pessimistic method? [U]
Compared to other methods, the value of voltage regulation obtained by the synchronous impedance method is always higher than the actual
value and therefore this method is called the pessimistic method. 29. In what way does the ampere-turn method differ from synchronous
impedance method? [A] The ampere-turn /MMF method is the converse of the EMF method in the
sense that instead of having the phasor addition of various voltage drops/EMFs,
here the phasor addition of MMF required for the voltage drops are carried out. Further the effect of saturation is also taken care of.
30. What are the test data required for predetermining the voltage regulation of an Alternator by MMF method? [R]
Data required for MMF method are :· Effective resistance per phase of the 3-phase winding R · Open circuit characteristic (OCC) at rated speed/frequency ·
Short circuit characteristic (SCC) at rated speed/frequency 31. Why is the MMF method of estimating the voltage regulation considered
as the optimistic method? [U] Compared to the EMF method, MMF method, involves more
number of complex calculation steps. Further the OCC is referred twice
and SCC is referred once while predetermining the voltage regulation for each load condition. Reference of OCC takes care of saturation effect. As
this method require more effort, the final result is very close to the actual value. Hence this method is called optimistic method.
32. State the condition to be satisfied before connecting two alternators in parallel [R]
The following are the three conditions to be satisfied by synchronizing the
additional Alternator with the existing one or the common bus-bars. · The terminal voltage magnitude of the incoming Alternator must be made equal to the
existing Alternator or the bus-bar voltage magnitude. · The phase sequence of the incoming Alternator voltage must be similar to the bus-bar voltage. · The frequency of the incoming Alternator voltage must be the same as the bus-bar
voltage.
33. How do the synchronizing lamps indicate the correctness of phase sequence between existing and incoming Alternators? [A]
The correctness of the phase sequence can be checked by looking at the
three sets of lamps connected across the 3-pole of the synchronizing switch. If the lamps grow bright and dark in unison it is an indication of the correctness of the phase sequence. If on the other hand, they become bright and dark one after the
other, connections to any two machine terminals have to be interchanged after shutting down the machine.
6.22
34. What are the advantages and disadvantages of three dark lamps method
of synchronizing? [E] Advantages: · The synchronous switch using lamps is inexpensive · Checking for
correctness of the phase sequence can be obtained in a simple manner which is essential especially when the Alternator is connected for the first time or for fresh operation after disconnection Disadvantages: · The rate of flickering of the lamps
only indicates the frequency difference between the bus-bar and the incoming Alternator. The frequency of the incoming Alternator in relation to the bus-bar frequency is not available.
35. How synchronoscope is used for synchronizing Alternators? [E]
Synchronoscope can be used for permanently connected Alternators where the correctness of phase sequence is already checked by other means. Synchronoscope is capable of rotating in both directions. The rate of rotation of
the pointer indicates the amount of frequency difference between the Alternators. The direction of rotation indicates whether incoming Alternator frequency is
higher or lower than the existing Alternator. The TPST switch is closed to synchronise the incoming Alternator when the pointer faces the top thick line marking.
36. Why synchronous generators are to be constructed with more synchronous reactance and negligible resistance? [A]
The presence of more resistance in the Synchronous generators will resist or oppose their synchronous operation. More reactance in the
generators can cause good reaction between the two and help the generators to remain in synchronism in spite of any disturbance occurring in any one of the generators.
37. List the factors that affect the load sharing in parallel operating generators? [K]
The total active and reactive power delivered to the load, connected across the common bus-bars, are shared among Synchronous generators, operating in
parallel, based on the following three factors · Prime-mover characteristic/input · Excitation level and · Percentage synchronous impedance and its R/X ratio .
38. How does the change in prime mover input affect the load sharing? [A] An increase in prime-mover input to a particular generator causes the
active power shared by it to increase and a corresponding decrease in active-power shared by other generators. The change in reactive power sharing is less appreciable. The frequency of the bus-bar voltage will also subjected to slight
increase in value. 39. How does change in excitation affects the load sharing? [A]
The decrease in excitation in one generator causes the reactive power shared by it to decrease and a corresponding increase in reactive-power shared
6.23
by other generators. The change in active-power sharing is less appreciable. There will be a slight decrease in terminal voltage magnitude also.
40. What steps are to be taken before disconnecting one Alternator from
parallel operation? [U] The following steps are to be taken before disconnecting one Alternator
from parallel operation
The prime-mover input of the outgoing generator has to be decreased and that of other generators has to be increased and by this the entire active-power delivered by the outgoing generator is transferred to other generators.
The excitation of the outgoing generator has to be decreased and that of other generators have to be increased and by this the entire reactive-power
delivered by the outgoing generator is transferred to other generators.
After ensuring the current delivered by the outgoing generator is zero, it
has to be disconnected from parallel operation.
41. What is meant by infinite bus-bars? [U] The source or supply lines with non-variable voltage and frequency are called infinite bus-bars. The source lines are said to have zero source impedance and
infinite rotational inertia. 42. How does increase in excitation of the Alternator connected to infinite
bus-bars affect this operation? [A] Increase in excitation level of the synchronous generator will effectively
increase the reactive component of the current supplied by the generator and hence the active power delivered.
(iii) SYNCHRONOUS MACHINES
1. What are the principal advantages of rotating field type construction? [U]
Relatively small amount of power required for field system can easily
supplied to rotating system using slip rings and brushes, more space is available
in the stator part of the machine to provide more insulation, it is easy to provide
cooling system, stationary system of conductors can easily be braced to prevent
deformation.
2. What are the advantages of salient type pole construction used in sync.
Machines? [U]
They allow better ventilation, the pole faces are so shaped radial air gap
length increases from pole center to pole tips so flux distortion in air gap is
sinusoidal so emf is also sinusoidal.
6.24
3. Which type of sync. generators are used in hydroelectric plants and
why?[U]
As the speed of operation is low, for hydro turbines used in hydroelectric
plants, salient pole type sync. Generator is used because it allows better
ventilation also better than smooth cylindrical type rotor.
4. Why the sync. Impedance method of estimating voltage regulation is
considered as pessimistic method? [U]
Compared to other method, the value of voltage regulation obtained by this.
5.Why MMF method of estimating voltage regulation is considered as
optimistic method? [U]
Compared to EMF method, MMF method involves more no. of complex
calculation steps. Further the OCC is referred twice and SCC is referred once
while predetermining the voltage regulation for each load condition. Reference of
OCC takes core saturation effect. As this method require more effort, final result
is very close to actual value, hence this method is called as optimistic method.
6. How is armature winding in alternators is different from those used in dc
machines? [R]
The armature winding of the alternator is placed in the stator, but in the
case of dc machines the arm winding is placed in the rotor.
7. What is hunting how can it be prevented? [U]
When a sync motor is used for driving a fluctuating load, the rotor starts
oscillating about its new position of equilibrium corresponding to the new load.
This is called hunting or phase swinging. To prevent hunting dampers are
damping grids are employed.
8. What is different torques of a sync motor? [R] 1. Starting torque
It is defined as angle through which the stepper motor shaft rotates for
each command pulse. It is denoted as β.
i) β=[(Ns-Nr)/ Ns.Nr]x360o ,
Where Ns = no. of stator poles or stator teeth Nr = no. of rotor poles or
rotor teeth
ii) β = 3600/mNr, Where m= no. of stator poles
6.25
PART – B
1. Explain the construction details of 3-phase IM and write its advantages. (Nov/Dec 2016) [R]
2. With neat sketches discuss about the two types of 3-phase IM. [A]
3. Derive the torque developed in 3-phase IM. (Nov/Dec 2016) [E] 4. Draw and explain the torque-slip characteristics of a 3-phase IM. [A]
5. Draw and explain the power flow diagram of a 3-phase IM. [A]
6. Develop a equivalent circuit for a 3-phase IM. (May/June 2016) [E]
7. Explain about the different types of starters in a 3-phase IM and discuss about its operation.[R]
8. Discuss the various methods of speed control in a 3-phase IM [R]
9. Derive an expression for the induced emf of an alternator [E] 10.Define voltage regulation .Explain the emf and mmf method to determine the
voltage regulation of alternators.[E]
11.Explain the construction and working of alternator (May/June 2016)[R] 12.Explain the construction and working principle of sync motor. Give the
reasons for making two different types of rotors. (April/May 2015) [R] 13.What are the advantages of having stationary armature winding in 3 phase
synchronous generator? Mention some special features of sync machine. [U]
14.Explain V-curve of synchronous motor and its applications [R] 15.Explain the various method of starting of synchronous motor and derive the
torque equation (May/June 2016) [R]
16.Explain the working of split phase capacitor start motor.(R) 17.Explain double field revolving theory of single phase induction motor
(Nov/Dec 2015) [R] 18.Explain the working principle of a 3 phase induction motor, hence derive the expression for its torque and obtain the condition for maximum torque
19. Explain various methods of starting in synchronous motors. (May/June 2016)[R]
6.26
PART-C
1.A 3 phase induction motor runs at 1140rpm at full load when supplied with power from a 60Hz,3 phase line calculate the number of poles and full load
speed, frequency of rotor voltage. (April / May 2015)[[A]
2.A 3 phase ,50Hz,20 poles salient pole alternator must be4 run at what speed if it has star connected stator winding? (May/June 2016)[A]
3.Calculate the pitch factor for the winding with 36slots 4 poles, coil span 1 to 8? (May/June 2016)[A]
4.Write down the equation of the induced emf for an alternator and calculate the same for a 3 phase,50Hz,20 poles salient pole alternator with star connected
stator winding which has 180 slots on the stator. Each slot consists of 8 conductors. The flux per pole is 25 mWb and is sinusoidal distributed. The coils are full pitch. (Nov/Dec 2015[A]
UNIT IV BASICS OF MEASUREMENT AND INSTUMENTATION PART-A
1. What is meant by measurement? [R] Measurement is an act or the result of quantitative comparison
between unknown magnitudes and the predefined standard. 2. How are the methods of measurement classified? [U]
These are two methods of measurement.
(i) Direct comparison method (ii) Indirect comparison method.
3. List out the dynamic characteristics of any measurement? [R]
1. Step response 2. Linear change 3. Sinusoidal change 4. Speed of response
5. Lag 6.Fidility
7. Dynamic error.
4. What are the types of errors in measurement? [R]
Instrumental errors, Limiting errors and Environmental errors.
5. Define a measurement system. [R]
A measurement system is defined as an assemblage of different physical
6.27
devices interconnected together to measure ,analysis and control either
electrical or non electrical quantities.
6. Define Instrument. How are the instruments classified? [R][U]
An instrument is a device for determining the value or magnitude of a quantity
or variable.
7. What are the applications of measurement system? [A]
The applications of measurement system are a) Monitoring of processes and
operations b) Control of processes and applications c) Experimental
engineering analysis
8. What are the various functional elements of a measurement system? [U] 1. Primary sensing element 2. Variable conversion element
3. Variable manipulation element 4. Data transmission element 5. Data presentation element
9. What is an absolute Instrument and secondary instrument? [R]
It measures the quantity in terms of physical contents of the Instruments. Use of this instrument is time consuming since every time measurement is made, it
takes lot of time to compute the magnitude of measurand. The secondary instruments are designed in such a manner that measure and can be measured
by observing the output indicated by the instrument. The examples of secondary instruments are voltmeter, ammeter, glass thermometer and pressure gauge etc.
10. Define the term Accuracy and precision. [R]
Accuracy is a measure of the closeness with which an instrument
measures the true value of a quantity. Precision is a measure of consistency or
repeatability of a series (successive) of measurements.
11. List the static characteristics and dynamic characteristics of
an Instrument. [R]
Static characteristic
1. Accuracy
2. Precision
6.28
3. Sensitivity
4. Resolution
5. Error
6. Range
7. Span
8. Drift
Dynamic characteristic
1. Speed of response
2. Lag
3. Fidelity
4. Dynamic error.
12. What is meant by calibration? [U]
Calibration is the process of checking the accuracy of instrument by
comparing the instrument reading with a standard or against a similar meter of
known accuracy. It is also defined as marking
the scale of an instrument.
13. What is standard and what are the types of standard? [U]&[R]
A standard is a physical representation of measurement. A known accurate
measure of physical quantity is termed as standard.
Types: 1. International standard
2. Primary standards 3. Secondary standards
4. Working standards.
6.29
14. Define dynamic response of an instrument [R]
The behavior of the instrument when inputs vary with time (i.e inputs are
dynamic in nature) and does the output, is called dynamic response of an
instrument or system. 15. What is the difference between analog and digital instruments?
(April/May 2015) [A]
16.Distinguish betweenthe direct and indirect methods of measurements.[A]
17. Define median and variance. [R] Median: The middle value of a set of an odd number of readings, if variables
are arranged in numerical order is called median.
Variance The variance is the mean square deviation, which is the same as
standard deviation, except that square root is not extracted.
V = (SD) 2
= d12+d2
2+……+dn2/n
=∑d2/n
18. Define standard deviation. [R]
The standard deviation or root mean square deviation of a sample is both
mathematically more convenient and statically more meaningful for analyzing
grouped data than is the average deviation. By definition, the standard deviation,
of a sample is given by S = ∑ (X-xi)2 /n = ∑d1
2 /n
Aspects Analog Instruments Digital Instruments
Information
form
As the position of the pointer
against a calibrated scale or dial
As a number
Human error Exists Does not exists
Accuracy +0.25% +0.005%
Construction Simple in construction Construction is
complex
S.No Direct method Indirect method
1. The unknown quantity is directly compared against a
standard
The parameter to be measured is compared with the standard
through the use of a calibrated system.
2. Less sensitive More sensitive
6.30
19. Define average deviation. [R]
The mean or average is a measure of how much the data is dispersed, or
varies from the average Value. The mean D is evaluated by adding all the
absolute values of deviations of a set of measured Values and dividing this sum
by the number of observations ‘n’.
20. Define loading effect in measurement. [R]
Loading effect of the instrument should be considered and corrections for
these effects should be made or more suitable instruments should be used.
21. Define arithmetic mean. [R]
The average value, or arithmetic mean value, is the most probable value
obtained from a series of readings of a given quantity. As a general rule, the more
readings, the more closely the computed average represents the most probable
value. The average value X is calculated by taking the sum of all the readings and
dividing by the number of readings.
23. What is the significance of calibration? [U]
All measuring instruments are to prove themselves their ability to measure
reliably and accurately. For this, the results of measurement are to be compared
with higher standards which are traceable to National or international
standards.
The calibration of a measuring instrument means introducing an
accurately known sample of the variable that is to be measured and then
observing the system’s response.
6.31
24. What is difference between accuracy and precision?[U]
25. Define error and limiting errors [R]
Error:
Error is defined as the difference between measured value and true value
Limiting errors:
Instruments having analog meters are usually guaranteed to be accurate
within certain percentage limits called limiting errors or guarantee errors.
26. Define transducer and Inverse transducer. [R]
A transducer is defined as a device that receives energy from one system
and transmits it to another, often in a different form. A transducer is general
form, may be defined as a device which converts energy from one form to another.
An inverse transducer is defined as a device which converts an electrical
quantity in to an nonelectrical quantity.
27. Mention some advantages of electrical transducer. [U] 1. Electrical amplification and attenuation can be easily done. 2. The effects of friction are minimized.
3. Mass inertia effects are minimized. 4. Very small power is required for controlling the electrical or electronic system.
28. Mention some basic requirements of a transducer. [U]
1. Ruggedness 2. Linearity 3. Repeatability
4. High output signal quality 5. Good dynamic response 6. High reliability and stability
7. No Hysteresis 8. Residual deformation
S.
No
Accuracy Precision
1. Accuracy refers to degree of
closeness of this measured value to the true value.
Precision refers to degree of
agreement Among group of readings.
6.32
29. What is the classification of transducers? [R]
The transducer can be classified (i) On the basis of transduction form used
(ii) As primary and secondary transducers (iii) As active and passive transducers (iv) As analog and digital transducers
(v) As transducers and inverse transducers 30. List out important selection of transducers. [R]
The gauge factor defined as the ratio of per unit change in resistance in per
unit change in length. Gauge factor Gf = (∆R / R) / (∆L/L)
33. What is resistance thermometer? [U]
The resistance of a conductor changes when its temperature is changed.
This properly is utilized for the Measurement of temperature. The resistance
thermometer is an instrument used to Measure electrical resistance in terms of
temperature, i.e., it uses the change in electrical resistance of the conductor to
determine the temperature.
34. What are the requirements for the resistance materials used in RTDS? [U]
The requirements for the resistance materials used in RTDS are
6.33
1. The change in resistance of material per unit change in temperature should be as large as possible.
2. The material should have a high value of resistivity so that minimum volume of material is used for the Construction.
3. The resistance of a material should have a continuous and a table relationship with temperature.
35. Mention the use of capacitive transducer. [U] 1. Capacitive transducers can be used for measurement of both linear and
angular displacements. 2. Capacitive transducers can be used for the measurement of force and
pressure.
3. Capacitive transducers are commonly used in conjuction with mechanical modifiers for measurement of volume, density, liquid level, weight etc.
36. What is the principle of piezoelectric transducers and name any two
piezoelectric materials. [U]
The piezo electric materials are i) Ammonium dihydragen phosphate ii)
Rochelle salt
37. What is piezoelectric effect? (April/May 2015) [U]
A piezo electric material is one in which an electric potential appears across
certain surfaces of a crystal If the dimensions of the crystal are changed by the
application of a mechanical force. This potential is produced by the displacement
of charges. The effect is reversible also i.e if a varying potential is applied to the
proper axis of the crystal. It will change the dimensions of the crystal there by
deforming it. This phenomenon is known as piezoelectric effect.
38. Give the factors to be considered for selecting a transducer. [R]
a) Physical quantity to be measured
b) Appropriate transducer principle is to be used for the given physical
quantity. c) Order of accuracy needed.
39. What are the active transducers? Give an example.[R]&[AP]
An active transducers generates an electrical signal directly in response to the
physical parameter and does not require an external power source for its
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operation. Such transducers draw energy from the system under measurement.
Active transducers are also called self generating type transducers.
e.g Tacho-generators used for measurement of angular velocity . 40. What are the passive transducers? Give an example.[R]&[A]
Transducers, in which electrical parameters i.e. resistance, inductance or
capacitance changes with the change in input signal, are called the passive
transducers. These transducers require external power source for energy
conversion. These transducers may draw some energy from the system under
measurement. Typical examples are strain gauges, thermistors etc.
41. Define scale factor. [R]
Scale factor is the inverse of sensitivity. It is defined as the ratio of the change
in the input to change in the output.
42.Define sensitivity of a transducer. [R]
Sensitivity of a transducer is defined as the change in the ratio of the output
quantity to the change in the input.
43. Define analog transducer. [R]
Analog transducer converts input signal in to output signal, which is a
function of time such as thermistor, Strain gauge, LVDT, thermocouple.
44. Define sensing element and transduction
element. [R]
Sensing element:
Sensing element is used to sense or direct any change in the quantity that is
being Measure makes an appropriate change in its output.
Transduction element: Transduction element transforms the output of a sensing element in to an
electrical signal.
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PART-B 1. Describe in detail the basic elements of a generalized measurement system
with examples. [R][A] 2. Explain in detail Time domain analysis in dynamic analysis of measurement
system. [U] 3. Explain the static characteristics of a measuring instrument. [U] 4. What are the Dynamic characteristics of a measuring device? Explain them.
[U] 5. Define static error and discuss the types of error occurring in measuring in
device. [R]
6. Describe in detail about standards and its types. [R] 7. Describe in detail about calibration and methods of calibration. [R]
8. a) Explain the advantages of electronic instrument. b)The table is given below lists a sample of experimental data.
Calculate a) Mean b) Mean deviation c) Standard deviation d) Variance e)
Probable error of one reading f) Probable error of mean [E]
9. The following values are obtained from the measurement values of 147.2, 147.4, 147.9, 148.1, 147.7, 147.5, 147.6, 147.4, 147.6 & 147.5. Calculate: a) the
arithmetic mean b) standard deviation c) The probable error of the ten readings [E]
10.Define the following terms in the context of normal frequency distribution of data. a) Mean value b) Deviation c) Average deviation d) Variance e) Standard deviation [R]
11.If a set of six observations are as follows: 1.5V, 3V, 1V, 5V,2V, 4V. Calculate
the arithmetic mean, average deviation and standard deviation. [E] 12.a) Why feedback is necessary in instrumentation systems? b) Explain the
significance of negative feedback? c) If the rms value of reading in volts is observed in a digit CRO were 3,5, 3.452, 3.620, 3.523. [E]
13. Discuss the types of systematic error with suitable examples. [A]
14. Explain the essential requirements of measuring instruments. [U] 15(i) Explain the resistive transducer with respective to potentiometer. ii) Explain
the capacitive transducer. iii) Describe the piezoelectric transducer and give the formula for coupling co-efficient. [R]
Value 3 4 5 6 7 8 9 10 11
Measurement
number
1 2 3 6 7 6 4 2 1
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16.(i) Explain the different selection criteria for the transducer. ii) Write a note an inductive transducer and piezoelectric transducer. (May/June 2016) [R]
17.(i) Write briefly on thermocouples and thermistors as temperature
transducers. ii) With neat figure explain LVDT for velocity measurement.[U] 18. Describe the methods of measurement of pressure using (1) Capacitive
transducers (2) Photoelectric transducer [R]
19. Briefly explain the principle of working of variable area capacitive transducer.
What are the advantages and disadvantages? (Nov/Dec 2016)[R] 20. Explain the construction and principle of working of a RVDT.
(Nov/Dec2015)[R]
PART - C
1. How are the various transducer classified? Summarize the various errors you
encounter in measurement. (May/June 2016) [R]
2. Explain the construction and principle of working of a LVDT. (Nov/Dec 2015)[R]
3. Write short notes on capacitor Microphone. (Nov/Dec 2016)[A]
4. Compare the features of RTD, Thermocouple and thermistor.
(Nov/Dec 2016)[A]
UNIT V ANALOG AND DIGITAL INSTRUMENTS
PART-A
1. What is creeping in an Energy meter? [U]
A slow but continuous rotation of the energy meter disc even when there is
no current flowing through the current coil but only the pressure coil is
energized, current coil is not energized.
2. State the principle of ramp type digital voltmeter. [R]
Ramp type DVM works on the principle of comparison of unknown voltage
with the ramp signal and by counting the number of pulses passing through till
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both the voltages become equal. This number of pulse will give the direct
indication of the voltage.
3. How a PMMC meter can be used as Voltmeter and Ammeter? [U]
When a shunt resistance is connected across the basic PMMC meter then it
will act as a DC ammeter and when a resistance is connected in series with the
basic PMMC meter then the meter will act as a DC Voltmeter.
4. What is Instrument Transformer and mention its classifications? [U][R]
The transformers used in conjunction with the measuring instruments for
measuring very large values of current or voltage which cannot be directly
measured are called instrument transformers are called instrument transformer.
i) Current Transformer ii) Potential Transformer / Voltage Transformer
5. What is a transfer Instrument? [R]
A transfer instrument is one that may be calibrated with a d.c source and
then used to measure a.c without any modification.
6. What is Auto ranging? [R] Auto ranging is the process of changing the range of the digital voltmeter for getting a reading with the optimum resolution under all the circumstances.
7. What is the reason for using Moving Iron instruments on both AC and
DC? [U]
Moving Iron instruments can be used for both a.c and d.c and d.c
measurements because, whatever may be the direction of the current through the
coil in the instrument, the iron values get magnetized and there will be a force of
attraction in the attraction type instrument and will be a force of repulsion type
instrument.
8. Why the PMMC instruments are not used for AC measurement? [U]
When the PMMC instruments are connected to A.C, the torque reverses as
the current reverses And the pointer cannot follow the rapid reversals. Hence the
deflection corresponding to mean torque is zero thus making the PMMC
instrument not suitable for a.c measurements.
9. State the advantages of PMMC instruments [U]
1. Low power consumption in the order of 25µw to 200µW. 2 High torque
weight ratio which in turn gives high accuracy. 3. Sensitivity is high. 4. Not
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affected by the external magnetic fields called stray magnetic fields because of
high flux density. 5. Instrument is free from hysteresis error. 6. It is a uniform
scale. 7. Effective damping is provided because of eddy current.
10. Define resolution of DVM. [R]
Resolution of DVM is given by, R = 1/10n
Where, R = resolution of DVM N = number of full digits in a digital display for a
41/2digit display, n = 4 and hence R = 1/104 = 0.0001 or 0.001%
11. What is volt ampere hour and watt-hour [U]
Volt ampere hour is the reactive power consumed by the load where watt-
hour is the real power consumed by the load.
12. How to evaluate phase angle error instrument transformer? [U]
The main condition to be satisfied by the instrument transformer is that
the phase angle of the Secondary parameter (V or I) must be displaced exactly by
180° from that of primary parameter (V or I) this condition is not satisfied, heavy
phase angle error occur in the measurement using instrument transformer.
Hence the phase angle error should be reduced to minimum and its value
Should be evaluated and induced in the measuring quantity to get highly
accurate measurement.
13. What is the purpose of Instrument transformer? [U]
This transformer used in conjunction with the measuring instruments for
measuring very large of current or voltage which cannot be directly measured
are called instrument transformer.
14. What are the types of digital voltmeters? [R]
a) Servo potentiometric type DVM b) Successive approximation c) Linear
ramp type DVM d) Staircase ramp type DVM e) Dual slope integrating type
DVM
15. Define nominal ratio of the Transformer. [R]
Nominal ratio Kn = rated primary current / rated secondary current for C.T
and Kn = rated primary voltage / rated secondary voltage for P.T
16. What are the essential parts of a ramp type digital voltmeter? [R]
17. Why it is necessary to make the potential coil circuit purely resistive in wattmeter? [U]
The inductance of the potential coil can cause error in wattmeter
instrument. Hence the inductance of the potential coil is compensated by a
capacitance thus making the potential coil circuit purely Resistive in nature. 18. How are the resistors checked using digital multi-meters? [R] For the measurement of various ranges of resistances, ohms convertor is used
which is nothing but a low current source. A known current from the low current
source is passed through the unknown Resistance and the voltage drop across
the resistance is measured. This voltage drop gives the direct indication of the
unknown resistance.
9. What are the advantages of digital instruments over analog instruments? (NOV/DEC2016)[R]
(i) Highly accurate reading can be taken (ii) Better resolution
(iii) High input impedance (iv) Digital display eliminates observational errors, interpolation errors and parallax errors committed by operators
(v) Reading speed is very high. (vi) Digital output can be directly recorded
(vii) The development of IC chips has reduced the cost, size and power requirement o DVM.
(viii) Portable
(ix)They can be used for the measurement of quantities like current,
impedance, capacitance, Temperature, pressure etc.
20. What are the different methods of measurement of frequency in the
power frequency range? [R]
(i) Mechanical resonance type/vibrating reed type frequency meter (ii) Electrical resonance type/Ferro dynamic type frequency meter (iii) Weston type frequency meter
21. What is the precaution to be followed while using current transformer?
[U]
The main precaution to be followed in a C.T is that the secondary winding of C.T
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should never be Open circuited while its primary winding is energized. Either it
can be short circuited or connected in series with the low resistance coil such as
coil of ammeter, current coil of wattmeter, relay coil etc.
If the secondary winding of C.T is open circuited while the primary winding
is carrying current, a very high voltage will be induced the secondary winding
which can be damaged the transformer insulation.
22. Explain the purpose of Schmitt trigger in digital frequency meter [R]
In a digital frequency meter, Schmitt trigger is connected between amplifier
and a gate and is used to convert the analog voltage from the amplifier to train of
pulses which is fed to the gate.
23. Explain the principle of digital phase meter. [R]
When two signals of same frequency, whose phase difference is to be
measured, are applied to the phase meter, the signals are converted to a square
waveform without changing the phase relationship using two Separate
preamplifier and attenuator block. The converted square pulses are fed to the
flip-flop.
The function of the two flip-flop is that, one flip-flop enables the AND gate
while the other disables it. The number of pulses allowed to pass during enabling
and disabling the gate are counted which is proportional to the phase difference
between the two signals.
24. Which torque is absent in energy meter? Why? [U]
In energy meter, there is no controlling torque, as the driving torque alone is
enough to cause continuous revolution of the disc.
25. Explain the term as applied to digital displays 3 ½ digits and 4 ½ digit
displays. [R]
The 3 ½ digit display has 3 full digits and one half digit whereas 4 ½ digit
display has 4 full digit and one half digit. Resolution of 3 ½ digit display is 0.1%
whereas resolution of 4 ½ digits display is 0.01%
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26. What is Potentiometer? [R]
A potentiometer is an instrument designed to measure an unknown voltage by
comparing it with a known voltage.
27. List the applications of DC potentiometer. [AP]
Measurement of small emf (up to 2V)
Comparison of emf of two coils.
Measurement of high emf (up to 250V)
Measurement of resistance
Measurement of current
Calibration of ammeter
Calibration of voltmeter.
28. List the applications AC potentiometer. [AP] 1. Measurement of self inductance 2. Calibration of ammeter
3. Calibration of Voltmeter 4. Calibration of wattmeter.
29. What are the types of DC potentiometer? [R] 1. D.C potentiometer 2. A.C potentiometer
30. What is a Bridge Circuit? What are the types? [R]
A bridge circuit in its simplest form consists of a network of four resistance
arms forming a closed circuit with a D.C source of current applied to two opposite
junctions and a current detector connected to the other two junctions.
31. What are the uses of bridge Circuit? [U]
The bridge circuits are mainly used for measuring unknown quantities
such as resistance, inductance and capacitance.
32. List the few applications of Wheatstone bridge Circuit. [AP] 1. To measure the DC resistance of various types of wire either for the purpose of
quality control of the wire itself, or of some assembly in which is used. 2. This bridge is also used extensively by telephone companies and others to
locate cable faults.
33. What are the advantages of bridge circuit? [U] 1. High measurement accuracy
2. The accuracy is independent of null detectors characteristics.
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3. The balance equation is the independent of the magnitude of the input voltage or its source impedance, the sensitivity and impedance of the null detector or
any impedance shunting the detector.
35. What is meant by transformer ratio Bridges? [R]
The transformer ratio bridges are popular one. These bridges are mainly
used for wide range of applications. The transformer ratio bridges are replacing
the conventional AC bridges.
36. List the applications of ratio transformer ratio bridge.[R]
1. It can be used for measurement of resistance, capacitance and inductance in
comparison with standard resistance, standard capacitance and standard
inductance respectively. 2. It can be used for measurement amplifier gain and phase shift 3. It is also used for measurement of transformer ratios.
37. What are the features of transformer ratio bridge? [U] 1. It can be used only in ac.
2. It gives very small ratio errors 3. This transformer ratio has high input impedance and low output impedance.
Due to this loading effect is very small.
4. The frequency range is from 50Hz to 50 kHz
38. What is a Wheatstone bridge? [U]
Wheatstone bridge is used for measurement of medium resistance in the
range of 1Ω to 100kΩ
39. What are the sources of error in bridge measurement? [U]
a) Errors due to stray field effects b) Leakage errors c) Eddy current errors d)
Residual errors e) Frequency and waveform errors
40. What is Kelvin Bridge? [R]
Wheatstone bridge is not suitable for measurement of very low resistance.
Kelvin’s bridge is a modification of Wheatstone bridge and is used to measure the
values of resistance below 1Ω
41. What is electromagnetic interference in instrument? [R]
If the parameter to be measured is at the place at which a measurement is to
be displayed or used for control purposes is at some distance from the point of
measurement, then it can lead to various problems. The main one is electrical
6.43
noise or interference being superimposed on the Measurement signal. This is
called electromagnetic interference.
42. What is Kelvin’s double bridge? [R]
The circuit consists of double bridge, because it incorporated a second set of ratio
arms. This circuit is mainly used for measuring very low resistances from 1Ω to
0.00001Ω.
43. What is Maxwell’s bridge? [R]
The Maxwell bridge or Maxwell-Wien bridge is used to measure both a given
inductance (with a between 1 and 10) and its series resistance by comparison to
a standard capacitance. Using a Capacitance as a standard offers several
advantages. Capacitors are easy to shield and they produce almost no external
field of their own. In addition, they are compact and fairly expensive.
44. State the advantages and disadvantages of
Anderson Bridge.[U]
Advantages: 1. This bridge may be used for accurate determination of capacitance in terms of
inductance.
2. A fixed capacitor can be used instead of variable capacitors in the case of Maxwell’s bridge.
3. It is much easier to obtain balance in case of Anderson’s bridge than in
Maxwell’s bridge for low coils.
Disadvantages: 1. The Anderson’s bridge is more complex than the prototype Maxwell’s bridge. 2. An additional junction point increases the difficulty of shielding the bridge.
PART-B 1. Explain voltage sensitive self balancing bridge, and derive the bridge
sensitivity of voltage sensitive Bridge with fundamentals. [R]
2. Explain the construction and working of digital millimeter with all the self diagnostic features. (April/May 2015)[U]
3. Explain in detail the measurements that are made in the following circuits. [U] i) Wheatstone bridge ii) Deflection type bridge
6.44
4. (i) Explain in detail about the laboratory type DC potentiometer. ii) Give the applications of AC potentiometer.[R]& [A].
5. Derive the bridge balance equation of Schering Bridge?(April/May 2015)[AZ]
6. Discuss in detail i) Bridge to measure low-Q of a coil. ii) Cause and effects of poor grounding in instruments.[U].
7. Describe the circuit of Kelvin Double bridge used for measurement of low resistance, derive the Conditions for balance. (April/May 2015) [U]
8. Explain how self inductance can be measured in terms of a standard capacitor
using an AC Bridge and give the detectors commonly used in AC Bridge. [U]
9. (i) With a diagram explain in detail about Hays bridge. ii) Explain how to determine frequency using Wien bridge with neat circuit diagram.[R] [U]
10 Draw the circuit diagram and phasor diagram for Anderson Bridge. Derive the expression for Unknown inductance. [E].
11. The four arms bridge ABCD, supplied with a sinusoid voltage, have the following values.
AB = 330Ω resistance in parallel with 1.5μf capacitor BC = 400Ω resistance
CD = 800Ω resistance; DA resistance R in series with a 0.2μf capacitor.
Determine the (i) value of R and (ii) Supply frequency at which the bridge will
be balanced. [E]
12. Discuss in detail about electrostatic and electromagnetic interference, and
grounding techniques. [R]
13.A Maxwell’s bridge used for measurement of inductive impedance consists of
following components as shown. Find the series equivalent of unknown
impedance. Lx, Rx. [E]
PART-C
1.Explain the working of ramp type digital voltmeter . (April/May 2015)[U]
2.What resistance range must resistor R3 have in order to measure unknown resistor in the range of 1-100kΩ using a Wheatstone bridge? Given R1=1KΩ and
R2=10KΩ. (NOV/DEC2016)[A] 3.(i)A Maxwell bridge is used to measure an inductive impedance. The bridge
6.45
constants at the balance are, C1=0.02μF; R1=510KΩ;R2=4.7KΩ and R3=120KΩ.Find the series equivalent of
unknown impedance.
(ii)Find the equivalent parallel resistance and capacitance that causes a wien bridge to null with the following component values.R1=2.7KΩ;C1=5μF;R2=22KΩ;R4=100KΩ.The operating frequency is 2.2kHz
