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Parallel I/O Parallel I/O
Parallel I/OParallel I/O
Introduction
o This section focuses on performing parallel input and output operations on the 68HC11
o 3 operation typeso Simple, blind data transfers
o Strobed transfers
o Transfers with handshaking
o Look at examples of each transfer operation
Contd…
SEGMENT code
Introduction
o Reading:o Text, Chap 9:
o Read: 9.1, 9.4-9.8.1o Scan: 9.2, 9.3
o E9: Section 6
77
Recall the block diagram of the
68HC11
Simple I/O operationsSimple I/O operations
o These I/O operations take place under the direction of the processor
o Operations are performed without regard to the status of the I/O portthe port is always assumed to be "ready"
Contd…
Simple I/O operationsSimple I/O operations
o Since the current status of the port is not known, it is possible too Read the same value in more than once
on input operationso Overwrite the current value in an output
port that is waiting to be transferred
o "Good" examples of use:o Input initialization values from a port port
is in known state as a result of system reset
o I/O when overwrites or multiple reads don't matter writing to the hex display’s port in the labs, for example
Simple I/O operationsSimple I/O operations
Simple I/O example -- keypad interface
Consider the simple 12-key keypad shown below
Simple I/O operationsSimple I/O operations
Simple I/O example -- keypad interface
Consider the simple 12-key keypad shown below
Simple I/O operationsSimple I/O operations
o High-level procedure to detect key closureso Drive Row 1 input lowo Read Columns -- any =0?o Repeat this process for all remaining rows
until “see” a column=0o If no column=0, then no key has been
depressed
Simple I/O operationsSimple I/O operations
o Knowing which row and column were low permits you to calculate the key number that was pressedo Can use a simple equation (similar to the
approach of Listing 9.5)o Key# = col# + (3*row#) -3o Assumes row and col numbers start with 1o Listing 9.5 is for 2-of-7 keyboard!
o Or use a lookup table (similar to the approach in Listing 9.10)
o – Assumes row and col use same port (port C)
Simple I/O operationsSimple I/O operations
o Key debounceo Need to avoid the multiple make/break
closures associated with key bounceo “Simple” approach is ID the key closed
and then wait for a period of time to see if the key is still closed (therefore not bouncing)
o Then and only then, return the key valueo The waiting period will vary from switch
to switch -- 10s to 100s of ms
Simple I/O operationsSimple I/O operations
o How will the system react if you hold a key down for a long time?o Should an action (in response to a key
closure) be repeated over and over despite there being only 1 switch closure “action”
o Should the action take place only once and then wait for the key “break” before recognizing another closure?
o Consider routines to recognize key makes and breaks
Strobed I/OStrobed I/O
o This method of performing I/O operations uses a control line, the strobe, to notify the receiving unit of the availability of data at its (input) port
o The process:o Device performing the write places data
onto data bus (its output port)o Strobe signal is asserted (for 2 cycles in
68HC11)o Strobe signal causes data to be latched into
input port of the receiving device
Contd…
Strobed I/OStrobed I/O
o Strobe signal causes an I/O interrupt to occur or a flag to be set -- in either case the receiving device is signaled that new data has arrived
o It is up to the receiving device to read the new data at its input port in a "timely" fashion
o Problemo If a second data item arrives at the input
port and is strobed in (latched) before the input device has read the first item, the first item will be overwritten and lost
Strobed I/OStrobed I/O
o 68HC11 register support for strobed I/Oo DDRC -- data direction register for port Co PORTCL -- port C input latch -- data is
latched on STRA edgeo PORTC -- input pins for port C -- not
latchedo PORTB -- latched output data port B –
outputs data using STRBo PIOC -- parallel I/O control registero PORTD -- bits 6 and 7 are STRA and STRB
Contd…
Strobed I/OStrobed I/O
Strobed I/OStrobed I/O
o Strobed input operations using port Co Data is placed at the input pins of port Co STRA is asserted by peripheral device,
causingo Data to be latched into PORTCLo STAF flag to be assertedo Interrupt initiated, if interrupts are enabled
o Data is read into to processor from PORTCL
o To clear STAF, read PIOC first then PORTCL
Strobed I/OStrobed I/O
Strobed I/OStrobed I/O
o Strobed Outputo Peripheral device is connected to Port Bo When the MCU writes to Port B, . . .
o Data is placed on Port B pinso STRB is asserted for 2 clock cycles
o Peripheral device should use STRB to latch the data
o STRB can be configured as active-high or active-low
Handshaking I/OHandshaking I/O
o In this mode, the sending and receiving devices exchange positive sent/received signals to one anothero Insures that each
transmitted word is received before the next word is transmitted
Handshaking I/OHandshaking I/O
o Transfers can occur in either the pulsed or the interlocked methodo Pulsed input operations
o Peripheral pulses STRA to indicate that data is present
o When 68HC11 reads the data (from PORTCL), it automatically generates an acknowledgment strobe on STRB for 2 cycles
o This mode is selected by initializing the PLS bit (bit 2 of the PIOC) to 1
Handshaking I/OHandshaking I/O
o Transfers can occur in either the pulsed or the interlocked methodo Interlocked input operations
o Here, STRB acts as a READY signalo Asserted = 68HC11 ready to receive datao Negated = 68HC11 is not ready -- do not send
data now
Handshaking I/OHandshaking I/O
Handshaking I/OHandshaking I/O
o Output operations with handshakingo Port C is used for output handshake operations,
along with STRB and STRAo – STRB is the output "data available" strobeo – STRA is the acknowledgment / input ready
strobe lineo PIOC bit 3, OIN, set to 1 for output operationso Pulsed operations
o 68HC11 writes data to PORTCL and automatically asserts STRB for 2 cycles
o Peripheral device reads data upon receipt of the STRB strobe
o Peripheral asserts its READY line (68HC11's input STRA line) to signal receipt of data
o PIOC bit 2, PLS set to 1 for pulsed mode
Handshaking I/OHandshaking I/O
o Output operations with handshakingo Interlocked mode
o Upon writing data to PORTCL, STRB is assertedo STRB negated only upon ACK
Handshaking I/OHandshaking I/O
Handshaking I/OHandshaking I/O
o Handshaking example:Centronics parallel printer interfaceo The "Centronics"
definition of a printer port interface has become the standard parallel printer interface
Handshaking I/OHandshaking I/O
o Using the 68HC11 as the output device (to the printer) requires a software interface (note the errors in the text!)
Handshaking I/OHandshaking I/O
Handshaking I/OHandshaking I/O
Handshaking I/OHandshaking I/O
; Listing 9.16; I/O service routines to control "Centronics" interface; part of printer control system. Also demonstrates; software handshaking because port C configured; for simple input strobe. Main program would call; service routines to store input data in a RAM print; buffer for later output to print mechanism.;;;CONNECTIONS; Computer Printer Port MCU as Printer Controller; DATA -----------------> Port C; STB -----------------> STRA; ACK <----------------- PD2; BUSY <----------------- PD3;;
Contd…
Handshaking I/OHandshaking I/O
PIOC CONFIGURATION DETAILS; INVB=x STRB not used; EGA=0 STRA/ACK active on falling edge; PLS=x Pulsed/Interlocked not used; OIN=x Output/input handshake not used; HNDS=0 Simple strobe mode; CWOM=0 Normal CMOS outputs; STAI=0 Disable interrupt; STAF=x Sets on falling STRA line; To clear STAF, read PIOC, then read PORTCL
Contd…
Handshaking I/OHandshaking I/O
ORG $100; Subroutine INIT_INTRF; Initializes parallel interface part; of printer upon power-up reset.; Calling Registers:; IX = Address of register block; No Return Registers except CCR affected
Contd…
Handshaking I/OHandshaking I/O
INIT_INTRF:psha ; preserve registersldaa PIOC,X ; clear STAF if setLdaa PORTCL,Xbset PORTD,X $0C ; PD2, 3 output andbset DDRD,X $0C ; BUSY, ACK high
ldaa #00 ; configure PIOCstaa PIOC,Xpula ; restore registersrts ; and return
Contd…
Handshaking I/OHandshaking I/O
; Subroutine INPUT; Reads parallel port to get byte sent; by an external device; Calling registers; IX = Address of register block; Return registers; ACCA = input data byte; CCR affected
Contd…
Handshaking I/OHandshaking I/O
INPUT: bclr PORTD,X $0C ; BUSY low and pulse ACK nop ; for approx 5 us (E=2MHz) bset PORTD,X $04 ; set ACK high againCIN: brclr PIOC,X $80 CIN ; wait for STB pulse
ldaa PORTCL,X ; get input and clear STAF bset PORTD,X $08 ; set BUSY high rts ; return
ParallelParallelsubsystem summarysubsystem summary
o Ports B and C are available for I/O only in the single chip mode -- can be replaced by the PRU when in expanded mode
o Port Ao 3 input, 3 output, 2 bi-directional pinso Bits DDRA7 and DDRA3 in PACTL set
direction for A7 and A3
o Port Bo Parallel output only (single chip mode)
Contd…
ParallelParallelsubsystem summarysubsystem summary
o Port Co Data register is PORTCo Latched register is PORTCLo Each bit is bi-directional
o Direction set using register DDRC
o Port Do 6 bi-directional pins, directions set by
DDRDo Pin 6 = STRA, Pin 7 = STRB
o These pins become AS and R/W* in expanded multiplexed mode
Contd…
ParallelParallelsubsystem summarysubsystem summary
o Port Eo 8-bit input only
o Conditions on reseto All data direction bits set to 0 (input)o Output port bits set to 0o Input port bits high impedance
Contd…
ParallelParallelsubsystem summarysubsystem summary
o Strobed I/Oo Strobed output via Port B, strobed input
via Port Co Detected edge on STRA causes input data
to be latched in PORTCL and flag set (and interrupt, if enabled)
o Writing data to Port B also pulses STRB
o Handshake I/Oo Port C used for either input or output
operationo Input: read data from PORTCLo Output: write data to PORTCL
