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Parking Pal Presentation #5 Team M1: Anna Kochalko Chris Moody Hong Tuck Liew John Wu Team TA: Kartik Murthy October 3, 2007 Gate Level Verilog Your digital parking meter of the future!
Parking PalPresentation #5
Team M1:Anna Kochalko
Chris MoodyHong Tuck Liew
John WuTeam TA:
Kartik Murthy
October 3, 2007Gate Level Verilog
Your digital parking meter of the future!
Status
Project Chosen Options explored and eliminated
Wrote Java Implementation Specification defined Verilog obtained/modified Test Benches Schematic Design Layout Simulations
The Big Picture
Mult/adderCar
~rate
60 currentTime
min hrs
TeaEncryption
Binary to BCD
Main Mux (MM)
AdderSubtractor
Compare(max)
(realTimeIn)
/11 /11
/11
/6 /6/7
MMMM
ticketTime
/11
getTicketID #
0
0
realTimeIn
timeLimittimeInMin
0
7SegmentDisplay
FlashMemory
Chargerate TimeLeft
/11
/1
/20
/1/11/11
/11
/7
BLOCK DIAGRAM
startTime
timeIn
reg
Car swipeIn
getID
Write_en
timeInMin
Charge
getCharge(SRAM)
start
/1
/12rate
0TL2
TL2[10]
TL2[10]
1 0
F(currentdate)
addresses
noCar10Min
swipeOutnoCar
getTicket/1
10
timeLimit
FLOORPLAN
Metal Layer Usage In Components
BCD (2 Metal layers – M1,M2) Encryption(4 Metal layers – M1,M2,M3,M4) – no
over routing Multiplier(3 Metal layers- M1, M2, M3) Adder/ Subtractor (2 Metal layers – M1,M2) Comparator (2 Metal layers – M1, M2) SRAM (4 layers – M1, M2) Muxes (2 layers – M1, M2)
JOHN AND ANNA
Mult/adderCar
~rate
60 currentTime
min hrs
TeaEncryption
Binary to BCD
Main Mux (MM)
AdderSubtractor
Compare(max)
(realTimeIn)
/11 /11
/11
/6 /6/7
MMMM
ticketTime
/11
getTicketID #
0
0
realTimeIn
timeLimittimeInMin
0
7SegmentDisplay
FlashMemory
Chargerate TimeLeft
/11
/1
/20
/1/11/11
/11
/7
Who’s Doing What?
startTime
timeIn
reg
Car swipeIn
getID
Write_en
timeInMin
Charge
getCharge(SRAM)
start
/1
/12rate
0TL2
TL2[10]
TL2[10]
1 0
F(currentdate)
addresses
noCar10Min
swipeOutnoCar
getTicket/1
10
timeLimit
ANNA
JOHN
CHRIS
LIEW
LIEW AND CHRIS
Gate Level Verilog (portion of Multiplier)
module multiplier6X5 (sixty, hours, hoursInMin); input [5:0] sixty; input [4:0] hours; output [10:0] hoursInMin;
and andx0(hoursInMin[0], hours[0], sixty[0]); and andx1(x1, hours[0], sixty[1]); and andx2(x2, hours[0], sixty[2]); and andx3(x3, hours[0], sixty[3]); and andx4(x4, hours[0], sixty[4]); and andx5(x5, hours[0], sixty[5]);
HalfAdderWithAndHA1(.A(sixty[0]), .B(hours[1]), .sumPrev(x1), .Cout(x10), .Si(hoursInMin[1]));
FullAdderWithAnd FA1(.A(sixty[1]), .B(hours[1]), .sumPrev(x2), .Ci(x10), .Cout(x11), .Si(y1)); FullAdderWithAnd FA2(.A(sixty[2]), .B(hours[1]), .sumPrev(x3), .Ci(x11), .Cout(x12), .Si(y2)); FullAdderWithAnd FA3(.A(sixty[3]), .B(hours[1]), .sumPrev(x4), .Ci(x12), .Cout(x13), .Si(y3)); FullAdderWithAnd FA4(.A(sixty[4]), .B(hours[1]), .sumPrev(x5), .Ci(x13), .Cout(x14), .Si(y4)); HalfAdderWithAnd HA2(.A(sixty[5]), .B(hours[1]), .sumPrev(x14), .Cout(x15), .Si(y5));
Multiplier Verilog Output
Loading snapshot worklib.testMult:v .................... Done ncsim> source /usr/cds/ldv-4.1/tools/inca/files/ncsimrc ncsim> run 0 sixty=111100, hours= x, hoursInMin= X, hoursInMin=xxxxxxxxx00 10 sixty=111100, hours= 4, hoursInMin= 240, hoursInMin=00011110000 20 sixty=111100, hours=10, hoursInMin= 600, hoursInMin=01001011000 30 sixty=111100, hours= 0, hoursInMin= 0, hoursInMin=00000000000 40 sixty=111100, hours=24, hoursInMin=1440, hoursInMin=10110100000 50 sixty=111100, hours= 5, hoursInMin= 300, hoursInMin=00100101100 60 sixty=111100, hours= 6, hoursInMin= 360, hoursInMin=00101101000 70 sixty=111100, hours= 7, hoursInMin= 420, hoursInMin=00110100100 80 sixty=111100, hours= 8, hoursInMin= 480, hoursInMin=00111100000 90 sixty=111100, hours= 9, hoursInMin= 540, hoursInMin=01000011100 100 sixty=111100, hours=10, hoursInMin= 600, hoursInMin=01001011000 110 sixty=111100, hours=11, hoursInMin= 660, hoursInMin=01010010100 120 sixty=111100, hours=12, hoursInMin= 720, hoursInMin=01011010000 130 sixty=111100, hours=13, hoursInMin= 780, hoursInMin=01100001100 Simulation complete via $finish(1) at time 180 NS + 0 ./multiplier.v:87 $finish; ncsim> exit bash-2.05a$ bash-2.05a$
Encryption (main module) module encryptor(v,k,c,o); input [31:0] v; input [63:0] k; input c; output [31:0] o;
wire ci; wire [15:0] sum,delta; wire [15:0]
v1,v2,k1,k2,k3,k4,s1,s2,s3,s4,s9,s6,s7,s8,s5,o1,o2,o3,o4,x1,x2;
assign v1 = v[15:0]; assign v2 = v[31:16]; assign k1 = k[15:0]; assign k2 = k[31:16]; assign k3 = k[47:32]; assign k4 = k[63:48]; assign ci = 0; assign sum = 16'h0; assign delta = 16'h9e37;
cla16b_adder g1(sum,delta,ci,s1,co1), g4(o1,k1,ci,s2,co2), g5(o2,k2,ci,s3,co3), g6(v2,s1,ci,s4,co4), g7(v1,x1,ci,s5,co5), g11(o3,k3,ci,s6,co6), g12(o4,k4,ci,s7,co7), g13(s5,s1,ci,s8,co8), g15(v2,x2,ci,s9,co9);
xor_16b g8(s2,s3,s4,x1), g14(s6,s7,s8,x2);
lshift4_16b g2(v2,c,o1), g9(s5,c,o3);
rshift5_16b g3(v2,c,o2), g10(s5,c,o4);
assign o[15:0] = s5[15:0];assign o[31:16] = s9[15:0];
endmodule
module overallTea(v,k,c,r,start,o); input [31:0] v; input [63:0] k; input c,r,start; output [31:0] o;
wire [31:0] q,f,out; encryptor e1(f,k,c,out); dff16b r1(q,out,c); mux32b m1(f,start,v,q), m2(o,ecout,0,out); control_16 c1(c,r,ecout);
endmodule
Verilog Output(Encryption) ncsim> source /usr/cds/ldv-5.1/tools/inca/files/ncsimrc ncsim> run 0 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=xxxxxxxx 1 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=xxxxxxxx 2 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=xxxxxxxx 3 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=xxxxxxxx 4 c1=0,c2=1,v=beefdeaa,k=00d400c300b200a1,o=d7c592c8 5 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=d7c592c8 6 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=d7c592c8 7 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=d7c592c8 8 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=d7c592c8 9 c1=0,c2=1,v=beefdeaa,k=00d400c300b200a1,o=ee31027a 10 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=ee31027a 11 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=ee31027a 12 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=ee31027a 13 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=ee31027a 14 c1=0,c2=1,v=beefdeaa,k=00d400c300b200a1,o=4cf225be 15 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=4cf225be 16 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=4cf225be 17 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=4cf225be 18 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=4cf225be 19 c1=0,c2=1,v=beefdeaa,k=00d400c300b200a1,o=98eb2ed4 20 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=98eb2ed4 21 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=98eb2ed4 22 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=98eb2ed4 23 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=98eb2ed4 24 c1=0,c2=1,v=beefdeaa,k=00d400c300b200a1,o=bc9254aa 25 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=bc9254aa 26 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=bc9254aa 27 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=bc9254aa 28 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=bc9254aa 29 c1=0,c2=1,v=beefdeaa,k=00d400c300b200a1,o=b9931335 30 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=b9931335 31 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=b9931335 32 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=b9931335 33 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=b9931335 34 c1=0,c2=1,v=beefdeaa,k=00d400c300b200a1,o=5a44a5f0 35 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=5a44a5f0 36 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=5a44a5f0 37 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=5a44a5f0 38 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=5a44a5f0 39 c1=0,c2=1,v=beefdeaa,k=00d400c300b200a1,o=02be9289 40 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=02be9289
41 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=02be9289 42 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=02be9289 43 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=02be9289 44 c1=0,c2=1,v=beefdeaa,k=00d400c300b200a1,o=fcfd5174 45 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=fcfd5174 46 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=fcfd5174 47 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=fcfd5174 48 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=fcfd5174 49 c1=0,c2=1,v=beefdeaa,k=00d400c300b200a1,o=2228453f 50 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=2228453f 51 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=2228453f 52 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=2228453f 53 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=2228453f 54 c1=0,c2=1,v=beefdeaa,k=00d400c300b200a1,o=e66911a6 55 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=e66911a6 56 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=e66911a6 57 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=e66911a6 58 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=e66911a6 59 c1=0,c2=1,v=beefdeaa,k=00d400c300b200a1,o=999b41cf 60 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=999b41cf 61 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=999b41cf 62 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=999b41cf 63 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=999b41cf 64 c1=0,c2=1,v=beefdeaa,k=00d400c300b200a1,o=0b077f18 65 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=0b077f18 66 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=0b077f18 67 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=0b077f18 68 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=0b077f18 69 c1=0,c2=1,v=beefdeaa,k=00d400c300b200a1,o=4a99812a 70 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=4a99812a 71 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=4a99812a 72 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=4a99812a 73 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=4a99812a 74 c1=0,c2=1,v=beefdeaa,k=00d400c300b200a1,o=b588a80f 75 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=b588a80f 76 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=b588a80f 77 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=b588a80f 78 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=b588a80f 79 c1=0,c2=1,v=beefdeaa,k=00d400c300b200a1,o=62fd6f96 80 c1=0,c2=0,v=beefdeaa,k=00d400c300b200a1,o=62fd6f96 81 c1=1,c2=0,v=beefdeaa,k=00d400c300b200a1,o=62fd6f96
Output Waveform (Encryption)
SRAM (Single Cell)
SRAM Waveform
SRAM (the bigger picture)
SRAM (the bigger picture)
Design Decisions
We decided to assign the two most difficult parts of our circuit to two people. Anna and John – SRAM Chris and Liew – Tea Encryption
We are also in the process of determining a sub-layout for the Encryption module
Looked at sensory amps and pre-charge transistors Added the pre-charge transistors to each SRAM Will use a sensory amp at the end of the SRAM to act
as buffer
Problems and Questions
The SRAM only being pulled to 1.2V instead of 1.8V
