HUAWEI TECHNOLOGIES Co., Ltd.

PBL Solution for HSE

Trey MalpassZeng LiYe Min

IEEE 802.3ba Task Force, 23-25 Jan 2008

HUAWEI TECHNOLOGIES Co., Ltd.

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IEEE 802.3ba Task Force, 23-25 Jan 2008

PBL Model

Block Generator

Block Distributor 64B/66B

encoder64B/66Bencoder

64B/66Bencoder

66bitLane1

Lane2

Lane10

CTBI

VCSEL Array

CGMII

BlockProcess

Block Alignment

64B/66Bdecoder64B/66Bdecoder

64B/66Bdecoder

66bitLane1

Lane2

Lane10

Alignment BlockGenerator

Alignment BlockDetector

PIN

PIN

PIN

PCS PMA/PMDMAC/RS

Buffer

Bit Matrix

Bit Matrix

N x（64＋4）bit

N x（64＋4）bit

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IEEE 802.3ba Task Force, 23-25 Jan 2008

PBL Model

• Receives data from MAC layer, generates 64-bit blocks• Transmits blocks through the CGMII bus• Blocks distributed to N lanes, alignment words will be

inserted in each lane following the distributor.• Encode the blocks in each lane (64B/66B encoding &

scrambler)• Bit matrix will adapt N-lane structure to standard CTBI for

all PMDs• Preserves block format in the physical Lanes (Block

interleave in physical lanes)

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IEEE 802.3ba Task Force, 23-25 Jan 2008

Block Generator and CGMII Interface

• MAC data frame will generate the 64-bit blocks using the existing 64B/66B rule.

• Based on the type of the Block, RS generates the 4-bit control code signal.

• (64+4)bit is the unit of the CGMII for each lane

• PBL distributes the blocks to each lane

Block GeneratorControl Signal

Generator

RS

MACMAC Data Frame

TXC<3:0> TXD<63:0>

Lane 0Lane 1Lane n

Distributed to Lane

Idle Insert

CGMII

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IEEE 802.3ba Task Force, 23-25 Jan 2008

Block Distribution and Alignment Insertion

•Alignment blocks will be added into the stream by increasing lane rate

Block Generator

Block Distributor 64B/66B

encoder64B/66Bencoder

64B/66Bencoder

66bitLane1

Lane2

Lane10

CTBI

Alignment BlockGenerator

PCSMAC/RS

scramble

scramble

scramble

•••Packet IPG Packet IPG

64B

64B

64B

A

A

A

64B 64B 64B 64B

64B 64B 64B 64B

64B 64B 64B 64B

•••

64B 64B64B ••• 64B64B

66B

66B

66B

A

A

A

66B 66B 66B

66B 66B 66B

66B 66B 66B

•••

Alignment block after 64/66 encoding

Alignment block before 64/66 encodingA

A

A

A

A

64B

64B

64B

A

A

A

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IEEE 802.3ba Task Force, 23-25 Jan 2008

Insert alignment block by increasing lane rate

• Alignment block is defined using a 64B/66B block format.

• Increase the lane rate to insert the alignment blocks.– If we send an alignment block once every 1375 blocks, the lane rate will

be 10.32GHz (0.073% increase)– If we send an alignment block once every 16k blocks, the lane rate will be

10.313GHz (0.00625% increase)– Alignment block rate will affect

• the maximum skew that can be compensated• adaptation to OTN • receive RAM size for de-skew• clock rate generator complexity in the encoding modules

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IEEE 802.3ba Task Force, 23-25 Jan 2008

What should the alignment block look like

•Alignment block:64-bit data + 4-bit ctrl

•Alignment block after 64/66 coding:

–SEQ is alignment block sequence number

–ID indicates the lane number

5a SEQ ID x x x x x1101

5a SEQ ID x x x x x10

TXD/RXD TXC/RXC DescriptionD D D D D D D D 0000 DataS D D D D D D D 1001 StartC C C C S D D D 1010 StartT C C C C C C C 1000 TerminateD T C C C C C C 0111 TerminateD D T C C C C C 0110 TerminateD D D T C C C C 0101 TerminateD D D D T C C C 0100 TerminateD D D D D T C C 0011 TerminateD D D D D D T C 0010 TerminateD D D D D D D T 0001 TerminateC C C C C C C C 1111 ControlA A A A A A A A 1101 AlignmentO O O O O O O O New OAMN N N N N N N N New NullX X X X X X X X New Reserve

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IEEE 802.3ba Task Force, 23-25 Jan 2008

Insert alignment block by increasing lane rate

•The received data is unaligned because of the skew introduced across physical lanes•Decode and detect the alignment block•Realign using alignment block with the same SEQ•Reassemble data steam in order by lane ID.

64B

64B

64B

A

A

A

64B 64B 64B 64B

64B 64B 64B 64B

64B 64B 64B 64B

•••

66B

66B

66B

A

A

A

66B 66B 66B 66B

66B 66B 66B 66B

66B 66B 66B 66B

•••

64B

64B

64B

A

A

A

64B 64B 64B 64B

64B 64B 64B 64B

64B 64B 64B 64B

•••

64B64B64B64B64B •••

Skewed data

A

A

A

•••

64/66 decode

Re-alignment Re-combine

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IEEE 802.3ba Task Force, 23-25 Jan 2008

PHY OAM Process

• PHY OAM process can be used to monitor lane failures.– LLF/RLF

– Others, i.e. Auto negotiate

• PHY OAM code is defined as a new block type.• Insert PHY OAM by stealing from IPG

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IEEE 802.3ba Task Force, 23-25 Jan 2008

What should the OAM block look like•OAM block: 64-bit data + 4-bit ctrl TXD/RXD TXC/RXC Description

D D D D D D D D 0000 DataS D D D D D D D 1001 StartC C C C S D D D 1010 StartT C C C C C C C 1000 TerminateD T C C C C C C 0111 TerminateD D T C C C C C 0110 TerminateD D D T C C C C 0101 TerminateD D D D T C C C 0100 TerminateD D D D D T C C 0011 TerminateD D D D D D T C 0010 TerminateD D D D D D D T 0001 TerminateC C C C C C C C 1111 ControlA A A A A A A A 1101 AlignmentO O O O O O O O 1011 OAMN N N N N N N N New NullX X X X X X X X New Reserve

1011

Block type:8bits

OAM type: 8bits•x01H:LLF•x02H:RLF•x03H:status advertisement•x04H:BER Monitor•Others: reserved

Broadcast OAM / lane OAM : 2bits

lane ID : 6bits

OAM value : 24bits

reserved

0xa5

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IEEE 802.3ba Task Force, 23-25 Jan 2008

Insert OAM block by stealing from IPG

Block Generator

Block Distributor 64B/66B

encoder64B/66Bencoder

64B/66Bencoder

66bitLane1

Lane2

Lane10

CTBI

OAM BlockGenerator

PCSMAC/RS

scramble

scramble

scrambleIPG DC

•••

• IPG adjustment gains gains enough bandwidth for inserted OAM• Introduce Deficit Counter mechanism to collect extra IPG• OAM blocks cover the extra IPG (generator)

Packet IPG Packet IPG Packet IPG Packet IPG Packet IPG Packet PacketIPG IPG Packet

64B 64B 64B64B64B64B64B64B ••• ••• 64B64B64B •••64B •••

IPG Packet IPG Packet

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IEEE 802.3ba Task Force, 23-25 Jan 2008

Insert OAM block by stealing from IPG

64B

64B

64B

O

O

O

64B 64B 64B

64B 64B 64B

64B 64B 64B•••

66B

66B

66B

O

O

O

66B 66B 66B

66B 66B 66B

66B 66B 66B•••

OO OAM block after 64/66 encoding

OAM block before 64/66 encoding

64B

64B

64B

64B

64B

64B

64B 64B 64B

64B 64B 64B

64B 64B 64B•••

64B IPG Block

64B 64B64B64B64B ••• ••• 64B64B64B64B •••

• Block generator adjusts IPG to get IPG blocks in each lane• Distributor sends IPG blocks to each lane• PHY OAM replaces the IPG block

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IEEE 802.3ba Task Force, 23-25 Jan 2008

Fault Indication by PHY OAM Block

Block Generator

Block Distributor 64B/66B

encoder64B/66Bencoder

64B/66Bencoder

66bitLane1

Lane2

Lane10

OAM BlockGenerator

PCSMAC/RS

scramble

scramble

scrambleIPG DC

Block Reassemble

Block Distributor 64B/66B

encoder64B/66Bencoder

64B/66Bencoder

66bitLane1

Lane2

Lane10

OAM BlockDetector

scramble

scramble

scramble

RLF

Receiver gets lane failure information, returns a Remote Link Fail status to Transmitter for OAM block generation

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IEEE 802.3ba Task Force, 23-25 Jan 2008

Block Encoding

• Receive distributed blocks in each lane• 64/66 encoding format is compatible to 10GE• Independently encode and scramble in each lane• The scrambler polynomial

– G(X)=1+X39+X58

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IEEE 802.3ba Task Force, 23-25 Jan 2008

64B/66B Block FormatsOriginal Data (64bit+4bit) Output Data (66Bit)

Description TXC/RXC TXD/RXD SYNC Block Payload

Data 0000 D D D D D D D D 01 D D D D D D D DControl Block Formats Block

Type

Start 1001 S D D D D D D D 10 0x78 D D D D D D DStart 1010 C C C C S D D D 10 0x33 C’ C’ C’ C’ D D D

Terminate 1000 T C C C C C C C 10 0x87 C’ C’ C’ C’ C’ C’ C’Terminate 0111 D T C C C C C C 10 0x99 D C’ C’ C’ C’ C’ C’Terminate 0110 D D T C C C C C 10 0xaa D D C’ C’ C’ C’ C’Terminate 0101 D D D T C C C C 10 0xb4 D D D C’ C’ C’ C’Terminate 0100 D D D D T C C C 10 0xcc D D D D C’ C’ C’Terminate 0011 D D D D D T C C 10 0xd2 D D D D D C’ C’Terminate 0010 D D D D D D T C 10 0xe1 D D D D D D C’Terminate 0001 D D D D D D D T 10 0xff D D D D D D D

Control 1111 C C C C C C C C 10 0x1e C’ C’ C’ C’ C’ C’ C’ C’Alignment 1101 A A A A A A A A 10 0x5a SEQ ID x x x x x

OAM 1011 O O O O O O O O 10 0xa5 OAMTYPE OAM Value

Null New N N N N N N N N 10 0x00 0x00Reserve New X X X X X X X X 10

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IEEE 802.3ba Task Force, 23-25 Jan 2008

Bit Matrix

• Adaptation between N PBL lanes to CTBI• Adapts to any N-lane physical transport by bit transpose• Bit Matrix is (n x m) memory

– n is number of distributed lanes (physical lanes) – m is number of electrical lanes in CTBI signal (10)

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IEEE 802.3ba Task Force, 23-25 Jan 2008

Bit Transpose (10:4)

64B/66Bencoder

64B/66Bencoder

64B/66Bencoder

4×25G

66bit

Lane1

Lane2

Lane4

CTBI

64B/66Bencoder

LD EML

LD EML

LD EML

LD EML

Lane3 MUXOptical Module

Bit skew

Bit Matrix block

bit

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IEEE 802.3ba Task Force, 23-25 Jan 2008

Bit Matrix

• The block from the independent lane is written into the row of matrix bit by bit

• Bits will be read from column of the matrix• A de-skew lane will help re-align the bits across the CTBI

– The mechanism is the same as the SFI-5 definition.

• A bit matrix is used in the 4x25G module.

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IEEE 802.3ba Task Force, 23-25 Jan 2008

Bit Pass Through

64B/66Bencoder

64B/66Bencoder

64B/66Bencoder

10×10G

66bit Lane1

Lane2

Lane10

CTBIBit Matrix

Special mode for 10x10G module, the pass through mode can keep the blocks running in the lanes

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IEEE 802.3ba Task Force, 23-25 Jan 2008

What do the PMD Modules look like?

Bit Matrix

10X10Gmodule

PL1

PL4

PL2PL3

PL10

PL9

CTBI

XLFBI

PL1

PL4

PL2PL3

4X10Gmodule

When the number of nTBI lanes = the number of module physical lanes, then the module is very simple and 64/66 blocks are preserved at the final output.

•Nx10G PMDs

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IEEE 802.3ba Task Force, 23-25 Jan 2008

What do the PMD Modules look like?

For the 4x25G PMD module, the bit matrix is required to go from 10-lane CTBI back to 4- lane physical; but this module is better able to tolerate the extra cost.

•4x25G PMD

64B/66Bencoder

64B/66Bencoder

64B/66Bencoder

4×25G

66bit

Lane1

Lane2

Lane4

CTBI

64B/66Bencoder

LD EML

LD EML

LD EML

LD EML

Lane3 MUXOptical Module

Bit skew

Bit Matrix block

bit

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Page 22

IEEE 802.3ba Task Force, 23-25 Jan 2008

Applications with PBL Model

• Backplane Transmission• Mapping to OTN

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Page 23

IEEE 802.3ba Task Force, 23-25 Jan 2008

Backplane Application•Backplane transmission

BlockBit

XLFBI

4X10G

PL1

PL4

PL2

PL3

Distributor

FEC

FECFEC

FEC

PMA/PMD

4x10GBASE-KR

FEC function is implemented in each lane; re-use existing KRCurrent FEC requires preservation of 64/66 block boundaries

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Page 24

IEEE 802.3ba Task Force, 23-25 Jan 2008

OTN application•PBL in OTN application

Bit Matrix

10X10Gmodule

PL1

PL4

PL2PL3

PL10

PL9

Transcode

Transcode

Transcode

OD

Un-Xv

OTN Line Card

CTBI SFI

XLFBI

PL1

PL4

PL2PL3

4X10Gmodule

Transcode

Transcode

Transcode

OD

Un-Xv

SFI

Transcode

10X10Gmodule

4X10Gmodule

CTBI

XLFBI

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Page 25

IEEE 802.3ba Task Force, 23-25 Jan 2008

OTN application•PBL in OTN application

CTBIPL1

PL4

PL2PL3

4X25G Module with CTBI Skew Line

Transcode

Transcode

Transcode

OD

Un-Xv

SFI

Transcode

OTN Line Card

CEI-25G

PL1

PL4

PL2PL3

4X25G Module with CEI-25G(In the future)

Transcode

Transcode

Transcode

OD

Un-Xv

SFI

Transcode

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IEEE 802.3ba Task Force, 23-25 Jan 2008

Conclusion

• Blocks running in Physical lanes (rather than bit interleave)– Benefit to OTN mapping and Backplane applications by using existing

technology.– Enables fault detection and maintenance per physical lane– Physical Bundling Layer can be easily extended to higher-rate Ethernet in the

future (1Tbps…)– Block integrity in each physical lane is an important feature

• Alignment blocks will be needed in multi-lane formats– Define the alignment block by extending 10GE block formats– Insert alignment blocks into the data steam

• PHY OAM provides the monitor of physical lane– Lane failure will be indicated (LLF/RLF)– More functions can be considered using PHY OAM (Auto Negotiate, BER monitor)

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