PC Board Design Example v2

7/27/2019 PC Board Design Example v2

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Printed Circuit Board Design Example

By Bob Lineberry, Virginia Tech Computer Engineering

Introduction ............................................................................................................................................................. 2

The Design Process ................................................................................................................................................. 2Eagle Light Edition PC Board Design Tool ........................................................................................................... 3

Create a New Project and Schematic .................................................................................................................. 3

Add Components to Your Schematic ................................................................................................................. 4Wire Modules, Then Connect Modules ............................................................................................................ 11

Generate Board from Schematic ....................................................................................................................... 13Eagle Autorouter ............................................................................................................................................... 19

Advanced Circuits Design Rules ...................................................................................................................... 21The High Cost of Vias ...................................................................................................................................... 27

Traces: Top or Bottom? .................................................................................................................................... 27

Eagle Fonts........................................................................................................................................................ 27Adding Useful Text........................................................................................................................................... 28

Resizing the Border ........................................................................................................................................... 29

Checking Drill Sizes ......................................................................................................................................... 30Pouring a Ground Plane .................................................................................................................................... 30

Eagle CAM Processors ..................................................................................................................................... 37

Graphicode GC-Prevue Gerber File Viewer ......................................................................................................... 40Files to submit ....................................................................................................................................................... 46PC Board Design Steps Review ............................................................................................................................ 46

Ordering a Board from Advanced Circuits ........................................................................................................... 47

Addenda ................................................................................................................................................................ 51Reading Data Sheets ......................................................................................................................................... 51

Making custom parts ......................................................................................................................................... 57

Create SN74LVC4245ADW ........................................................................................................................ 57Create LTL-14 Bi-Polar LED ....................................................................................................................... 74

Create SW-PB-MOM.................................................................................................................................... 75

Copying Library Parts ....................................................................................................................................... 76

Editing Packages to Correct Pin Numbering .................................................................................................... 76Changing All Pads in a Library ........................................................................................................................ 76

Approving Errors .............................................................................................................................................. 79

Correcting Overlap Errors ................................................................................................................................. 79Autorouting a SMD Device .............................................................................................................................. 85

Stop Mask Errors .............................................................................................................................................. 86

Value as Text in Layer 27 ................................................................................................................................. 88Changing Header Numbering ........................................................................................................................... 88

Dimension wont Delete ................................................................................................................................... 89

Manual routing tricks: ....................................................................................................................................... 89Panelizing Boards ............................................................................................................................................. 89


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IntroductionIn this tutorial, we will wade through the process of creating a printed circuit (pc) board. These steps illustrate someprinciples of project management, trouble-shooting, trade-offs, and reading data sheets.

It is tempting to skim a document, looking for quick answers. Students should work through their own design process,sometimes spending hours studying data sheets and experimenting with tools. This document aims to clarify certain

procedures, for which the author found no satisfying explanations.

There are known inconsistencies in the screen captures. The author attempted to document techniques for correctingschematic and board errors in the Addenda. As the outline for this document was refined, only the best examplesremained, regardless of version. You can improve this document by contacting the author with suggested clarifications.

The Design ProcessJust as this document is an exercise in refining the presentation of ideas, the design process continually refines a bundleof hardware and software objects to solve a problem, entertain, or both. Unfortunately, we are constrained by quality,budget, and time. (Or grade, credit limit, end of the semester) (Or good, fast, cheap) You can only have two.

http://en.wikipedia.org/wiki/Project_triangle

Our goal is to create an inexpensive processor-based pc board, which will easily interface with a laptop, a breadboard,and the 3.3V bus of an FPGA board.

Potential building blocks are: Processors, programmers, debuggers Voltage regulator circuits 3.3V-5.0V logic transformation module Surface Mount Device (SMD) breakout USB interface to laptop Diagnostic light-emitting diodes (LED) Sockets to connect this board to a standard breadboard using 22 gauge solid hookup wire

Using a search engine, I spent days reviewing other designs. It is generally cheaper to purchase a demo, evaluation,

breakout, or prototype board than to design and build one from scratch. I found the following designs very attractive: Microchip PICkit 2

(http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en023805) Hack A Day 18F4550 Proto Board (http://eegeek.net/content/view/50/32/) Olimex PIC-USB-4550 (http://www.olimex.com/dev/index.html)

Because we want some special features, we will design our own board. We choose the functions to implement: PIC 18F4550 for USB programming, A/D conversion ICSP port to program and debug from PICkit 2 Boot-loader to program 18F4550 through USB port from PC 5V to 3.3V regulator and bidirectional driver to interface to Spartan-3E board Sockets to connect each module to breadboards, external power, etc. Bi-polar LED logic indicators

We need a block diagram to picture our project in our mind. It was easy to download the schematic diagram of the OlimexPIC-USB-4550 and make notes on it in pencil. If you use a pen, and scratch through previous thoughts, you will have acluttered drawing.

If the parts are not available, the project wont get built on time. Create a spreadsheet to organize your parts Download and search the Digikey catalog (pdf) Check parts choices on the Digikey website for cost and availability

o If Digikey shows little or no stock, you wont get it this semester.

4 August 2008, by Bob Lineberry, Virginia Tech Computer Engineering, Page 2


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If you choose a part that only comes in a QFN package, and you dont know if we have the equipment to solder aleadless chip, you may be heading for an incomplete project.

Download data sheets for each component. Digikey provides many data sheet links, but the manufacturers site will havethe latest information. Transfer mechanical data to your parts spreadsheet. This will help you locate appropriate Eaglelibrary parts or help you edit existing parts.

Read the Eagle User Manual. Draw your design using Eagle Light Edition PC board design tool. Work in pieces or

modules.

Save your work often. Use some form of versioning. If you mess up your design, you will want to be able to start at aknown good version, rather than starting over from the beginning.

Critique your design using Eagles ERC and DRC tools. Force your design to meet all guidelines required by AdvancedCircuits.

Review the Gerber format files, generated by Eagles cam processors, using GC-Prevue.

Assemble all files required for your assignment. This set may be different than the set required by Advanced Circuits.

Eagle Light Edition PC Board Design ToolWe will use Eagle Light Edition, because it is free, and there are numerous examples online. Here are some knownlimitations:

The useable board area is limited to 100 x 80 mm (4 x 3.2 inches). Only two signal layers can be used (Top and Bottom). The schematic editor can only create one sheet.

A search for Eagle tutorials yielded some useful links: http://www.cadsoft.de/freeware.htm http://gaussmarkov.net/wordpress/category/tools/software/eagle/ http://www.muzique.com/schem/eagle.htm http://www.instructables.com/id/Draw-Electronic-Schematics-with-CadSoft-EAGLE/ http://www.sparkfun.com/commerce/hdr.php?p=tutorials

http://www.batchpcb.com/eagle-tutorial.php http://www.opencircuits.com/Eagle_Links

The Eagle website has many libraries beyond the ones in the default installation. It takes less time to use a pre-builtlibrary part than to build one:

http://www.cadsoft.de/cgi-bin/download.pl?page=/home/cadsoft/html_public/download.htm.en&dir=eagle/userfiles/libraries

Download and Install Eagle: http://www.cadsoft.de/freeware.htm

Run ~\Eagle\bin\eagle.exe

The embedded help file can assist an experienced user. The user manual is more thorough and highly recommended. ~\Eagle\doc\manual_en.pdf

Create a New Project and SchematicEagle Menu: File--New--ProjectPIC_kludge

http://en.wikipedia.org/wiki/KludgeFile--New--SchematicFile--SaveAs--PIC_kludgeView--Grid--



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The grid helps place components in a logical orientation. Most parts, we are specifying, have 0.1 pin spacing, so wechoose the default, but turn the display on. We would hope the grid would stay on every time we open our project, but itdoes not.

Add Components to Your SchematicAdd component modules to the schematic view. Our modules are: PIC chip, I/O connections, voltage regulator, logictranslation, and logic indicators.

Study another project, like the Hack A Day 18F4550 Proto Board. It does not matter how the components are placed, soleave plenty of room between modules.

Add the PIC18F4550_40, from the microchip library. We chose the 40 pin DIP package to allow soldering with a penciliron and to simplify adding sockets next to each pin for creative expansion.



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Left click the mouse to anchor the part on the grid. Escape twice gets you out of add mode.

What is an ICSP port? What does it look like? What library part? How much time do we need to spend browsing Eagle

libraries before we have a good feel for what parts are available?

By studying the PICkit 2 documents, especially 44-Pin Demo Board User's Guide and PICkit 2 Users Guide, I foundthe pinout and mechanical considerations for this jack.



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By loading the Hack A Day 18F4550 Proto Board Eagle schematic, using the i (info button), I identified the Eaglelibrary, con-lstb.

The part, MA06-1 looked close, so I added it to our schematic page.

To add a USB connector, I studied the Hack A Day 18F4550 board page, which revealed a Berg library. This helped mefind a Berg 61729 connector, which is available at Digikey.



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When I was adding the USB connector, I found that right-clicking the mouse rotated the connector, before placing it. Youcan also use the Move tool and the right mouse button to rotate parts. Test this function before you need it. How manymouse buttons did you use? In what sequence?

I did not find a LM1117 voltage regulator in the default Eagle library. However, by searching the libraries page at http://www.cadsoft.de/download.htm

I found v-reg-2.lbr had the part, so I copied it to my installed version of ~\Eagle\lbr\

From the Eagle control panel, I scrolled down to the new library and highlighted the dot to include it in my project. Thismakes it easier to choose from a smaller set of libraries when adding parts.

I added a LM1117 (TO220 package) in vertical orientation.

The next part is a Texas Instruments SN74LVC4245ADW Octal Bus Transceiver in a 24-SOIC package.

The texas.lbr did not contain a similar device. A google search did not reveal a library part. So lets make a part.

Refer to: Create SN74LVC4245ADW in this documents Addenda.

Add the newly created component, 74LVC4245.



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I wanted to rotate the chip before anchoring, so I right-clicked, while the part was hovering, then left-clicked to anchor it.

I want to add sockets for easy connections from this board to a standard breadboard. Also, I want to connect a signal toon-board diagnostic LEDs.

I look through the con*.lbr for appropriate connectors. Remember we used the con-lstb.lbr for pin headers. Con-lsta.lbrhas socket headers.



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Add a 20 pin socket header to the schematic page. Right-click to rotate, then left-click to anchor.

Leave enough room for Labels, which can be used to connect Nets. Sometimes it is easier than drawing a lot of wires.

Move Groups as needed to organize your design.

Select Group button Draw a rectangle around the group of components Right-click the middle of the group and select Move Group Right-click to rotate Left-click to anchor

Add additional sockets as desired.

We also need sockets for LED indicators. Bi-color LEDs would be nice. SIP resistor packs would simplify assembly.



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I did not find all the exact parts, so I chose similar parts, based on the electrical and mechanical data found in thecomponent data sheet. Above is resistor-sil.lbr.

Above is a first trial of the LED indicators. I was not pleased with the LED symbols. There were no appropriate bi-polarLED devices in the standard Eagle libraries and I could not find one online.

Refer to: Create LTL-14 Bi-Polar LED in this documents Addenda.



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Add LTL-14 LEDs to our schematic.

How about external power? We could use USB power or wires from another power supply. Lets add an external powersocket connector from library lsta and power selector pins from library lstb.

Refer to: Create SW-PB-MOM in this documents Addenda.

Add momentary push-button switches for Reset and Boot-Load functions for the PIC18F4550.

Wire Modules, Then Connect ModulesRead the Eagle User Manual, located in the directory ~\Eagle\doc, particularly the sections, The Schematic EditorWindow, Creating the Schematic Diagram, and Considerations Prior to Creating a Board. The concepts of wire, net,name, value, and label will take some practice before they become familiar.

Complete your Schematic view before creating the Board view. Learn one tool at a time.

Labels can simplify and clarify connections.

In this screen capture, a wire was drawn from the connector SV1 one grid length. This was necessary because we couldnot apply a Label to a connector pin. The wire is assigned a Net Name, like N$33. When a Label is added to the end of awire, a dialog asks us to confirm that we want to connect the Net Name to the Label Name. A Label Name indicates thatall wires or nets with that Name are connected together.

As an experiment, I attempted to add a Net to the connector pin, as the User Manual instructed. The Net turned into aWire, with a Net Name, and Naming the Net produced the same dialog as Labeling a Wire. There is no one correctmethod to producing a working design.

In the next screen capture, a wire was added between the connector and resistor (Name=R6, Value=221). A wire wasadded to the end of R6 so we could add a Label Name (RB5). Eagles Electrical Rule Checker (ERC) complained that weneeded to add a junction symbol between SV1-Pin1 and R6.



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Wire each module separately. Run ERC often. Dont ignore warnings or errors. Dont automatically approve allexceptions. Take the time to understand why Eagle is complaining. In our design, we will approve several exceptions.

I like to place power and ground pins directly inside the rectangle of the symbol view. Eagle doesnt like that. After making

absolutely sure these connections were correct, I approved these exceptions.

When I was laying out the Board view (next section), several component values overlapped useful text and EaglesSmash command did not work for me. I wanted most values to remain on the Board, to help mount components, so Ichose to remove some value fields for clarity. Eagle didnt like this. In most cases, I added Text in the Value layer, whichis similar to the Value field associated with a component, but easier to move independently. After making absolutely surethe Text matched the Value, I approved these exceptions.

Our complete schematic has many standard resistors and capacitors, which closely match the data sheets and the libraryparts. Transfer important component dimensions from the data sheets to the parts spreadsheet to make our library searcheasier.



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I did not find any shortcuts for this process. We need to allow enough room for each components footprint so we dontcrowd them together on the board. We need to match the lead spacing or risk damaging components when they aremounted. The pad drill sizes and diameters can be adjusted for groups of components, as we will show later in thisdocument.

Generate Board from SchematicThere is a button (below View), which switches between the Schematic view and the Board view. The first time this button

is executed, a generic board view is generated, similar to the one below.



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It is critical that the Schematic and Board remain consistent. Some edits to the Board view will damage this relationship.Eagle will generally display an error message before allowing such actions. ERC will indicate if the views and their linksare consistent.

The components are initially drawn outside the default board border. Each component will need to be moved into theboards border. The border size can be adjusted later.

If you need an exact border size, you should set this before placing components. The border snaps to the grid, so youshould set the grid size to the needs of the project.

ViewGridDisplay=On, Size=0.05 inch



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Using the Move tool, select each component and move it inside the board outline. Place components from one corner ofthe board and fill the board efficiently. Place connectors close to an edge. Place components within a group together.

Use the schematic to locate a components name to help differentiate where identical value components are placed. Usethe Board/Schematic Button to toggle between views.

Rotate components so the airwires are short, straight and not crossed. This exercise involves some trial and error; youcan move these components repeatedly as you finalize your board routing.

The next screen capture shows an obvious crossing of airwires.

Rotating the component will improve signal routing.



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In the next screen capture, all the components are placed compactly, but the airwires are not optimized. Zoom in to anarea to untangle the airwires. The problem areas may become clearer when we start auto routing the board.

When the board is first generated, the default visible layers (Display tool under the info tool) are:



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Review the Eagle User Guide, Chapter 10, Layers and their Usage. As we place components, we may find that a layersinformation overlaps another layer, interfering with a clear visualization of how our board will turn out. You may toggle anylayer on or off. It is tempting to turn on all layers, to be safe, but this will produce some unexpected errors. See StopMask Errors in the Addenda.

The following screen capture shows overlapping information.



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Notice what happens if we turn off the tNames layer:

We need to see the values in the board view, to be able to easily mount our components, but we dont really need to knowthat the resistors are named R4 and R3. We may decide to select or deselect layers in the cam processors whengenerating our Gerber files later in this document.



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Regularly run ERC and DRC, using the default rules.

Double click any DRC errors to zoom in on the problem:

All 4 of these errors indicate that we have placed the double socket connector too close to the edge of the board. We

move the connector. We will need to check the default Eagle rules against the requirements for Advanced Circuits beforedeciding we have found all relevant errors.

If there is no popup window, generally there are no DRC errors. You can select the yellow exclamation mark to see thatindeed there are no errors. This is a good sign.

Eagle AutorouterImportant:

Read the Eagle Users Manual chapter on the Autorouter before running these tools.



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Do not crop the border until the design is fully routed; you may need to move components to allow room fortraces.

Always run the Ratsnest tool before running the Auto router tool. From the Board view, select the Auto route tool button and save the default settings for future use.

ceeding.

The EAGLE Autorouter is based on the ripup/retry algorithm. Save your files, using versioning, on a regular basis. Run ERC and DRC regularly, and fix errors before pro

After running the Ratsnest tool, several components obviously need to be rotated, like the LED header:

ontinue rotating components until all obvious tangles are straightened.C



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From the Board view, select the Auto route tool button and save the default settings for future use.

Read the Eagle Users Manual section on What Has to be Defined Before Autorouting.

Advanced Circuits Design RulesThere are a lot of pages to read. Much of the information is beyond the scope of our simple design project. However, eventhough I have been very careful to follow all the guidelines, every board I have sent them has gone to Cam Hold. Thisdelays the boards manufacture by one or two days as you explain to their engineers why your board is special andneeds to be produced with all the errors intact.

Here are some of their design rules I followed: http://www.4pcb.com/ Tips & Tools

http://www.4pcb.com/http://www.4pcb.com/http://www.4pcb.com/


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o Rigid PCBs Proto vs. Production (we will be ordering a standard spec board) Tolerances

o Glossary of Terms

From the Eagle Board view, choose EditDesign Rules. Save the default before modifying. To the best of my knowledge,the default Eagle Design Rules meet all of the specifications required by Advanced Circuits.

Lets run the default Auto router and see how bad it is. Even though auto routers are crude, you can trick them by usingrestrict layers.

Note that the SMD did not get routed. Refer to: Autorouting a SMD Device in this documents Addenda.

After the Routing Grid has been changed from 50 to 25, the Auto router completes, but there are some obvious areas forimprovement.



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Component layer traces (or vias) under a SMD will hide any problems. Traces beneath a SMD may be damaged if theSMD needs to be replaced.

Choose the Ripup tool, then the Green Traffic Light button to rip up all signals.



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Choose the Change tool, and select layer tRestrict.

Using the Rect drawing tool, draw a rectangle under the SMD. Left click to start the rectangle. Release the mouse button.Start dragging to reveal the rectangle extents. Left click to end the rectangle. Do not cover the SMD pads.

Ratsnest, then Auto route again.

Change the layer to bRestrict.Draw a Rect around the SMD.Ripup all signals.Ratsnest, then Auto route again.



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The SMD traces are still very close to the SMD pads. If our soldering technique is not perfect, we may have a short circuitLets increase the wire to pad clearance in the Design Rules.

Through trial and error, 12mil clearance gave the best results while minimizing vias. Save as SMD1.dru



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We could manually move the trace, which contains the via, but this could create more problems. Refer to: Dimensionwont Delete in this documents Addenda.

Instead, lets try to restrict it. Change layer to vRestrict. Draw a Rect to specify the rectangle where we want to restrictvias. Ripup all signals, Ratsnets, and Auto route.

Now no vias are obvious. An easy way to look for vias is to Display only the via layer (18). We have a blank page.

To get back to a reasonable Display of layers, select all, then de-select: tNames(25) and tStop(29). Refer to: Stop MaskErrors in this documents Addenda.



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The High Cost of ViasWhy are vias a problem? If you google for through hole via reliability, you will find that there is no preferred method fordealing with them.

If you leave them as-is, the thin plating of the drilled hole may crack when the board expands at a different rate withrespect to temperature.

If you fill a via with solder, the solder may hold the plating tightly, allowing the pad to separate from the board.

If you fill a via with a wire, then solder, you have added an enormous cost to the board.

If the via is under a SMD chip, there is no way to probe or fix a problem.

The obvious solution is to avoid vias. Thats why Eagle places a high cost for vias. Look at the default tabs in the Autoroute GUI. The initial cost of 8 quickly increases to 99 as the routing is optimized. The higher the cost, the more the autorouter algorithm attempts to avoid that choice.

Traces: Top or Bottom?Another issue is whether the majority of traces should be routed on the top or bottom layer. On a board, with only surfacemount components, the top layer is the only option. If we want to generate a large ground plane on the bottom layer, we

would want to route most traces on the top layer. If we have connectors, which conceal the top pads, we want to routetheir signals on the bottom layer to avoid covering potential problems.

Eagle Fonts http://www.cadsoftusa.com/faq.htm#06022701

EAGLE uses and shows in the Layout Editor (also in the Schematic) a proportional font by default. But this one can't beused for generating manufacturing data by the CAM Processor. The CAM Processor can only work with the EAGLEinternal vector font. The appearance of the vector font however, differs from the proportional font in size and length. Thuswe recommend to write all texts - at least those in copper layers - in vector font.

Besides, there is the option Always vector font in the Options/User Interface menu which displays and prints all texts invector font, independent of the originally defined font. If this option is active, the texts on the screen will look exactly thesame as they will do on the printed circuit board. A particularly suitable example to demonstrate the differences would beinverted text in a polygon (therefore the text is written in one of the Restrict layers). If you pass on the BRD file directly toyour Board House in order to let the operator there generate the manufacturing data, it's recommended to activate theoption Persistent in this drawing, too. In this case his EAGLE system will display the vector font as it is on yours. It doesnot matter if the option Always vector font is set or not then.

http://www.cadsoftusa.com/faq.htm#06022701http://www.cadsoftusa.com/faq.htm#06022701


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Adding Useful TextIn our example design, we chose not to Display tNames (to eliminate clutter) and tStop (to eliminate nuisance stop maskerrors).

However, we are missing some important information, which will help us place components and troubleshoot thepopulated board. Few designs work perfectly the first time.

Change the layer to tValue (27), since we know we will cam process tValues in the top silkscreen layer.

Choose the Text tool. Enter the string, but dont paste it yet.

Change the text parameters for a Size of 0.05, a Ratio of 15% (thickness/height) and Font: Vector. I used trial and error toarrive at these settings.

Use the Zoom tool for a more precise view. Feel free to turn off some board layer views if it will make the final boardclearer. You may want to turn off the bottom layer, since it wont interfere with text on the top layer.

Important: If you have to move a component, Ripup all first, Move the component, Ratsnest, and Auto route again.

Here, we have finished annotating our board. We used several areas of tRestrict to make component identification clearer.

o We forced the USB connections to be on the bottom side of the connector. Note that if you cover all 4pads of the USB connector with tRestrict, DRC will complain.

o We placed tRestrict over several component Values, to avoid the process of removing value, adding text,approving an ERC error, for each component.



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o To force the top trace away from the LM1117 voltage regulator, in case we need to add a heat sink.o Overlapping a tRestrict polygon with a pad will produce an error.

We grouped components into modules and moved them several time to eliminate all vias. More time was spent re-arranging and re-routing this board so this tutorial would be as clear as possible. In the next screen capture, bottom traces are turned off.

Resizing the BorderSo far, we have been able to fill our screen with our PC board view. The actual board size will appear much smaller,similar to this:



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There may be a mechanical constraint, which forces the board to be long and skinny, or L shaped.

We set the border in the dimension layer. For our purposes, we can just move the right side of our board outline.

If you need an exact border size, you should set this before placing components. The border snaps to the grid, so youshould set the grid size to the needs of the project.

Checking Drill SizesWe must specify drill (hole) sizes large enough to insert the leads of our components or our project will not be completedon time. If you manually drill a PC board hole, you will destroy the through-hole conductive plating.

Refer to the spreadsheet you made to organize your parts. There should be columns for: Default Eagle Drill (size) Datasheet Maximum Drill (inches)

If you need to increase your drill sizes (which includes your pads), you need to group the affected components in aseparate library by size. The ULP script changes all the pads in a library.

Refer to: Changing All Pads in a Library in this documents Addenda.

Pouring a Ground PlaneIt is a challenge to pour a ground plane. Before experimenting, create a new copy of your schematic and board files withsome kind of revision control. For example, copy the PIC_kludge_4 files to a temp directory, rename them asPIC_kludge_5 and copy them back to the original project.

Run the ERC and DRC and make corrections before attempting the pour.

Delete the bStop and bRestrict rectangles, under the SMD, before the pour.

Change layer to 16 (Bottom)



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Draw a polygon around the outside edge of the board. The parameters are at the top of the screen. Adjust the parametersfollowing the Eagle User Manual. Thermally isolate pads from the plane to be able to solder them.

The polygon will appear to smear, like a thick line, until you left click at the end. Then the polygon becomes dotted.

Choose the Name tool; double-click a polygon blue dot; connect the pour to DGND.

Here are the properties of our blue-dotted polygon:



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To view the results, select Ratsnest (obviously). To increase the Pour area, decrease the Spacing and Isolate values.

If you need to Modify your design, Delete the Polygon first. With the Move tool, left-click near the edge of the Pour toreveal a dotted polygon line. Move the line outside the boards border. Now the full Polygon is revealed and can be

deleted.

Make any changes in the Schematic view, then in the Board view, then Ratsnest and Auto route. When you are satisfied,you can add the Pour.

If you make modifications with the Pour in place, signals will automatically tie to the Pour and create other routingproblems that you have already solved.

Coverage with Spacing and Isolate = 0.024



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How do we trick the program into Pouring under the PIC processor? Bogus parts. Lets add some 1.0M resistors underthe PIC, which we will not populate (R9 and R10). We chose these signals because the traces were already runningunder the PIC.



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Eagle CAM ProcessorsThe Computer-Aided Manufacturing (CAM) processors convert vector information to Gerber format. PC Boards used to bedrawn on huge Gerber plotters and transferred to photo-sensitized board stock. Some of the naming conventions remain,despite improvements in technology. Before surface mounted devices, there was a sharp distinction between theComponent and Solder sides of a board.

Some information will be on both the Top and Bottom layers, like pads. It is helpful to automate a mapping of layers tooutput files. A component can be replaced in the Schematic view, routed in the Board view, ERC and DRC checked, andCAM processed in minutes.

From the Board view, choose FileCAM Processor. We need tabs for each output file. The section name should bedescriptive and clear. The Device output is critical. All output files use GERBER_RS274X, except the Drill section, whichuses EXCELLON. The output file names should be meaningful and have the correct extension.

Default Solder Settings:

Note that we Added a tab for each new output file.

Default Component Settings:



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Custom Top Silkscreen settings. For our board, we will not use the tNames layer in this cam processor. The tNamesclutter the silkscreen. The tValues are more important for this design. The LED flat is in layer tDocu. We want to add thislayer to the top silkscreen cam processor tab.

Default Bottom Silkscreen:



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Default Bottom Solder Mask:

Default Top Solder Mask:

Default Drill Settings:



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Default Border Settings:

Save these settings in a dot cam file.

Process Job to generate all the output files.

Graphicode GC-Prevue Gerber File ViewerHow do we know if we succeeded? We need an accurate Gerber file viewer.

Download and install the free version of GC-Prevue http://www.graphicode.com/ You will need to register

Kill the buy me splash screen to reveal a rectangular border.

We need to import each CAM layer. We can change the colors and turn layers on and off later.

http://www.graphicode.com/http://www.graphicode.com/http://www.graphicode.com/


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You may check all the imported information, but usually multiple Enter key strokes displays the imported layer.



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Continue importing at least the border (.bor), bottom (.sol), top (.cmp), top silkscreen (.plc), and dril ls (.drd). Once you aresatisfied with these layers, you may add any other layers you generated.

The order of importing affects the view. Importing the border layer first automatically sizes the viewing frame. Import thebottom layers before the top ones.



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I installed the current version of GC-Prevue and all my layers were yellow. Double-click any layer (left column) to open aproperties dialog. Make choices for each layer, Apply, and OK. I have not found a way to automatically apply a specificcolor each time I input a layer.



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You can hide layers. There are multi-color flag-like icons, which globally manipulate layer views.Note that when you View after Hide, you may need to move the cursor into the project window before the layer turns on.

The Layer Information (right-click) of the Border layer gives us the size of the board:

The Layer Information of the Drill layer gives us a good idea if we have undersized a substantial number of pads and drillsfor our component selection.

Eagle Lite version 5.0 is more accurate than previous versions. We still want an independent view of the files we will besending to our board house. Remember that we can control which information is present in each layer using the CAMprocessors.

Lets compare Eagles view to GC-Prevue:



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Files to submitFollow the instructions given in your assignment. Who is your audience? Who is your customer?

Assemble all the files specified in the CAM processor section with the current schematic and board files. This wouldinclude: .sol, .cmp, .plc, .pls, .sts, .stc, .drd, .bor, .sch, and .brd files.

Zip all these files with a file name that identifies who you are, what the project is, the version of the project, and the date of

submission. Abbreviations are fine.

PC Board Design Steps Review1. It always takes longer than you think2. Research, read, make notes3. Sketch a preliminary design4. Determine if your selected parts are available, affordable, and able to be soldered5. Download all Data Sheets and make an organization spreadsheet6. Sketch a schematic diagram7. Breadboard your design and make it work8. Search for examples, which clarify unfamiliar topics9. Revise your schematic diagram10. Transfer your schematic diagram to Eagle11. Use version control so you dont have to start from the beginning12. Create a board view in Eagle13. Constantly run ERC and DRC14. Use tricks to fool the Auto router15. Run CAM processors to generate Gerber files16. Critically review your generated files in an accurate Gerber viewer17. Modification Order: Sketch, Breadboard, Schematic, Board, Restrict, Ratsnest, Auto route, CAM, GC-Prevue18. Assemble your files and submit them19. Dont skip steps if you get stuck. Review what works and what doesnt.20. Make your creation a reflection of your self-image. Do you want to work for BMW or Walmart?



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Ordering a Board from Advanced Circuits Zip your Gerber files: .sol, .cmp, .plc, .pls, .sts, .stc, .drd, .bor Upload your zip file to http://www.freedfm.com/

Immediately, their software recognizes all of the layers, except .bor, for which we choose Drawing/Other. They mayignore this file by using the extents of the components as the border size.

The bottom of the page requires some thought. Since I am a registered user, my name a telephone number are filled infrom their database. We are ordering a prototype, so follow those guidelines. If you submit top and bottom silkscreen andsolder mask, you must choose both for those fields, or receive an error. 0.062 is a standard board thickness. Use theLayer Information for the border file in GC-Prevue to find the X and Y dimensions.

http://www.freedfm.com/http://www.freedfm.com/http://www.freedfm.com/


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After Submit, wait for an email.



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You must view DFM results before concluding that your design is OK.

The standard price is $83.58 each in quantities of 5. Thats too expensive. The last time I ordered, I was able to changethe quantity field to 1 and re-calculate.

I decided to click through to see if I could order less than 5. No.

Even though I ran all my designs through their FreeDFM design rule checker, my boards still ended up in Cam Hold afteplacing my order. After working with a board house for several years, through dozens of designs, you may appreciate whythey red flag certain techniques and you may choose a more conservative design approach.

http://www.4pcb.com/

http://www.4pcb.com/http://www.4pcb.com/http://www.4pcb.com/


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Obviously, there are too many options. Lets choose a simple order. If you are a student, you may be able to order a$33.00 special. Read the fine print.

You may be able to panelize your design and further reduce the cost. For instance, I could fit 6 copies of the board usedin this document on a panel. See Panelizing Boards in the Addenda. Be careful not to let another group hold up theproduction of your board and adversely affect your grade.

Update: We panelized a board this summer and ordered a $33.00 special. They charged us an extra $50.00 for multipleparts, even though there was really only one part. I argued with them for a half hour. Even if you connect multiple boardswith some bogus traces, they will find it and charge the extra $50.00. With shipping, 9 boards cost around $100.00. Let usknow if you find a better deal.



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Addenda

Reading Data Sheets

The following part requires 0.039 +0.004 -0.002 drills, on 0.100 centers. If the leads are closer to the maximumdiameter, will they fit into your dri lled pad?

The following part requires 0.43 mm dril ls, on 4.88 mm centers. No tolerances are specified, but we should allowfor manufacturing variations.



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The following part uses a bussed schematic, so locating Pin 1 is critical.

The following part has a polarity that depends on lead length.



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The following part has a non-standard footprint and angular leads.

The following part has mounting holes and very large drills.



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The following parts have a different lead spacing, depending on value.

The following parts have a different lead configuration, depending on value.



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Tantalum capacitors are extremely s table and have a low effect ive series resistance (ESR). They also have apolarity and tend to explode when reverse-biased (installed backwards).

The following vol tage regulator will shut down if it gets hot. Note that a TO-220 case with no heat sink will exhib itan average temperature rise of 79 degrees C above ambient if you try to dissipate a Watt through it. That will burnyou.



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The following resistors dimensions vary by power dissipation.

The following tranceivers require two vo ltages, three grounds, and log ic referenced to Vcca.

You might want to pro tect this device, since it is a surface mount package and diff icult to replace.



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Making custom parts

References:

http://www.instructables.com/id/How-to-make-a-custom-library-part-in-Eagle-CAD-too/ ftp://ftp.cadsoft.de/eagle/userfiles/doc/eagapp3.zip

Create SN74LVC4245ADW

The 74xx-us.lbr contains a SO24W package. But I cant add it to the schematic.

There are 3 essential representations of a component: package, symbol, and device. The package is the physicalrepresentation. The symbol is the representation on the schematic page. The device representation maps the logical pinsto the physical package.

Page 14 of the SN74LVC4245ADW datasheet gives the dimensions of the DW package.

The most difficult function I encountered was copying a package group to the paste buffer. I changed versions from 4.16r2to 5.0.0 (recently released) to see if there were any improvements. I checked to see if there was a SN74LVC4245ADW orsimilar part in the Eagle 5.0 package. I was back to making a new device.

In this part creation process, we are going back and forth between an existing library and a new library we are creating.Eagle allows only one library to be open at a time.



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We could build a package from scratch, but to save time we copy a package from another library:Control PanelFileOpenLibrary74xx-us.lbrSelect the Package button

Choose the SO24W package:

Select the Group button



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Depress and hold the left mouse button to start a selection outside the package. Drag a rectangle around the entirepackage and release the mouse button.

Note that the package changes colors (brighter), when selected.

Select the Cut button.

One option is to choose the Go button (next to the Stop sign) after the Cut button:



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Another option is to right-click over the selected group and choose Cut Group. Another option is to right-click outside ofthe group and choose Cut Group. The appearance is very different for each option, but the result is the same.

This places the group in the Paste Buffer.

FileNew (opens new library) FileSave As (74LVC)

We have created the 74LVC library. There are no completed components in it yet.

Select the Package button



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When the Paste button is selected, the Paste Buffer contents appear in the editor window. Move the mouse to the centerof screen and paste the device package with a left click. To help place this package on the pc board, place it with thecursor cross hairs near the middle of the package.

FileSave

Open 74xx-us.lbr

There is an octal bidirectional bus transceiver, similar to our device. This closes the 74LVC library, because Eagle Lightonly allows one library to be open at a time.

Load an existing symbol, similar to our bidirectional buffer.



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Use the same general procedure to copy this symbol to the paste buffer: Group Select All Cut Group



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Open 74LVC.lbr Select the Symbol button Create a New Symbol



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Study the SN74LVC4245A data sheet

Select the Name button

Use the left mouse button to select a pin (not the name string) to change a pins name. In our example, we selected theleft end of the pin named G. We will change its name to match the data sheet.



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Note we have used !OE in the dialog box. On the Symbol editor, OE, with a bar on top, appears. This is an Eaglefeature.

To enlarge the symbol footprint, in order to add more pins, select Move, left-click an edge, drag the outline, and left-clickto anchor.

ViewZoom-to-fit or choose the left-most magnifier icon.

To move pins, choose the Move button. Left-click the end of a pin to select it, move it to the desired location, and left-clickto anchor it.



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To add pins, choose the Pin button from the left side menu. Move the mouse to place the pin, right-click to rotate the pin,then left-click to anchor it.

When you select the Pin button, green circles are shown on the symbol. This is another Eagle feature.

With Name selected, right-click a green circle and choose Properties. The Direction is In for input. The Length is Middle,but could be short or long. The Function is Dot for low-true. Read the Eagle user manual for more information.

To Move the variable name, >Value Change Layer to Values



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On the symbol view Left-click >Value, move cursor, left-click to anchor.

Change layer back to Symbols

Finish adding pins, names, and properties, so that our symbol matches the data sheet. Note that Eagle was not happynaming two pins with the same string, so we had to be creative (3.3VA and 3.3VB).

The final step is mapping a device variant.

Select the Device button Add a New device



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Add the symbol we just created



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Select the New button Type in an appropriate variant string



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ADW is our package variant for the SOIC or SO24W in the SN74LVC4245A data sheet. A is for chip revision A. DW is forSOIC.

Have your SN74LVC4245A data sheet open. Select the Connect button

Highlight corresponding pin and pad and choose Connect. You should connect a pin name to each pad name.



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OK. File--Save

We now have our new library component to add to our schematic.



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Create LTL-14 Bi-Polar LEDRefer to Create SN74LVC4245ADW for a more detailed description of creating a part.

Steps: Open the Library editor (led.lbr) Copy an existing package (LED3MM.pac) to the Paste Buffer (Group, Cut, Go) Open a new or existing library PackageNew--Name Paste Buffer and Save (library) Open led.lbr again Copy an existing symbol (DUOLEDRG-A) to the Paste Buffer Open the same library you pasted the Package into SymbolNew--Same Name as Package, above Paste Buffer and Save (library) Edit symbol layer to match our chosen component Save (library) Create new device (Same Name as Package) Add symbol we just created New (variant), Package name as above, variant named something useful Connect: Map our symbol to our package

Save (library)



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Create SW-PB-MOMRefer to Create SN74LVC4245ADW for a more detailed description of creating a part.

Steps: Open the Library editor (switch-dil.lbr) Copy an existing package (DS01.pac) to the Paste Buffer (Group, Cut, Go) Open a new or existing library PackageNew--Name Paste Buffer and Save (library) Open switch-misc.lbr Copy an existing symbol (DT) to the Paste Buffer Open the same library you pasted the Package into SymbolNew--Same Name as Package, above Paste Buffer and Save (library) Edit symbol layer to match our chosen component Save (library) Create new device (Same Name as Package) Add symbol we just created New (variant), Package name as above, variant named something useful Connect: Map our symbol to our package

Save (library)



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Copying Library PartsEagle Control Panel: File-New-Library: PIC_kludgeResize windows to view both Eagle Control Panel and Eagle Library Editor windows.Control Panel: Left-Click & Drag Device LVC4245 from 74LVC library into Library Editor window.Library Editor: Save PIC_kludge library.Control Panel: Expand PIC_kludge library to reveal device LVC4245 added.

Add all the other custom parts to the PIC_kludge library to make them easier to find, in case editing is required.

Editing Packages to Correct Pin NumberingEdit MA06-1 package. Remove the 1 and 6, since the connector is wired backwards. We will use text on the board toshow pin 1.

Edit MA06-1 device. New variant. Scroll down to choose MA06-1. Choose variant A.

Connect 1.1 to 1, 1.2 to 2, etc.

Save.

In Schematic view, replace MA06-1 with MA06-1A.

In the Board view note the conflicting 1 and 6 are gone. Use the Text editor to add (1), size 0.05, vector, ratio 12%, layer27 tValue, next to the VPP pin.

Changing All Pads in a LibraryMake new libraries, according to drill size.Copy devices to these libraries, which require a global change to drill size.Remember that the change-pad-in-lbr.ulp script changes all devices in the library.

What are the default drill sizes for each part?

Library: open PIC_kludge.Device: open MA06-1 (we did this to find the package)The upper right corner shows a MA06-1 package.Package: open MA06-1Right-click a pad; select properties. Note the default drill size is 0.032 inches, which will not fit the pin header we haveselected.

Refer to your organization spreadsheet. Note that parts CON-9, CON-20, MA06-1, and FE05-1 all require larger drillsizes.

Control Panel: File-New-Library: PIC_kludge_040Resize windows to view both Control Panel and Library Editor windows.Control Panel: Left-Click & Drag Device MA06-1 from PIC_kludge library into Library Editor window.



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Library Editor: Save PIC_kludge_040 library.Repeat for the other 3 parts.Control Panel: View PIC_kludge_040 library to see that it contains all 4 parts.

Library Editor: PIC_kludge_040Run ULP:



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Convert inches to mm to run this script. http://www.unitconversion.org/unit_converter/length.html

This will change all drills within +/- 50% of 1.016 mm.

View Grid to change back to inches.

Now right-click a pad (properties) to check the dril l sizes:

http://www.unitconversion.org/unit_converter/length.htmlhttp://www.unitconversion.org/unit_converter/length.htmlhttp://www.unitconversion.org/unit_converter/length.html


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Schematic View: Replace the original parts with the enlarged-drill size parts.Make sure the changes are consistent between the board and schematic views by running ERC and DRC.

In my case, I had to move a trace to increase the clearance between it and a switch pad.Split is a good tool to move only a small section of a trace.Continue refining until ERC and DRC produce no (unapproved) errors

Approving ErrorsSchematic (ERC Errors and Warnings)

I like to include the power and ground pins in the Symbol view. Eagle complains when +5V, GND, VDD, or VSSare connected to such pins. Approving such errors or warnings moves them to a folder that can be safelyignored.

When the Value of a component clutters a board layout, I remove the value. This is reflected in the Schematicview and can be safely approved and ignored.

Board (DRC Errors) Board errors are more serious, usually indicating short circuits or mechanical conflicts. These should be fixed. If you are designing a special board, with special mechanical features, you may carefully approve errors. Board errors will probably be caught by the board manufacturer, so be prepared for a delay.

Correcting Overlap ErrorsWe need to correct the multiple DRC errors and figure out how to autoroute the SMD chip.

Reduce the size of the problem. Make a test project, using just the SMD chip and the headers.



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ERC errors are expected.

Generate the board layer.

Move components into board outline, rotating for straightest airwire placement



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Lots of DRC errors, just like with our larger project

Simplify. Cut the problem in half. Check the library part, which we created. User error is generally a good place to starttroubleshooting.



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This should be pin 1. Somehow, the library part became corrupted.

So we generate a new library part: We copy the package from 74xx-us.lbr, SO24W, as before. We name the new package LVC4245 to distinguish it

from the corrupted part. We check the name of each pin. They are in order from 1 to 24 as required. We copy the symbol we created from 74LVC.lbr, 74LVC4245, to save all the time we spent editing. We name the

new symbol LVC4245 to distinguish it from the corrupted part. We add a new device, named LVC4245. We add the LVC4245 symbol, we created. We add a new variant, called

ADW, to make our part match the manufacturers data sheet. We connect the pin description to the pin number. We save our work often.

Use the replace command to replace the 74LVC4245 part with the newly created LVC4245 part in our test schematic.



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We have some expected ERC errors, which can be approved and ignored.

Our test board looks almost identical.



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Now the Overlap errors are gone.

The SMD project still wont auto route, but that is covered in another section of this document.



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Autorouting a SMD DeviceImportant:Select the Auto route tool and save the default settings for future use.

Change autoroute parametersChange Routing Grid from 50 to 25 (our chip has a smaller pin spacing)

The test project now autoroutes, but the routes are obviously not optimized.

To ripup all routes, choose Ripup, then the green stoplight icon.



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Stop Mask Errors

After replacing the 74LVC4245 part with the LVC4245 part in the PIC_kludge schematic, perform ERC.Switch to the Board layerPerform DRC.541 Stop Mask errors. Oh joy!

Simplify the problem.Create another test project.Load testLVC4245Notice that not all layers are shown.Turn on all layers and re-run DRCNow we have multiple Stop Mask errors. Consistent.



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Increasing Min and Max values increases the number of Stop Mask errors.Setting both to 0 does not eliminate Stop Mask errors.Changing 100% to 50% does not reduce the number of Stop Mask errors.

Are these really important?

http://www.cadsoftusa.com/version50.htm

The DRC now reports an error if an object in the t/bPlace, t/bNames or t/bValues layer overlaps with an object

in the t/bStop layer (provided these layers are active when the DRC is run).

This is odd behavior.

So in the Board view, we choose Layers and display None.Then select layers: Top, Bottom, Pads, Vias, tStop, bStop, Drills, Holes. We dont care if the solder mask

overlaps the silkscreen.

Run DRC again and we have no errors.

So we can probably safely ignore stop mask errors, if all layers are turned on.

http://www.cadsoftusa.com/version50.htmhttp://www.cadsoftusa.com/version50.htmhttp://www.cadsoftusa.com/version50.htm


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Value as Text in Layer 27If the component value is in the wrong location, use Info and remove the value, then add Text in layer 27 (tValue),which we will include in the top silkscreen.

If you are adding text, type the text in the box, then adjust the size and ratio, before pasting.

Changing Header NumberingThe numbering of the headers did not match the numbering of the PIC chip. Lets make some new parts, withoutnumbers.

Eagle Control PanelFile Open Library: con-lstaPackage: FE20Group allCut

GoFile New (Library)Package: New: CON-20Paste from clipboardFile Save-as con-bob (.lbr)Delete the 1 and 20 from layer 21 (tPlace)Re-Open con-lsta.lbrCopy (group-all, cut, go) the Symbol FE20-1Symbol: New: CON-20Paste from clipboardShow all layers (each pin is numbered in sequence, with direction Pas and swap level 1)Save libraryOpen device: New: CON-20

Add Symbol CON-20New: Variant: A (anything here)Connect: G$1.1-1, G$1.2-2, etc.Save library

Open PIC_kludge_2.schReplace connectors on each side of the PIC chip with the new CON-20.We remove the value of each connector, to remove clutter.We move the connectors back into position, since the origin of the original part did not match the origin of the part wemade.We run DRC and correct any routing errors caused by moving these connectors. Rip up the old route before manuallyplacing the new one. Start at one end of the air wire and work toward the other end.



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Now we can place Text on the Top silkscreen layer to help identify the PIC pins.

Repeat the process for the LVC4245 socket connector.

Dimension wont DeleteIf the autorouter adds a via, which you cannot delete, we can remove wires and net names from the schematic until the

via disappears on the board view. The better approach is to Ripup All, then use Restrict layers to fool the Auto router.

However, the drill (dimension layer 20) is still present. How to delete it?

Before we lose all this work, close the board view, save schematic as PIC_kludge_2.sch. Now regenerate a new board tosee if the extra via dimensions are still there.

Realizing that placing the parts was taking too long, I created a temp folder, copied PIC_kludge.brd into the folder,renamed it to PIC_kludge_2.brd, and copied it back to the PIC_kludge project folder. With PIC_kludge_2.sch open, Iopened the .brd file and magically the extra dimension marks (drills from deleted vias) were not there. Much faster thanstarting from scratch.

Manual routing tr icks:To change a route, rip up the entire trace between endpoints, then route the airwire. Otherwise the schematic and boardwill not be consistent.

You must start at an end of an airwire. Then you can pick your route and the airwire follows the tip of the manual route.

In moving a route, when trace is too long, use the Split tool to force a new direction for the route, in the middle of the longtrace

Panelizing BoardsThese techniques worked better in Windows than linux. Your mileage may vary.

http://claymore.engineer.gvsu.edu/~steriana/Python/gerbmerge/ http://gerbv.sourceforge.net/
http://claymore.engineer.gvsu.edu/~steriana/Python/gerbmerge/http://claymore.engineer.gvsu.edu/~steriana/Python/gerbmerge/http://gerbv.sourceforge.net/http://gerbv.sourceforge.net/http://gerbv.sourceforge.net/http://claymore.engineer.gvsu.edu/~steriana/Python/gerbmerge/

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PC Board Design Example v2

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